JPH0342019B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a self-resetting superconducting loop circuit constructed using Josephson junctions and superconducting striplines.

(Prior Art and its Problems) A superconducting loop circuit consisting of a Josephson junction and a superconducting strip line, which is conventionally used in a Josephson memory circuit, has the configuration shown in FIG. The superconducting loop circuit in the figure operates as follows.
When input current I _S is passed through input line 11 with gate current Ig flowing from gate current path 12, gate 1
0 switches to voltage state. When gate 10 switches to voltage state, gate current Ig flows through superconducting loop circuit 13. Gate 10 is reset to a zero voltage state as the bias current decreases. On the other hand, the superconducting loop circuit 13 has inductance and the resistance component is zero, so the following equation holds true.

LdI/dt=V where L: inductance, V: voltage on both sides of inductance, I: current flowing through inductance, t: time When gate current Ig flows toward the superconducting loop circuit and gate 10 is reset to zero voltage state, Since the voltage on both sides of the inductance becomes zero and dI/dt=0, the gate current Ig continues to flow toward the superconducting loop circuit 13. When the gate current Ig becomes zero from this state, the current flowing through the superconducting stripline having the above-mentioned inductance is conserved when the voltage across the superconducting stripline is zero, so the superconducting loop circuit 13 A circulating current continues to flow through the circuit formed by the gate 10 and the gate 10. Therefore, even if the gate current becomes zero, this superconducting loop circuit 13 is not reset to its original state. Conventionally, a reset gate 14 is used to reset the circuit.
is connected in series with the superconducting loop circuit 13, a reset signal is applied from the outside using the reset input circuit 15, and the reset gate 14 is switched to a voltage state, thereby generating a voltage across the inductance and closing the closed circuit. The circulating current flowing through the circuit was reset to zero. The zero current state here is
A state in which the current is so small that its effect on the subsequent operation of the circuit is the same as when the current is zero.

However, the reset method using the reset gate 14 shown in FIG. 1 requires an external circuit for generating a reset signal. The circuit that generates this reset signal uses the gate current Ig that drove the gate 10.
It must be driven during a period when the power supply for gate 10 is zero, and a power supply having time dependence different from the power supply for driving gate 10 must be used. Furthermore, a timing control circuit for determining the time at which the reset signal is applied is also required, which has the disadvantage of complicating the circuit.

(Object of the Invention) An object of the present invention is to provide a self-resetting superconducting loop circuit using a superconducting circulating current, which eliminates the above-mentioned conventional drawbacks.

(Structure of the Invention) According to the present invention, a first switch is constructed by connecting one or more switches in series using Josephson junctions, and is switched by a current applied to an input line.
a superconducting loop circuit consisting of a gate, a second gate using a Josephson junction having a magnetically coupled input line, and a superconducting stripline having an inductance, the first gate and the superconducting A first gate current path configured of a gate current path that supplies a gate current to a loop circuit, and in which input lines of the first gate and the second gate are coupled in series.
A self-resetting superconducting loop circuit using a superconducting circulating current, characterized in that a second current path in which a current path, a superconducting loop circuit, and a second gate are connected in series are connected in parallel. is obtained.

(Example) The details of the present invention will be explained below using the drawings.

FIG. 2 is a diagram showing a first embodiment of the present invention, in which reference numerals 20 and 24 indicate magnetically coupled quantum interferometer gates. 22 is a gate current path through which a gate current Ig flows. 21 is the input line of gate 20 and gate 2
0 and magnetically coupled. 25 is gate 20
is the input line of gate 24 coupled in series with . 23 is a superconducting loop circuit consisting of a superconducting stripline having an inductance L, and is connected in series with the gate 24. Also gate 20
A first current path in which the input line 25 of the gate 24 is connected in series and a second current path in which the superconducting loop circuit 23 and the gate 24 are connected in series are connected in parallel.

In the circuit shown in Figure 2, the gate current Ig and the input current I _S
are run in the time relationship shown in Figure 3. After passing the gate current Ig at time t ₁ , the input line I _S flows at time t ₂ .
is input, the gate 20 starts the switch, and the current I _L is applied to the superconducting loop circuit 23 at time t ₃ , which is the sum of the switching time of the gate 20 and the current transfer time, time t ₂ after time t ₂ . appear. This current I _L becomes the gate current of the gate 24. On the other hand, if the current flowing in the input line 25 of the gates 20 and 24 is I _A , I _A appears at time t ₁ when the gate current Ig is input, and at time t ₃ when the gate current Ig flows toward the superconducting loop circuit 23. becomes zero. When the gate 20 is reset to the superconducting state by decreasing I _A , the voltage across the inductance of the superconducting loop circuit 23 becomes zero and the current I _L is conserved. Therefore, even if the input current _IS becomes zero at time _t4 , the currents I _L and I _A are not affected. When the gate current Ig becomes zero at time _t5 , the current flowing through the superconducting loop circuit 23 is conserved, so the superconducting loop circuit 23
A circulating current flows through a closed circuit in which the gates 20 and 24 are connected in series. This circulating current causes I _L and I _A to become I _A
= _−IL . As a result, the gate current and the input current flow through the gate 24 through the input line 25, and the gate 24 switches to a voltage state. gate 24
When a voltage is generated, the circulating current flowing in the closed circuit becomes zero state after a time _t2 after time _t5 , and the circuit is reset. Here, the time _t2 is determined from the switching time of the gate 24 and the circuit constant of the closed circuit. Also, the gate 24 has its gate current I _L
becomes zero, so it is reset to a superconducting state.

FIG. 4 shows the threshold characteristics of the gate 24, with the current I _L on the vertical axis and the current I _A on the horizontal axis. 2nd above
Gate current Ig shown in Fig. 3 in the circuit shown in Fig.
To explain the operation based on the time relationship of the input current I _S using FIG. 4, the operating point that initially was at point 40 at time t ₀ changes to time t ₁ due to the input of the gate current Ig.
moves to point 41 at time t3, and moves to gate 20 at time _t3 .
The switch moves to point 42. As the gate current Ig becomes zero, the operating point moves to point 43 at time _t5 , and the gate 24 switches.
When the gate 24 switches, the currents I _A and I _L both become zero, so the operating point returns to point 40.

FIG. 5 shows a second embodiment of the invention. The gate 50 is a current injection type quantum interferometer gate, and the gate 52
5 is a gate current path that supplies a gate current Ig to the gate 50; 51 is an input line that supplies an input current to the gate 50; 53 is a superconducting loop circuit consisting of a superconducting stripline having an inductance L;
4 is a gate consisting of a single Josephson element connected in series with the superconducting loop circuit 53; 55 is an input line of the gate 54 and connected in series with the gate 50; Resistors 56 and 57 are connected to gate 5, respectively, to ensure the transfer of current to superconducting loop circuit 53 by the switch in gate 50 and the reset of the current to a zero state by the switch in gate 54.
A damping resistor coupled in parallel with 0,54. The difference between the first embodiment shown in FIG. 2 and the embodiment shown in FIG. 5 is that the magnetically coupled quantum interferometer gate of the gate 20 is replaced by the current injection quantum interferometer gate of the gate 50. , the magnetically coupled quantum interferometer gate of gate 24 is a single Josephson junction of gate 54 , and the damping resistor 56 is coupled to gate 50 and the damping resistor 57 is coupled to gate 54 in parallel. . Therefore, the circuit operation of the second embodiment is similar to that of the first embodiment.

The above embodiments have been described on the assumption that the sum of the inductances of the superconducting loop circuit 23 and the gate 24 is sufficiently larger than the sum of the inductances of the gate 20 and the input line 25 of the gate 24. If the circuit of the present invention is actually used in a driver circuit or a sense bus circuit of a memory circuit, the inductance of the superconducting loop circuit 23 will be several hundred times larger than the sum of the inductances of the input lines 25 of the gates 20 and 24, approximately. The above assumption holds true. On the other hand, if the above assumption does not hold, then the sum of the inductances between the superconducting loop circuit and the gate 24 is aL ₀ , and the sum of the inductances between the gate 20 and the input line 25 of the gate 24 is bL ₀ , and a
Consider the case where and b have similar values. The gate current Ig flows through both inductances at time t ₁ shown in Figure 3 in inverse proportion to the ratio of the inductances, so if the current flowing through the inductance of aL ₀ is 1/aI ₀ , then the inductance of bL ₀ is 1/bI. ₀ current flows. At time _t3 , all current flows toward the inductance of aL ₀ , so the magnetic flux created by the current flowing through the inductance of aL ₀ is aL ₀ (1/a+1/b)I
It becomes ₀ . At time t ₅ , the magnetic flux of the superconducting loop circuit is conserved, so the inductance aL ₀ ,
The circulating current flowing through bL ₀ is a(1/a+1/b)/a+bI ₀ or 1/bI ₀ . The gate 24 shown in FIG.
If the current flowing from the direction toward the input line 25 of the gate 24 is positive, when the gate current is 1/aI ₀ and the input current is 1/bI ₀ at time t ₁ , no switch occurs, and at time t ₃ It is necessary to switch when the gate current is 1/bI ₀ and the input current is -1/bI ₀ .

Therefore, when a>b, the gate 24 may be left as is, but when a<b, it is necessary to replace the gate 24 with a gate having an asymmetric threshold characteristic as shown in FIG. Figure 6 shows a gate with asymmetric threshold characteristics used for the gate 24, where the horizontal axis shows the current I _A flowing through the input line 25 of the gate 20 and gate 24, and the vertical axis shows the superconductivity. A current I _L flows through the loop circuit 23 and gate 24. Point 60 in FIG. 6 is the operating point at time _t0 in FIG. 3, point 61 is the operating point at time _t1 , point 62 is the operating point at time _t3 , and point 63 is the operating point at time _t5 . Further, a gate having an asymmetric threshold characteristic as shown in FIG. 6 can be used as the gate 24 even when a>b for the purpose of widening the operating margin.

FIG. 7 shows a third embodiment of the invention. The third embodiment, like the first embodiment shown in FIG. 2 gate 74, and the first input line 75 of the second gate. 76 is a second input line of the second gate, and an input current is supplied from the outside. In the third embodiment, the second gate 7
4 is provided with a second input line 76, and an input current of a constant value is always supplied from the outside, thereby making the operating margin wider than in the first and second embodiments.
This method is particularly effective when a gate with asymmetric threshold characteristics is used as the second gate 74.

In the embodiment described above, one switch using a Josephson junction was used as the first gate, but a gate in which a plurality of switches using Josephson junctions were connected in series as the first gate was used. It can also be used. In this case the input current I _S
If the circuit parameters are selected so that all switches switch simultaneously, the essential operation of the circuit is the same as that described in the above embodiment, but
By increasing the voltage generated across the first gate, the ability to drive current to the superconducting loop circuit increases, and the time for transferring current to the superconducting loop circuit can be shortened.

As is clear from the above explanation, the first gate has a resistor, such as a two-junction or three-junction magnetically coupled quantum interferometer gate, a current injection quantum interferometer gate, or a gate consisting of a single Josephson element. A gate with a Josephson junction that does not have to be used can be used. In addition, the second gate is a gate using a Josephson junction with a magnetically coupled input line without resistance, such as a two-junction or three-junction magnetically coupled quantum interferometer gate, or a gate consisting of a single Josephson junction. can be used.

(Effects of the Invention) As explained above, the self-resetting superconducting loop circuit using a superconducting circulating current according to the present invention has a higher power supply than the conventional circuit, which generates an external reset signal, a power supply for driving the reset signal generating circuit, and a reset signal. This eliminates the need for a timing circuit to provide the timing for generating , and has advantages such as miniaturization of the circuit, ease of design, increased operating margin, and shortened operating time since no timing circuit is required.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a conventional example. FIG. 2 shows a first embodiment of the invention.
Figure 3 shows the gate current Ig and input current in the example.
It shows the time dependence of I _S , the current I _L flowing through the superconducting loop, and the current I _A flowing through the first gate.
Figure 4 shows the threshold characteristics of the gate used as the second gate in the first embodiment, where the horizontal axis is the current I _A flowing through the first gate, and the vertical axis is the current I flowing through the superconducting loop. It is _L. FIG. 5 shows a second embodiment of the invention. Figure 6 shows the threshold characteristics of a gate with asymmetric threshold characteristics, where the vertical axis is the current I _L flowing in the superconducting loop,
The horizontal axis is the current I _A flowing through the first gate. 7th
The figure shows a third embodiment of the invention. In the figure, 10...gate using Josephson junction, 11...input line, 12...gate current path, 13...superconducting loop circuit, 14...reset gate, 15...reset input line, 20...
...first gate, 21 ... input line of first gate, 22 ... gate current path, 23 ... superconducting loop circuit, 24 ... second gate, 25 ... input line of second gate , 40...Operating point at time _t0 in Fig. 3, 41...Operating point at time _t1 in Fig. 3, 42...Operating point at time t3 in Fig. ₃ ,
43...Operating point at time _t5 in Fig. 3, 50...
...first gate, 51 ... input line of first gate, 52 ... gate current path, 53 ... superconducting loop circuit, 54 ... second gate, 55 ... input line of second gate , 56...damping resistance, 5
7...Damping resistance, 60...Time t ₀ in Figure 3
61...Operating point at time _t1 in Fig. 3, 62...Operating point at time t3 in Fig. ₃ , 63...Operating point at time _t5 in Fig. 3, 7
0...first gate, 71...first gate input line, 72...gate current path, 73...superconducting loop circuit, 74...second gate, 75...second gate First input line, 74... second input line of the second gate.

Claims (1)

[Claims] 1. A first gate configured by one or more switches using Josephson junctions connected in series and switched by a current applied to an input line;
a superconducting loop circuit consisting of a second gate using a Josephson junction having a magnetically coupled input line and a superconducting stripline having an inductance; and a gate connected to the first gate and the superconducting loop circuit. a first current path consisting of a gate current path that supplies current, and in which the input line of the second gate and the first gate are coupled in series;
A self-resetting superconducting loop circuit using a superconducting circulating current, characterized in that a second current path in which the superconducting loop circuit and the second gate are coupled in series is coupled in parallel.