JPH0342746A - Duplex device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of system performance by providing respectively duplexed central controller and a main storage device and providing address/data reception buffer circuits, buffer number '0' display circuits and collating starting/dissidence detection circuits for respective main storage devices. CONSTITUTION:The collating starting/dissidence detection circuits 250 holds addresses which is read out with the central controllers 10 and 11 and reading data and transmits them to a main storage device 20 (21) on an opposite-side when data to be copied in the address/data reception buffer circuits 230 does not exist based on the display of the buffer number '0' display circuit 240. When the address and data are received from the main storage device 20 (21) on the opposite side, the memory content of a self system is read and coincidence/dissidence of the address and data, which are transmited from the other system is detected. When they are dissident, it is reported to the central controllers 10 and 11.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing device, and more particularly to a device for collating the contents of a duplicated storage device.

(Prior Art) Conventionally, in order to check the content between dual main storage devices, the content read from one storage device is transferred to the other based on the address read from the main storage device by a central control unit. There is a well-known method for comparing and verifying the contents read from the main storage device. However, when the address used to read the contents of the main memory from the central control unit and the read data are received, the demta read from the other main memory does not match. It is necessary to check whether the At this time, both data must be compared faster than the central controller can read/write. If the verification speed is slower than the read/write speed of the central controller, the access speed of the central controller must be limited.

(Problem to be Solved by the Invention) In the above-mentioned conventional system including the duplicated main storage devices, checking the contents between the duplicated main storage devices becomes a limiting factor in the performance of the central controller. Ta. As a result, no matter how fast the central controller can execute instructions, the operating clock of the central controller must be slowed down to perform match/mismatch verification tests, which degrades system performance. There is a drawback.

An object of the present invention is to have dual main storage devices and dual central control devices, and to read/write data from the central control device to one main storage device and to the other main storage device. A system that copies written data, which has a buffer in the main memory to store the address and data for the copy, and when there is no data to be copied in the buffer, the memory contents of both systems are In order to guarantee a match, the central control unit holds the read address and read data and sends it to the main memory of the other party, and the main memory of the other party receives the address and data for which mismatch should be detected. The system reads the memory contents of its own system, detects the match/mismatch between the address and data sent from the other system, and reports the mismatch to the central control unit to eliminate the above drawbacks and reduce system performance. The object of the present invention is to provide a duplex device configured such that there is no problem.

(Means for Solving the Problems) A duplexing device according to the present invention includes a duplexed central control unit and a duplexed main storage device, reads/writes data in the first main storage device, and reads/writes data in the second main storage device. It is configured so that data can be copied in the main storage device. In accordance with the above configuration, each main memory device includes an address/data reception buffer circuit, a buffer number O display circuit, and a verification activation/discrepancy detection circuit.

The address/data reception buffer circuit is for storing address data and data for data copying.

The buffer number O display circuit is used to indicate the state when there is no data to be copied in the address/data reception buffer circuit.

The verification activation/mismatch detection circuit detects when there is no data to be copied in the address/data reception buffer circuit.
In order to ensure that the memory contents of both systems match, the central control unit holds the read address and read data and transmits it to the main memory of the other side, and also transfers the address and data from the main memory of the other side. When received, it reads out the memory contents of its own system and detects whether the address field and data sent from the other system match/mismatch, and if they do not match, it reports to the central control unit.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a duplexing device according to the present invention.

In FIG. 1, 10.11 is the central control unit,
20 and 21 are main storage devices, respectively.

Since this embodiment is duplexed, the central controller 10 and the main memory 20 are used to store the first 0 system, the central controller 11
and the main storage device 21 constitute a second system.

In the 0 system, the central controller 10 and the main memory 20 are connected via a signal line 30 to form an address/data bus (BUS), and in the 1 system, the central controller 10 and the main memory 20 are connected to each other via a signal line 30 to form an address/data bus (BUS).
1 and the main memory 21 is an address/data bus (,
BUS) and are connected by a signal line 31.

The 0-system main storage device 20 and the 1-system main storage device 21 are connected to an address/data bus (MBUS) for data copying.
are connected by a signal line 32 and further connected by a signal line 33 to form a signal line.

The signal line 33 carries a QZERO signal indicating that the address/data input to the copy buffer is 0.

The main storage device 21 of the 1st system and the central control device 1° of the θ system are connected by a signal line 41 for carrying the UNM signal, and the main storage device 20 of the 0th system and the central control device 11 of the 1st system are connected by a signal line 41 for carrying the UNM signal. 2 and 2 are connected by a signal line 40 for carrying the UNM signal. The UNM signal is a signal that reports a mismatch to the central controller 10.11.

FIG. 2 is a block diagram showing an example of the internal configuration of the main storage device 20 shown in FIG. 1.

In FIG. 2, 200 is a memory access receiving circuit;
10 is a DRAM element, 220 is an address/data output circuit, 230 is an address/data receiving buffer circuit, 24
0 is a buffer number O display circuit, and 250 is a verification activation/mismatch detection circuit.

The main storage device 20 includes a memory access receiving circuit 200 and a D
RAM element 210 and address/data output circuit 220
, an address/data reception buffer circuit 230 , a buffer count O display circuit 240 , and a verification activation/mismatch detection circuit 250 .

FIG. 3 is a conceptual diagram showing the data copy operation in FIG. 1.

In FIG. 3, 200.201 is a memory access receiving circuit, 210.211 is a DRAM element, 220.221 is an address/data output circuit, and 230 is a DRAM element.
．． 231 are address/data receiving buffer circuits, 240 and 241 are buffer number O display circuits, and 2
50 and 251 are verification activation/mismatch detection circuits, respectively.

The main storage device 2 is connected from the central control device 10 via the signal line 30.
When a write instruction is sent to 0, the write instruction is received by the memory access receiving circuit 200. When data is written to the main memory device 210, the address/data output circuit 220 simultaneously sends data to the main memory device 210 via the signal line 32.
A write instruction is sent at 7 for 1. Main storage device 21
Then, the write instruction, write address, and write data are stored in the address/data reception buffer circuit 231.

The main memory device 21 retrieves the write information stored in the address/data reception buffer circuit 231, and
Write to 11. As a result, the same data is written to the same address in the main memory devices 20 and 21.

Address/data reception buffer circuit 2 in main memory 21
31, the main memory devices 20.21 can operate asynchronously, and on the copying side, the DRAM elements operate at low speed, and the central control device 10.11
In systems that are directly accessed (i.e., execution systems), DRAM
The device operates at high speed.

When the execution system is not under high load, there are few write operations on the execution system. At this time, the number buffered in the copy address/data reception buffer circuit 231 is almost zero. In such a case, the address/data receiving buffer circuit 231 for copying may overflow.
I have plenty of time. On the other hand, on the copying side, the contents of the address/data reception buffer circuit 230 are empty. At this time, by checking the memory contents\
It is possible to check the contents of the main memory without affecting the execution system.

FIG. 4 is a conceptual diagram showing the operation when the contents of the address/data receiving buffer circuit in FIG. 1 are empty.

In FIG. 4, elements shown in FIGS. 1 and 3 are numbered similarly to those shown in FIGS. 1 and 3.

When the contents of the address/data reception buffer circuit 231 are empty, no data exists therein, so this state is detected by the buffer number 0 display circuit 241. As a result, it is displayed on the signal line 33 carrying the QZERO signal that the contents of the address/data reception buffer circuit 231 are empty.

Therefore, the buffer number 0 display circuit 240 receives the above state, and the memory access receiving circuit 200 operates in the verification check mode. In the memory access receiving circuit 200 operating in the verification check mode, the central controller 10
The address output from the central controller 10 when reading is received.

Similarly, read data from main memory 210 is received by memory access receiving circuit 200, and address and read data are received by memory access receiving circuit 200 from address/data output circuit 220.
The signal is sent to the main storage device 21 via the US signal line 32'f.

On the other hand, in the main memory device 21, the internal verification activation/mismatch detection circuit 251 is activated to receive the address, and then data is read from the DRAM element 211 using the received address. The data sent out via I7 via the MBUS signal line 32 and the data read from the DRAM element 211 are checked by the comparison activation/mismatch detection circuit 251 in the main memory 21. If it turns out that the two are inconsistent,
The verification activation/mismatch detection circuit 251 sends a mismatch report signal UNM to the central controller via the UNM signal line 41.

(Effects of the Invention) As explained above, the present invention utilizes the timing when the contents of the address/data reception buffer circuit are empty to start the verification timing between the duplicated main memories, thereby performing the verification operation. Since it uses the free time of the main memory, it has the effect of collating the contents between the duplicated main memories without impairing information processing capacity.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a duplexing device according to the present invention. FIG. 2 is a block diagram showing an example of the internal configuration of the main storage device shown in FIG. 1. FIG. 3 is a conceptual diagram showing a data copy operation similar to FIG. 1. FIG. 4 is a conceptual diagram showing the operation when the address/data receiving buffer circuit shown in FIG. 1 is empty. 1o, ii...Central control unit 20.21...Main storage device 200.201...Memory access receiving circuit 210.
211...DRAM element 220.221...Address/data output circuit 230, 231・0 Tufa circuit 240.241・・250.251・・Road 30 to 33, 40°・Number of address/data reception bars/buffers 0 display circuit/verification start/mismatch detection circuit/signal line

Claims (1)

[Claims] It is equipped with a duplicated central control unit and a duplicated main memory, and is configured such that data can be read/written in the first main memory and the data can be copied in the second main memory. a duplexing device, wherein each of the main storage devices includes an address/data reception buffer circuit for storing the address and data for the data copy, and the data to be copied does not exist in the address/data reception buffer circuit. Sometimes, there is a buffer number 0 display circuit to indicate the state, and when the data to be copied does not exist in the address/data reception buffer circuit, the central control unit reads the data to ensure that the memory contents of both systems match. It holds the received address and read data and sends it to the main memory of the other party, and when the address and data are received from the main memory of the other party, it reads the memory contents of its own system and sends them from the other system. What is claimed is: 1. A duplexing device comprising: a verification activation/mismatch detection circuit for detecting coincidence/mismatch of addresses and data and reporting to a central control unit in the event of a mismatch.