JPH0342747B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an imaging device that can effectively suppress blooming.

(Prior art) Conventionally, as shown in Japanese Patent Application Laid-Open No. 138371/1983,
To prevent blooming in solid-state image sensors such as CCDs, overflow and
Instead of providing a drain, a method is being considered that utilizes surface recombination to eliminate excess carriers.

This method has advantages such as high sensitivity because it does not sacrifice the aperture ratio in the light-receiving surface, and higher horizontal resolution because the degree of integration can be improved.

1 to 3 are diagrams for explaining a blooming prevention method using such surface recombination, and FIG. 1 is a front view of a general frame transfer type image sensor.

In the figure, reference numeral 1 denotes a light receiving section, which is composed of a plurality of photosensitive vertical transfer registers.

Further, reference numeral 2 denotes a storage section, which is composed of a plurality of vertical transfer registers that are shielded from light.

Reference numeral 3 denotes a horizontal transfer register; the information in each vertical transfer register of the storage section 2 is transferred by one bit at the same time to the horizontal transfer register, and then the video signal is transferred from the output amplifier 4 by causing the register 3 to perform a horizontal transfer operation. can be obtained. OB is a vertical transfer register section that is vertically shielded from light and is called an optical black.

Generally, the information formed in each vertical transfer register of the light receiving section 1 is vertically transferred to the storage section 2 during the vertical blanking period in the standard television system, and is sequentially transferred from the horizontal transfer register 3 within the next vertical scanning period. It is read line by line.

Here, it is assumed that the light receiving section 1, the storage section 2, and the horizontal transfer register 3 are each driven in two phases, and the respective transfer electrodes are _P1 , _P2 , _P3 , _P4 , _P5 , _P6 , The transfer clocks are (φ _P1 , φ _P2 ), (φ _P3 , φ _P4 ), (φ _P5
，
φ _P6 ).

FIG. 2 is a diagram showing the potential profile under such transfer electrodes _P1 to _P6 . For example, by applying a low level voltage -V ₁ to the electrodes P ₂ , P ₄ , P ₆ , the electrodes P ₁ , P ₃ , P When a high level voltage V ₂ is applied to ₅ , a potential as shown by the solid line in the figure is formed. Moreover, the electrode P ₁ ,
A low level voltage V ₁ is applied to P ₃ and P ₅ , and the electrodes P ₂ and
When a high level voltage V ₂ is applied to P ₄ and P ₆ , a potential as shown by the broken line in the figure is formed.

Therefore, by applying alternating voltages with opposite phases to electrodes P ₁ , P ₃ , P ₅ and electrodes P ₂ , P ₄ , P ₆ , carriers are sequentially transferred in one direction (rightward in the figure). .

In addition, the dashed-dotted line in the figure indicates a large positive voltage V ₃ at the electrode.
This shows the potential when .

FIG. 3 is a diagram showing the shape of the electrode voltage and internal potential in the thickness direction of the semiconductor substrate 6. As shown in the figure, for electrode voltage _V3 , the potential well becomes shallow and excess carrier becomes a second state in which it recombines with majority carriers at the interface with the insulating layer.

On the other hand, when the electrode voltage is _-V1 , the first state is an accumulation state, and a large number of carriers tend to gather around the interface, and the large number of carriers are supplied from, for example, a channel stopper region (not shown).

Therefore, for example, when a barrier is formed by applying voltage -V ₁ to electrode P ₂ , by alternately applying voltages -V ₁ and V ₃ to electrode P ₁ , the electrode
The minority carriers accumulated under _P1 are limited to a predetermined amount or less.

However, in order to effectively eliminate excess carriers, accumulation states and inverted states must be formed alternately and at high speed in the semiconductor substrate during the accumulation period, which reduces power consumption. The problem is that it is large. Furthermore, when such pulse control is performed at high speed, there is a problem in that noise caused by the pulses is mixed into the signal.

FIGS. 4a and 4b are diagrams for explaining such a problem. In the figure, 100 is a part of a driver circuit which will be described later, and it operates at a predetermined P according to the timing of a pulse Ψ _AB from a clock generator which will also be described later.
(Peak) - P (Peak) level -V ₁ , V ₃ drive pulses (hereinafter referred to as AB pulse φ _AB ) are supplied.

101, 109 are differential capacitors, 102,
108 is a bias diode, 104, 107
is a transistor, 103 and 106 are smoothing capacitors, and 105 is a capacitor formed between the electrodes _P1 .

FIG. 4b is a diagram showing waveforms at various parts. The operation of FIG. 4a will be explained based on FIG. 4b.

When the pulse Ψ _AB is input as shown in b in the same figure, the transistor 107 is turned on at the rising edge, and the power supply -V ₁ is applied to the capacitor 105 through which the current i _AB flows from the capacitor 105 toward the power supply -V ₁ . It will be charged.

Further, at the rising edge of the pulse Ψ _AB , the transistor 104 is turned on and the power supply +V ₃ is applied to the capacitor C, which is charged with this voltage V ₃ . In this case, since the interelectrode capacitance 105 equivalently has an input capacitance of several thousand PF, when pulses of voltages -V ₁ and V ₃ (hereinafter abbreviated as _AB pulse φ ) will flow. When this current flows through the silicon substrate of the image sensor, the resistance of the silicon substrate is several tens of mΩ, so it ends up being several tens of mV.
noise (referred to as AB noise here). In order to reduce this noise, there are ways to reduce the absolute value of the differential current by reducing the resistance of the silicon substrate or by making the rise and fall characteristics of the AB pulse gentler, but these methods also AB noise of several mV remains.

By the way, the standard level of the signal output from the image sensor is usually several hundred mV, and if the dynamic range at the time of imaging is set to about four times the standard signal level, the general video signal level is still about
It will be on the order of 100mV.

Therefore, in general movie imaging, the above-mentioned AB noise appears on the screen to an extent that cannot be ignored, especially when the subject is dark.

Further, in general, the output signal of the image sensor is clamped as a black reference signal by a DC reproducing circuit called a clamp circuit, in which a signal corresponding to the optically shielded portion OB is used. If a pulse is supplied during the period of this black reference signal, AB noise will be superimposed on the black reference signal. Therefore, when this signal is clamped, fluctuations in the clamp potential occur due to the AB noise, resulting in line-like low frequency noise on the display, significantly degrading the image quality.

The motorization rate of this clamp potential is the standard signal level (100mV) mentioned above and the AB noise level (several mV).
Although it is not determined by the ratio of V) alone, it was confirmed that even if clamp effects, gamma characteristics, etc. are considered, noise of several tens of mV remains at the NTSC signal level.
In addition, this phenomenon is especially true when the AB pulse φ _AB is
In the case of synchronization (for example horizontal synchronization) and asynchronous, or when the repetition period of AB pulse is changed according to the brightness level of the subject, or when the phase of clamp pulse and AB noise changes, etc. Significant. In this case, there was a drawback that the brightness level changed over several H times.

(Objective) It is an object of the present invention to provide an imaging device capable of accurate clamping that can eliminate the drawbacks of the above-mentioned techniques.

Another object of the present invention is to provide an imaging device that contains less AB noise, consumes less power, and is highly effective in preventing blooming.

Still another object of the present invention is to provide an imaging device that can effectively suppress deterioration of video signals due to AB noise.

(Example) The present invention will be explained below based on Examples.

FIG. 5 is a diagram showing an example of an imaging device using an imaging element according to the present invention. In this example, the sixth and seventh
A case in which a single-phase drive type frame transfer type CCD as shown in the figure is used will be explained.

In the figures, the same reference numerals as in FIGS. 1 to 4 indicate the same elements. IS is a CCD image sensor as an imaging means. In this embodiment, together with the transfer clock φ _PI to the light receiving section 1, _{an AB} pulse φ
is applied.

Furthermore, transfer clocks φ _PS and φ _S are applied to the storage section 2 and the horizontal transfer register 3, respectively.

506 is the above transfer pulse φ _PI , φ PS , φ S necessary for transfer of this CCD image sensor and the above-mentioned transfer pulse φ PI , φ _PS , φ _S
A driver circuit 507 serves as a reading means for supplying AB pulses φ _AB , and 507 is a first clock circuit that forms timing signals Ψ _PI , Ψ _PS , Ψ _S of φ _PI , φ _PS , φ _S among these pulses. It is a rater.

514 is a second clock generator as a recombination control means, and based on the timing signal Ψ _AB of the clock generator 514, the driver circuit 506 forms an AB pulse φ _AB ,
It is supplied to the electrode P _AB of the image sensor described later.

Reference numeral 508 is a reference oscillator, and 509 is a horizontal clock counter, which counts output pulses of the oscillator 508 and forms horizontal synchronization signals and the like. A vertical clock counter 510 counts the horizontal synchronizing signal output from the horizontal clock counter 509 and outputs a vertical synchronizing signal and the like.

511 is a decoder, and a counter 50
Various timing pulses are outputted according to the output state of 9,510.

That is, the driver circuit 5 outputs timing signals for the composite synchronization signal C・Sync, the composite blanking signal C・BLK, the transfer pulses φ _PI , φ _PS , φ _S, etc.
Supply to 06.

Further, the decoder 511 and the AND gate 513 form inhibiting means according to the present invention.

That is, by outputting the low level ENABLE-AB signal at the timing shown in Figure 9,
The output of the second clock generator is prohibited. 512 is a D flip-flop whose output is input to the D input terminal to form a frequency divider.

Further, the output of the oscillator 508 is input to the clock input of this flip-flop.

Also, the output of flip-flop 512 and
The logical product with the ENABLE.AB signal is AND gate 51
3 is formed as a timing pulse Ψ _AB .

Further, the decoder 511 outputs a clamp pulse CPOB to a clamp circuit 503, which will be described later, at a timing as shown in FIG. clamp pulse
Clamping operation is performed while CPOB is at high level.

In addition, the decoder 511 generates a sampling pulse synchronized with the horizontal transfer clock of the image sensor IS.
SUMP is output to the sample and hold circuit 502.

Also, among the outputs of the driver circuit 506, a composite synchronization signal C・Sync, a composite blanking signal C・
BLK etc. are supplied to the process circuit 504.

Further, the output of the process circuit 504 is sent to the recording device 50.
5.

FIG. 6 is a diagram schematically showing the electrode structure and potential in a cross section of the boundary area between the light receiving section 1 and the storage section 2 of the image sensor IS.

In the figure, P _PI is the transfer electrode that applies the transfer clock φ _PI of the light receiving section, P _AB is the recombination control electrode as a recombination means for applying the recombination clock φ _AB , and P _PS is the transfer clock φ of the storage section. The transfer electrode to which _PS is applied, the solid line in the figure indicates the potential state when a low level voltage is applied as φ _PI , φ _PS and a high level voltage is applied as φ _AB , and the broken line indicates φ _PI ,
This is when φ _PS is set to high level and φ _AB is set to low level.

Incidentally, a potential staircase as shown in the figure is formed in the substrate 6 by ion implantation. Also, 5
is an insulating layer. In addition, the lower part of the insulating layer that is not covered by the electrodes P _PI , P _PS , and P _AB , that is, the boundary between the insulating layer and the semiconductor substrate constitutes a virtual electrode, although it is not shown in the diagram. For example, a P-type inversion layer is formed for this purpose. Therefore, the potential in the semiconductor region not covered by the electrodes is not changed by the bias applied to each electrode.

FIG. 7 is a diagram showing an example of an electrode pattern in the area shown in FIG. CS is a channel stop and prevents horizontal charge movement. 5th~
According to the embodiment shown in FIG. 7, electrodes for charge recombination
Since the width of _PAB can be made sufficiently smaller than the width of transfer electrode _PPI , the removal efficiency can be increased when removing excess charge.

Furthermore, in a single-phase drive type CCD image sensor, the charge recombination operation can be performed independently of the transfer operation.

Moreover, the recombination control structure of the image pickup device of this embodiment can be formed using the polysilicon gate formation step for the electrode, which can be manufactured in the same process as the channel stop, and the ion implantation step for forming the internal potential steps.

FIG. 8 shows the clock pulses φ _AB , φ _PI , φ _PS , φ _S output from the clock driver 506 to drive the image sensor shown in FIG. 5 and the output of the amplifier 4.
A vertical blanking signal is generated between times t ₁ to _{t 3} and t ₄ to _{t 6} in synchronization with the vertical synchronizing signal V _D obtained for each television field, which is a waveform diagram of Voutl, etc.
V _BLK is output.

Further, H _BLK is a horizontal blanking signal. First, during the accumulation period from time t ₁ , t ₃ to _{t 4} , and t ₆ , the level of φ _PI is set to approximately the intermediate level between −V ₁ and V ₂ .
It is fixed at _V5 level (the state indicated by the dashed-dotted line in the sixth figure). Further, at the end of each accumulation period, whether to raise or lower φ _PI is switched for each field.

To explain this, during the accumulation period, φ _PI is reduced to V ₅
By setting the voltage level, potential wells are formed in the substrate under the transfer electrode P _PI (X region) and in the substrate under the virtual electrode (Y region), and charges are accumulated in each well.

As shown in FIG. 8, during a period slightly longer than each horizontal blanking period within this accumulation period, an AB pulse φ _AB
Multiple pieces are supplied. At this time, the potential below the electrode P _AB goes up and down, but when the potential goes down, the excess charge in the well is recombined with the hole and disappears when the potential goes up, and the charge in the adjacent well disappears. Does not leak.

Next, by supplying multiple pulses of φ _AB from time t ₁ to _{t 2} and from t ₄ to _{t 5} , excess charge immediately before vertical transfer is removed. Further, between times _t2 to _t3 and _t5 to _t6, clocks φ _PI and φ _PS of the same number as the number of pixels in the vertical direction of the light receiving section 1 and the storage section 2 are supplied in phase.
As a result, the charge in each pixel cell in the light receiving section 1 is transferred to the corresponding storage cell in the storage section.

At this time, in the present invention, the clock φ _AB applied to the recombination electrode P _AB is fixed at _V4 . This voltage V ₄ is the electrode
The voltage value is such that the potential level under P _AB is located between the upper and lower limits of the potential level of the virtual electrode section.

As described above, at the end of each accumulation period, whether to raise or lower φ _PI is switched for each field.

That is, let the amounts of charge entering the wells in the X region and Y region shown in FIG. 6 during the accumulation period of the first field up to time t ₁ in FIG. 8 be X _INT and Y _INT , respectively.
Next, during vertical transfer starting from time _t2 in FIG. 8, by raising _φPI from the intermediate level _V5 to the _V2 level at the beginning of the transfer,
The charges in the area enter the X area and are added, X _INT + Y _INT
Then, it is transferred to the storage section. Also, the second field changes φ _PI from the intermediate level V ₅ to − at the beginning of the transfer.
By lowering _V1 , the charge in the X area to the left of the Y area in FIG. 6 enters the Y area and is added. Interlace operation is performed by changing the combination of charges added for each field in this manner.

As a result, an interlacing effect can be achieved with a small number of pixels, and the dark current level does not change from field to field, making flickering less likely to occur.

When the vertical transfer is completed, the charges in the storage section are read out line by line in synchronization with the horizontal cycle by the clocks φ _PS and φ _S between times t ₃ - _{t 4} and t ₆ , and the horizontal line signal is is output as This period t ₂ ~ t ₃ , t ₆ ~
corresponds to the vertical scanning period of a standard television signal.

Next, FIG. 9 is a diagram showing detailed operation timing of the circuit shown in FIG.

By sequentially sampling and holding the dot sequential signal read from the image sensor IS in the sample/hold circuit 502, the duty of the dot sequential signal is widened. Therefore, this sample
The output Vout2 of the hold circuit 502 is as shown in FIG. Incidentally, here, the output of the light shielding part OB of the image sensor IS is obtained in the back porch of the horizontal blanking period H-BLK.

Further, the output of this sample and hold circuit 502 is clamped in a clamp circuit 503 by a clamp pulse CPOB shown in FIG. The output of the clamp circuit 503 is subjected to corrections such as γ correction and aperture correction in a process circuit 504, and is mixed with a composite synchronization signal and a composite blanking signal before being led to a recording device 505.

Further, in this embodiment, the output ENABLE AB of the decoder 511, which functions as an inhibiting means, causes the output of the clamp pulse CPOB to be at least at a high level (time t ₁₀ to t ₁₁ ), that is, while the clamp operation is performed, the AB pulse φ _AB is cut off, and a constant potential _-V1 is supplied.

Therefore, there is no possibility that the clamp level will fluctuate due to the noise (AB NOISE in FIG. 9) generated with the application of the pulse φ _AB .

Furthermore, in this embodiment, the variation of the AB pulse φ _AB is prohibited from a timing t ₉ , which is earlier than the timing t ₁₀ when the clamp pulse CPOB becomes high level, by a margin of time τ, to a certain time t ₁₁ at which the clamp ends. This is to prevent the falling part of AB noise from being mixed into the video signal during clamping.

Furthermore, in this embodiment, while the optical image is incident on the image sensor and stored, the diachronic AB pulse is not supplied, but is supplied almost only during the horizontal blanking period, which suppresses noise on the screen. obtain. Moreover, it is highly energy-saving.

Furthermore, in this embodiment, the period exceeding the horizontal blanking period (times t ₈ to t ₁₂ ) by several percent of the horizontal period
Since the AB pulse is applied from _t7 to _t13 , the blooming suppression effect is even greater.

That is, the first additional period t ₇ to _{t 8} immediately before the blanking period H-BLK and the second additional period t ₁₂ immediately after the blanking period H-BLK.
Since φ _AB is supplied even at ~t ₁₃ , blooming can be further prevented.

Furthermore, since the first additional period is longer than the second additional period, noise does not appear in the screen area of the receiver (IZ in FIG. 9). That is, generally the fifth illustrated circuit 50
2 to 504, etc., a time delay occurs in the signal in the process of processing the signal.

For example, a delay as shown in FIG. 9 between Vout2 and Vout3 occurs.

Therefore, when the period H-BLK is exceeded by several percent and φ _AB is supplied, if both the first additional period and the second additional period are the same length, the screen range
AB noise of the second additional period appears in IZ. Of course, if both the first and second additional periods are shortened, the image will not appear in the screen range, but the recombination ability will deteriorate accordingly. Therefore, in this embodiment, the first
Since the additional period of φ AB is made longer than the second additional period, the maximum amount of φ _AB can be supplied.

Furthermore, the pulse φ _AB is supplied for a predetermined period of time just before the frame transfer period, and excess charge immediately before the transfer is removed, so that smear does not occur.

In the above explanation, an example of a frame transfer type CCD using a single-phase drive method has been described, but it goes without saying that the present invention is similarly applicable to a CCD image sensor using a multi-phase drive method. or,
It is clear that the present invention is applicable not only to CCDs but also to all types of image sensors that convert image signals into charges and store them.

Furthermore, although this embodiment shows an example in which the frequency of the AB pulse is relatively high, this frequency may also be low, and in that case, the present invention can prevent fluctuations such as the rise and fall of this pulse during the clamp operation. This also includes those that prohibit the rise and fall of AB pulses to prevent them from entering.

(Effect) According to the present invention, φ _AB is operated only during the horizontal blanking period, the first additional period immediately before the horizontal blanking period, and the second additional period immediately after the horizontal blanking period, even during the accumulation period. Because it has a high power saving effect, the noise is not noticeable.

Furthermore, according to the present invention, stable clamping operation can be realized because φ _AB is not supplied during clamping operation during the horizontal blanking period.

The image sensor Noise is not added to the read signal from the receiver, and the power saving effect is high.Furthermore, no noise appears on the screen of the receiver, and the blooming prevention effect is also high.

[Brief explanation of drawings]

Figure 1 is a schematic diagram of a conventional CCD image sensor, Figure 2 is a diagram explaining the driving method of the sensor shown in Figure 1, Figure 3 is a diagram explaining the principle of surface charge recombination, and Figure 4 a is a diagram of the conventional CCD image sensor. FIG. 5 is a diagram showing a configuration example of the image pickup device of the present invention, and FIG. 6 is a structure of an image pickup device suitable for the image pickup device of the present invention. FIG. 7 is a diagram showing an example of the electrode pattern of the element shown in FIG. 5, FIG. 8 is a drive timing chart of the imaging device of the present invention, and FIG. 9 is a timing diagram of a clock driver. IS...Image sensor as an imaging means, 1
. . . Light receiving section, P _AB . . . Recombination control electrode as recombination means, 506 . . . Clock driver as control means.

Claims (1)

[Scope of Claims] 1. Imaging means having a plurality of light receiving sections for converting an optical image into charge information and reading out the charge information at a television cycle; and at least a portion of the charge information in each of the light receiving sections. signal supply means for applying a periodic signal to the electrodes in each of the light receiving sections for repeatedly recombining with charges of other polarity; and a part of the output of the imaging means during a horizontal blanking period of the television period. clamping means for clamping the period, and controlling the signal supply means to apply the periodic signal to the electrode during the horizontal blanking period excluding approximately the part of the period; the signal supply means for applying the periodic signal to the electrodes also during a first additional period immediately before the ranking period and a second additional period shorter than the first additional period immediately after the horizontal blanking period; An imaging device comprising: a control means for controlling.