JPH0342848A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0342848A
JPH0342848A JP1178566A JP17856689A JPH0342848A JP H0342848 A JPH0342848 A JP H0342848A JP 1178566 A JP1178566 A JP 1178566A JP 17856689 A JP17856689 A JP 17856689A JP H0342848 A JPH0342848 A JP H0342848A
Authority
JP
Japan
Prior art keywords
wiring board
semiconductor chip
electrode pad
semiconductor device
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1178566A
Other languages
Japanese (ja)
Inventor
Hiroki Ochi
越智 博樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1178566A priority Critical patent/JPH0342848A/en
Publication of JPH0342848A publication Critical patent/JPH0342848A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To conduct stable positioning among projecting electrode pads by connecting the electrode pad, one part of a nose of which is inserted into the through-hole of a wiring board, and the conductive layer of the electrode pad while forming a wiring shaped into an element forming layer. CONSTITUTION:In the semiconductor device, a projecting electrode pad 1 having a conductive layer 2 connected to wirings 7 in an element forming layer 8 formed onto a semiconductor chip 9 is shaped, and conductive layers 6 are formed onto the inwalls and surfaces of the through-holes 5 of a wiring board 4. According to such structure, even when the semiconductor chip 9 is loaded on the wiring board 4, the projecting electrode pad 1 of the semiconductor chip 9 is inserted to the edge sections of the through-holes 5 of the wiring board 4, and connected by the conductive layers 6 and the conductive layer 2. As a result, the semiconductor chip 9 is positioned automatically by the electrode pad 1 and the through-holes 5 on loading. Consequently, the connecting pad sections of the wiring board on which the semiconductor chip is loaded is inserted into the through-holes, thus performing stable positioning.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に関し、特に半導体装置の外部接
続用のバット構造に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a bat structure for external connection of a semiconductor device.

〔従来の技術〕[Conventional technology]

従来、この種の半導体装置は、配線基板上に搭載される
場合には、半導体装置のバンプ構造の電極パッドと、配
線板のパッド部とを互いに突き合わせて、はんだ付けに
より接続を行っていた。
Conventionally, when this type of semiconductor device is mounted on a wiring board, the bump-structured electrode pads of the semiconductor device and the pad portions of the wiring board are butted against each other and connected by soldering.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、上述した従来の半導体装置では、半導体
チップ上に形成された外部接続パッド部と半導体チップ
を配線基板上のパッド部に搭載し、接続する場合に、互
いに凸状の形状をしているため、搭載したときに不安定
になり、これらパッド間の安定した位置合せ精度の確保
が難しくなる欠点がある。
However, in the conventional semiconductor device described above, when the external connection pad section formed on the semiconductor chip and the semiconductor chip are mounted on the pad section on the wiring board and connected, the external connection pad section formed on the semiconductor chip and the semiconductor chip are mutually convex shapes. , it becomes unstable when mounted, and has the drawback that it is difficult to ensure stable alignment accuracy between these pads.

本発明の目的は、かかる問題を解消する半導体装置を提
供することにある。
An object of the present invention is to provide a semiconductor device that solves this problem.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、配線基板のスルーホールにその
先端の一部が挿入される凸状の電極パッドと、この電極
パッドの導電層と接続するとともに素子形成層内に形成
された配線とを有している。
The semiconductor device of the present invention includes a convex electrode pad whose tip is partially inserted into a through hole of a wiring board, and a wiring connected to a conductive layer of the electrode pad and formed in an element formation layer. have.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。第1図
は、本発明の一実施例を示す半導体装置と配線板の斜視
図、第2図は第1図のA部拡大断面図である。この半導
体装置は、第2図に示すように、半導体チップ9上に形
成された素子形成層中8の配線7に接続される導電層2
を有する凸状の電極パット1が設けられたことである。
Next, the present invention will be explained with reference to the drawings. 1 is a perspective view of a semiconductor device and a wiring board showing an embodiment of the present invention, and FIG. 2 is an enlarged sectional view of section A in FIG. 1. As shown in FIG.
This is because a convex electrode pad 1 having a convex shape is provided.

方、配線基板4のスルーホール5には、その内壁及び表
面には、導電層6が形成されている。
On the other hand, a conductive layer 6 is formed on the inner wall and surface of the through hole 5 of the wiring board 4.

このような構造にすることにより、例えば、第1図に示
すように、配線基板4に半導体チップ9を搭載する場合
でも第2図に示すように、半導体チップ9の凸状電極パ
ッド1が、配線基板4のスルーホール5のエッチ部には
め込まれて、導電層6と導電層2とで接続される。この
ため、半導体チップ9は、搭載したときに、自動的にこ
の電極パッド1とスルーホール5とで位置決めされる。
By adopting such a structure, for example, even when the semiconductor chip 9 is mounted on the wiring board 4 as shown in FIG. 1, the convex electrode pads 1 of the semiconductor chip 9 can be It is fitted into the etched portion of the through hole 5 of the wiring board 4 and connected to the conductive layer 6 and the conductive layer 2. Therefore, when the semiconductor chip 9 is mounted, it is automatically positioned between the electrode pads 1 and the through holes 5.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、半導体装置の電極パッ
ドを凸部状にすることにより、半導体チップを搭さいす
る配線板の接続パッド部のスルーホールにはめ込まれる
ので、安定した位置合せが期待出来る半導体装置か得ら
れるという効果かある。
As explained above, in the present invention, by making the electrode pad of a semiconductor device into a convex shape, it can be fitted into the through hole of the connection pad part of the wiring board on which the semiconductor chip is mounted, so that stable alignment is expected. This has the effect of making it possible to obtain a semiconductor device that can be manufactured.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例を示す半導体装置と配線基
板の斜視図、第2図は第1図のA部拡大断面図である。 1・・・凸状電極バッド、2,6・・・導電層、3,7
・・・配線、4・・・配線基板、5・・・スルーホール
、8・・・素子形成層、9・・・半導体チップ。
1 is a perspective view of a semiconductor device and a wiring board showing an embodiment of the present invention, and FIG. 2 is an enlarged sectional view of section A in FIG. 1. 1... Convex electrode pad, 2, 6... Conductive layer, 3, 7
... Wiring, 4... Wiring board, 5... Through hole, 8... Element formation layer, 9... Semiconductor chip.

Claims (1)

【特許請求の範囲】[Claims] 配線基板のスルーホールにその先端の一部が挿入される
凸状の電極パッドと、この電極パッドの導電層と接続す
るとともに素子形成層内に形成された配線とを有する半
導体装置。
A semiconductor device having a convex electrode pad whose tip is partially inserted into a through hole of a wiring board, and a wiring connected to a conductive layer of the electrode pad and formed in an element formation layer.
JP1178566A 1989-07-10 1989-07-10 Semiconductor device Pending JPH0342848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1178566A JPH0342848A (en) 1989-07-10 1989-07-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1178566A JPH0342848A (en) 1989-07-10 1989-07-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0342848A true JPH0342848A (en) 1991-02-25

Family

ID=16050721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1178566A Pending JPH0342848A (en) 1989-07-10 1989-07-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0342848A (en)

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