JPH0342870A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to a mask ROM using an ion implantation code mask method.
The present invention relates to the structure of a semiconductor device incorporating a semiconductor device.

[Summary of the invention]

The present invention makes it easier to carry out the code mask process after forming the gate electrode by making the gate electrode in the memory section of the mask ROM thinner than the peripheral circuit section.

[Conventional technology]

In mask ROM using ion implantation mask method, data IT
A code is written by implanting impurity ions into the memory transistor portion corresponding to I IF (or 10'') to make it a depletion type.

Conventionally, this code mask process is performed before forming the gate electrode.

[Problem to be solved by the invention]

However, T A T (Turn Around Ti
In order to shorten m5), it is necessary to shorten the steps after the code mask step. For this purpose, it is desirable to perform ion implantation after forming the gate electrode, but with the normal thickness of the gate electrode, it is difficult to implant ions through the gate electrode.

[Means to solve the problem]

Therefore, in the present invention, the above-mentioned problem is solved by making the gate electrode of the memory section thinner than the gate electrode of the peripheral circuit section.

(Function) By making the gate electrode of the memory section thinner than the normal gate electrode of the peripheral circuit section, ions can be easily implanted through the gate electrode.

Also, if the gate electrode in the peripheral circuit section is made thinner, gate 1
However, in the present invention, there is no problem because the gate electrode in the peripheral circuit portion is kept at a normal thickness.

〔Example〕

In the present invention, the thickness of the gate electrode of the memory section is determined so that ions are not implanted into the channel during the ion implantation of the source and drain. For example, NMO8 type mask ROM
When the source and drain are implanted with arsenic at 50 to 70 keν, Rρ and ΔRp of arsenic in Si are about 400 and 140, respectively, so a polysilicon gate electrode thickness of 1000 is sufficient. Next, when implanting ions through a polysilicon gate electrode, with a normal polysilicon gate electrode thickness, for example, when implanting arsenic, 500 keV or more is required, but by making the polysilicon gate electrode 1000 times thinner, 200k
Can be injected at eV. 100k if you double charge
Injection is also possible at eV.

The semiconductor device of the present invention can be realized through the following manufacturing process. First, in FIG. 1 fat, a gate insulating film 2 and a thick gate electrode 3 are sequentially formed on a semiconductor substrate l, and then a resist pattern 4 is formed in a portion that will become a peripheral circuit in a photo process. Using the resist pattern 4 as a mask, the gate electrode 3 and gate insulating film 2 of the memory section lO shown in FIG. 1 fat are sequentially etched.
In l, gate zetsu again! ! After forming the film 5, a resist pattern 6 is formed in the memory section 10 by a photo process. Next, in FIG. 1fd+, after etching the gate insulation #5 on the thick gate electrode 3 using the resist pattern 6 as a mask, a thin gate electrode 7 is deposited on the entire surface. Thereafter, a code mask process is performed to write a code, and then the gate electrodes of the memory section 1O and the peripheral circuit section 11 are patterned simultaneously using a normal photoetching process.

Furthermore, if the etching uniformity and reproducibility of the gate electrode are sufficiently improved, this can also be achieved by stopping the etching of the gate electrode 3 midway through the process shown in FIG. 1 (dl) and making the gate electrode thinner.

Furthermore, in the structure of the semiconductor device of the present invention, the thin gate electrode portion can be used as a high resistance element, a fuse, etc., so that it is easy to mount the semiconductor device together with such elements.

〔Effect of the invention〕

As described above, by using the structure of the present invention for a semiconductor device incorporating a mask ROM, the TAT can be shortened.

[Brief explanation of drawings]

1M) to (dl are examples of sequential cross-sectional views of manufacturing steps for realizing the semiconductor device of the present invention. ■...Semiconductor substrate 2.5...Gate insulating film 3...Thick gate Electrode 4.6...Resist pattern 7...Thin gate electrode or more

Claims (1)

[Claims] A semiconductor device incorporating a mask ROM using an ion implantation code mask method, characterized in that a gate electrode in a memory section is thinner than a gate electrode in a peripheral circuit section.