JPH0342876A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of an electrically rewritable semiconductor nonvolatile memory.

[Conventional technology]

In a conventional semiconductor nonvolatile memory in which a tunnel region and a control gate are formed by an impurity diffusion layer on a semiconductor substrate, an insulating film on the control gate is formed of a silicon oxide film.

[Problem to be solved by the invention]

However, since the insulating film on the control gate was formed of a silicon oxide film in this way, the capacitance value of the capacitor composed of the control gate and floating gate was proportional to the dielectric constant of the insulating film, so a large value was obtained. I can't.

The capacitor constituted by the control gate and the floating gate affects the data writing and erasing efficiency of the semiconductor nonvolatile memory, and has a problem in that the writing and erasing efficiency is low due to its small capacitance value.

This will be explained below. As shown in FIG. 3(a), the equivalent circuit of the electrically rewritable nonvolatile memory in the film is expressed in terms of capacitance as shown in FIG. 3(b).

Here, the voltage VP of the floating gate is expressed as follows.

Here, considering the case where charge is injected into the floating gate, this can be achieved by grounding the drain and the substrate and applying a high voltage to the control gate. Of course, the larger the voltage between the floating gate and the tunnel region provided in a part of the drain, the higher the Fowler-No.
The rdhjm tunneling current becomes larger, making it easier to inject charges into the floating gate. Therefore, when injecting charges, it is desirable that the value of CC be large.

SUMMARY OF THE INVENTION The present invention solves the problem of low data writing and erasing efficiency, and aims to improve the capacitance value without increasing the area of the capacitor constituted by the control gate and floating gate. The purpose of the present invention is to provide a semiconductor nonvolatile memory with increased data writing and erasing efficiency.

[Means for resolving issues]

The semiconductor device of the present invention is a semiconductor nonvolatile memory including a control gate formed by an impurity diffusion layer provided in a part under a floating gate formed on a semiconductor substrate with a gate insulating film interposed therebetween. The insulating film between the floating gate and the floating gate is formed of a dielectric material having a relative permittivity of 4° or more.

[For production]

According to the above configuration of the present invention, the capacitance value of the capacitor constituted by the control gate and the floating gate increases, the electric field between the floating gate and the tunnel region increases, and the data writing and erasing efficiency as a memory function increases. improves.

〔Example〕

FIG. 1 is a plan view and a sectional view of an embodiment of the present invention,
The manufacturing method will be explained below in order according to the main steps.

First, a silicon nitride film is deposited on a P-type silicon substrate 106.
After depositing about 600A, a silicon nitride film was left only in the element forming area by photolithography, and a resist was further applied.
After opening the resist at the P-type stopper formation part by photolithography, the energy was 40 KeV and the dose was 4.
B (boron) ions are implanted under the condition of x10"cm-', then the resist is removed, and annealing is performed for about 60 minutes in a nitrogen atmosphere at 1000° C. to form a P channel stopper region 112.

Then, using the silicon nitride film as a mask, wet oxidation at 950°C is performed to selectively apply LOCO3 to the field region.
An oxide film 109 is grown to a thickness of about 1 μm. Next, after removing the silicon nitride film, TaCN5 was used as a source material.
The tantalum oxide film was deposited at approximately 600A using the photo-CVD method using
deposit

Next, after removing the resist in areas other than the area above the control gate by photolithography, dry etching is performed to remove the resist.
Etch the tantalum oxide film.

Thereafter, thermal oxidation is performed in an oxygen atmosphere at 1100° C. to form a silicon oxide film 113 of about 600 layers. and,
A region causing the Fowler-Nordheim tunnel phenomenon (hereinafter referred to as a tunnel region) is opened by photolithography, and the silicon oxide film is removed using hydrofluoric acid or the like. Next, the resist is removed and thermal oxidation is performed for about 10 minutes in an oxygen atmosphere at 900° C. to form a silicon oxide film 107 of about 100 layers in the tunnel region 104.

Then, a polycrystalline silicon layer with a thickness of about 4000 nm is formed on the entire surface, and an N-type impurity P (phosphorus) or As (arsenic) is diffused, and then a gate electrode 102b is formed by photolithography.
Then, a floating gate 102a is formed. Furthermore, using the resist and gate electrode as a mask, an energy of 80 KeV and a dose of 5X were applied to the N channel formation region.
P (phosphorous) ions were implanted under the condition of 10” am-2, and N
The type low concentration diffusion layer 105 is formed as an offset region.

Next, a resist was applied to cover the gate electrode by photolithography, and then this resist was applied as a mask at an energy of 80 KeV and a dose of ffi4XIDI5cm-2.
Perform ion implantation under the conditions of source/de.

An N-type high concentration diffusion layer 108 in the rain region is formed.

Next, a PSG film is deposited as an interlayer insulating film 114 over the entire surface.

In the subsequent steps, contact holes for leading out the source/drain are formed by photolithography according to a conventional method, and then aluminum for electrode wiring is sputtered. Then, the aluminum wiring is patterned by photolithography.

Finally, a passivation film 111 of silicon oxide is deposited to obtain the memory cell structure shown in FIG. 1(b).

In this way, the equivalent circuit of the configured memory cell is
Shown in Figure (c).

Now, we will explain how the capacitor formed by the control gate and floating gate affects the characteristics of the memory.

First, when storing data in a memory cell, a voltage higher than the threshold voltage is applied to the gate 202 of a selection transistor, and a voltage of about 20 V is applied between the drain 201 of the selection transistor and the control gate 203.

Now, let us consider the case where electrons are injected into the floating gate to increase the threshold voltage of the memory transistor. A voltage V2 is applied to the drain 201 of the selection transistor.
, when voltage v1 is applied to the control gate 203,
The voltage V4 of the floating gate is determined by a capacitor C3 formed by the floating gate and the control gate, a capacitor C2 formed by the floating gate and the impurity diffusion layer of the tunnel region, and other capacitors C3 parasitic to the floating gate. This equivalent circuit is shown in FIG. 1(d).

From this equivalent circuit, the value of the floating gate voltage v4 is expressed by the following equation.

Here, if V2 and V are set to zero, then the following is obtained. From this equation, the value of the floating gate voltage v4 increases as the capacitance value of CI increases.

Therefore, the larger the capacitance value of the capacitor C7 constituted by the control gate and the floating gate, the larger the voltage value of v4 becomes, and the data writing and erasing efficiency becomes better.

Since the insulating film on the control gate of the present invention has a higher dielectric constant than a silicon oxide film, the capacitance value of the capacitor C0 can be increased with the same area and film thickness.

Therefore, if the data write and erase voltages are the same,
The higher voltage applied to the floating gate and tunnel region provides better write and erase efficiency. Also,
In order to maintain the same efficiency as the conventional one, it is possible to reduce the area of the capacitor C1, that is, the areas of the control gate and floating gate.

〔Effect of the invention〕

As described above, according to the present invention, the area of the memory cell can be reduced without lowering the conventional data writing and erasing efficiency, so that high integration is possible. Also,
If the memory cell has the same area, the voltage applied during writing and erasing can be lowered, and the voltage applied to the gate film of the transistor can be lower, making the gate film less likely to be destroyed and improving reliability. becomes possible.

In the present invention, a tantalum oxide film has been described as a dielectric having a relative dielectric constant of 4.0 or more, but silicon nitride films, Pb
T i O3, P Z T (P b T i Os
/PbZr0. ), BaTiO3, etc. may also be used.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are a plan view and a sectional view showing an embodiment of a semiconductor nonvolatile memory according to the present invention. FIG. 1(c) is an equivalent circuit diagram of FIGS. 1(a) and 1(b) which are examples of the semiconductor nonvolatile memory of the present invention. FIG. 1(d) is an equivalent circuit diagram using a capacitor when writing data to the semiconductor nonvolatile memory of the present invention. 101a, 101b, 108... Diffusion layer in source/drain region... Gate 102a of selection transistor... ◆ Floating gate of memory transistor... Control gate of memory transistor... Diffusion layer in tunnel region ◆ - Transistor Offset region of...Silicon substrate...Tunnel oxide film...LOGO9 oxide film 102, 103, 104, 105# 106, 107, 109, 110, 111, 112, 113, 13a 114, 201, 202, 203, 204, Vl ・ v7 ・ V, ・ v4 ・ C1 ・ C2 ・ ... Aluminum wiring layer ... Passivation film ... Channel stopper ... Gate oxide film ... Tantalum oxide film ... Interlayer insulating film ... Drain of selection transistor・Gate of selection transistor ・Control gate of memory transistor ・Source of memory transistor ・Voltage of control gate ・Voltage of diffusion layer in tunnel region ・Voltage of silicon substrate ・Voltage of floating gate ・Floating gate A capacitor composed of a floating gate and a control gate ・Capacitor 3 composed of a floating gate and a diffusion layer in the tunnel region ・A capacitor parasitic to the floating gate or more

Claims (1)

[Claims] In a semiconductor non-volatile memory comprising a control gate formed by an impurity diffusion layer provided in a part under a floating gate formed on a semiconductor substrate via a gate insulating film, insulation between the control gate and the floating gate is provided. A semiconductor device characterized in that a film is formed of a dielectric material having a dielectric constant of 4.0 or more.