JPH0342910A - Buffer circuit - Google Patents

Abstract

PURPOSE: To remove a high frequency noise spike with high precision by providing a first circuit connected between an input terminal and an output terminal which is provided with at least one switching element, and a second circuit connected between the input terminal and the output terminal and also connected with the first circuit which effectively controls the operation of a switching element. CONSTITUTION: In this case of a pulse signal in which a Vin is changed from 0V to 3V, and returned to 0V, when the Vin is changed from 0V to 3.0V, terminals 18 and 22 are immediately turned into a low level. In this case, the terminals 18 is held at a low level even when a transistor P1 is turned on. When a terminal 24 is turned into a high level, a transistor N4 is turned on, and the terminal 24 is turned into a low level. Once the terminal 24 is turned into a low level, a transistor P3 is turned on, and the terminal 18 is turned into a high level. The level of the terminal 18 is inverted by an invertor constituted of transistors P2 and N2, a Vout is turned into a low level, a terminal 26 is turned into a high level, and a transistor P7 is turned off.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a buffer circuit, and particularly to a buffer circuit that converts a low level signal into a higher level signal.

[Prior Art] Many current semiconductor integrated circuits require converting low level logic input signals into higher level logic output signals. For example, it is often necessary to convert a TTL input signal varying between OV and 3.Ov for logic "0" and logic "1m" to a higher level CMO8 amplitude varying between Ov and 5V. In order to operate TTL circuits together with CMOS circuits, an interface, or buffer circuit, is provided between the two circuits that converts relatively low TTL logic levels to higher levels at which the CMOS circuits can operate reliably. There must be.

A relatively simple TTL-CMOS buffer circuit.

This is a CMOS inverter that receives TTL level input and outputs CMOS level output. This TTL-CMOS inverter includes an NMO3) transistor;
The MOS transistors are about five times as wide as in a typical conventional CMOS inverter, compared to half the width of a 1MO8) transistor. Therefore, given a 5V supply, for this CMOS inverter typically.

It switches its output between the entire 5V CMOS range when its input is at about 1.5V, rather than about 2.5V, which is the switching point of a typical CMOS inverter. Very complex buffer circuits that perform such operations are also known, e.g., U.S. Pat. No. 3,755.
．． No. 690 and No. 4.048,518.

The switching point of this inverter of 1.5v is suitable for operation with TTL input. Because, T.T.
In the L standard, 2. Logic “1” for voltage level above OV
, 0.8V or less is considered to be a logic “O゜.However, 0.8V in these TTL
and 2. The limit on Ov is for DC specifications. T
TL1 typically operates under AC conditions varying between 0 and 3V, with the switching point located in the middle (1,5V) of the TTL input signal range of a simple buffer.

If the buffer circuit has a switching point of 1.5 V and the input normally varies between Ov and 3V,
The buffer circuit has approximately 1 on each side of the switching point.
．． It can be said that it has a noise margin of 5 V. That is, when the input is Ov, 1.5 in the positive direction
Momentary noise pulses up to V can be ignored. Thereby, even if a noise pulse of this level appears at the input, no error will occur at the output of the buffer circuit. Similarly.

When the input is 3V, 1.5V goes in the negative direction
Noise pulses up to 100 kHz can be ignored in this buffer circuit.

[Issue 8 to be solved by the invention] However, in this conventional buffer circuit, the absolute value is 1.
．． Pulses above 5 V cannot be ignored. This level of noise then produces a false CMOS level output in response to one or both of the TTL input levels.

The problem of the invention is that high levels of noise can be ignored. An object of the present invention is to provide a TTL-CMOS buffer circuit with a high noise margin.

[Means for Solving the Problems] The buffer circuit of the present invention has a buffer circuit of about 2,
A positive-going noise pulse of 4V can be ignored, and a negative-going noise pulse of about 0.8■ applied to the input of a, OV can be ignored. The buffer circuit of the present invention has a logic "O" voltage of 0.8 V and a logic "1" voltage of 2.8 V. This satisfies the TTLi style specifications of OV. The buffer circuit of the present invention achieves these obvious objectives by reducing the input noise to a typical instantaneous pulse (several n
This is achieved by taking advantage of the fact that s to several Ions).

The buffer circuit of the present invention includes two independent buses between input and output. The first bus is a high-speed AC bus,
This is approximately 2.0V when the input signal increases from Ov to 3V.
Logic “0” state and logic “ with high switching voltage of 5V
1” Switch the state.

When the input signal decreases from 3V to Ov, a switching voltage as low as about 1.1 cm switches between a logic "1" state and a logic "0" state. The second bus is a low-speed DC bus that controls the operation of the first bus, and both increases and decreases the input signal by approximately 1. It has a low switching voltage of IV. By applying different DC and AC switching voltages and by creating a hysteresis effect in the AC path, the TTL-CMOS buffer circuit of the present invention can suppress high-frequency noise spikes with higher accuracy than conventional buffer circuits. Can be removed gradually.

[Function] The TTL-CMOS buffer circuit of the present invention has a first inverter path that operates at a relatively high speed, and a second inverter path that operates at a relatively low speed and is connected to the first path and controls the operation of the first inverter path. 2 inverter paths with short connection time.
．． Positive or negative noise paths with amplitudes up to 4v do not adversely affect the output level.

[Example] Next, an example of the present invention will be described with reference to the drawings.

As shown in the embodiment shown in FIG.
The S-buffer includes a first high speed (AC) path 10 and a second low speed (DC) path 12.

Pass 10. and 12 is an input TTL level signal V.

an input terminal 14 that receives a CMOS level output signal v
.

The first path 10 has an input inverter comprising PMO8) transistors P3 and Pl and NMO8) transistor N1 connected in series between the supply voltage (here +5V) and the reference voltage line (here ground). are doing. The larger the W/L ratio of a transistor, the more
A large drain current flows with the same gate voltage. For each of these MOS transistors, furthermore,
Preferred width to length ratio (W/L ratio) for all other MOS transistors included in the buffer circuit of FIG.
is marked in microns in FIG. However, it should be understood that these ratios are merely representative and are not meant to limit the scope or effect. for example.

These ratios will vary with different electrical process parameters.

The W/L ratio of the inverter consisting of transistors Nl, PI and P3 is selected such that when the gate voltage of transistor P3 is Ov, the switching voltage of vl is approximately 2.5V. The gates of transistors P1 and N1 are vl,
It is connected to the input terminal 14, and an inverter terminal 18 is established at the common connection point of the drains of both these transistors P1 and N1. Terminal 18 is connected to the gates of transistors P2 and N2, which are connected between a +5v voltage source and ground. Transistors P2 and N2 constitute a second inverter stage. The inverter terminal 20 at the common connection point of the drains of transistors P2 and N2 is connected to the output terminal 16.

Slow DC path 12 includes an input inverter consisting of transistors P4 and N3 connected between +5Vt and ground.

Transistor N3. The W/L ratio of P4 is the transistor PL
, Nl is smaller than the W/L ratio of the switching point, i.e., N3. P4 inverter is approximately 1. V of LV. The gates of transistors P4 and N3 are connected to input terminal 14.

An inverter terminal 22 is formed at the common connection point of the drains of transistors P4 and N3.

Inverter terminal 22 is connected to the gates of transistors P5 and N4, which are connected between the +5v voltage and ground. The inverter terminal 24 is the common connection point of the drains of transistors N4 and P5.

It is connected to the gate of the transistor P3 and one end of the capacitor C1, and the other end of the capacitor C1 is grounded. Capacitor C1 has floating capacitance and transistor P
3, typically on the order of o,tpp.

Slow path 12 also includes a second inverter consisting of transistors P6 and N5 connected between the +5v voltage source and ground. The gates of transistors P6 and N5 are connected to output terminal 16.

An inverter terminal 26, which is a common drain connection point of transistors N5 and P6, is connected to the gate of transistor P7. The source of transistor P7 is connected to a +5V voltage source, and its drain is connected to a +5V voltage source.

It is connected to the gate of transistor P3 and capacitor C1, as well as to the output terminal 24 of an inverter stage consisting of transistors P5 and N4.

The operation of the buffer circuit of FIG. 1 will be described with further reference to the DC and AC transition curves of the high speed bus 10 and low speed bus 12 shown in FIGS. 2 and 3. Here, four cases are possible.

1) V+- is a pulse signal from Ov to 3V and then back to Ov.

2) ■ is a noise pulse going in the positive direction from Ov to 2.4V, then back to Ov.

3)■, is 3. Ov to 1.2 V, (-shite3.
This is a negative going noise pulse returning to Ov.

4) vo is a direct current that switches between 0.8v and 2.07v.

In case 1), V, , is from Ov to 3. A weird badass to the OV.

Terminals 18 and 22 immediately go low. This is because the input of a, OV is at a voltage higher than the switching point of the single-car inverter, and this voltage is Nl.

High enough to switch the inverter consisting of PI, P3 and the inverter consisting of N3 and P4.

When terminal 18 goes low, terminals 20 and v,,1 go high, which causes transistors P6. N5
The terminal 26 is set to low level. When the terminal 22 becomes low level, the transistor N
4 is turned off, and when terminal 26 goes low, transistor P7 is turned on. In this way, transistor P
When 7 is turned on, terminal 24 immediately goes to +5V.

Transistor P3 is turned off. (2) When the voltage returns to Ov, the transistor P4 is turned on and the terminal 22 becomes high level. However, at this time, the transistor P3 is still off, and the terminal 18 remains at a low level even though the transistor P1 is on. When the terminal 24 becomes high level, the transistor N4 turns on and the terminal 24 becomes high level.
becomes low level. This is because transistor N4 has a larger W/L ratio than that of transistor P7, so it overcomes transistor P7, which is already on at that time. -dan,
When terminal 24 becomes low level.

Transistor P3 is turned on, and since transistor P1 is always on, terminal 18 goes high. terminal 1
The level of 8 is inverted in an inverter consisting of transistor P2°N2.

■・. 1 is set to low level, terminal 26 is set to high level, and transistor P7 is turned off.

In the case of 2), 2.4Vl from V + and KaOV:
When changed, the input voltage is not high enough to immediately switch terminal 18 low. However, transistor P4
．． Terminal 22 of the inverter consisting of N3 immediately goes low. This is because the switching point is approximately 1. I
This is because it is just V. When terminal 22 goes low, transistor N4 turns off and transistor P
5 turns on. Transistor P5 is made relatively long and narrow so that it is a weak current source even when on, and charges terminal 24 positively and slowly.

If, like a typical noise pulse, is at 2.4V for a few nanoseconds before returning to Ov, terminal 24 will be less positive before being returned to ground by turning on transistor N4. The potential does not rise in the direction of . if,
If terminal 18 does not go low, then V at the output of the inverter consisting of transistor N2°P2. ,
is not at a high level. If v+fi was 2.4v for a long time, unlike the noise pulse case.

The gate of transistor P3 eventually turns off.

The 2.4v input level causes node 18 to go low;
■It is sufficient to make 1 a high level.

In the case of 3), ■ is 3. Being Ov.

The gate of transistor P3 is 5. Ov, meaning that transistor P3 is off. if.

Once vII, drops to 1.2 V, transistor P1 turns on. But transistor P3 is off,
Since it is connected in series with transistor P1, terminal 1
8 does not go high, and V o ++ 1 remains high. If +”1m only drops to 1.2 V, it is not low enough to make terminal 22 high. It is necessary to bring terminal 24 to a low level and turn on transistor P3. In the case of such a negative-going pulse, unless one input pulse becomes 1.1 V or less, even a noise signal with a long I! duration will not cause ■, 1 to go to a low level.

In the case of direct current (4), an inverter consisting of transistors N3°P4 controls the state. ■.

When is less than 0.8v, terminal 22 is at high level.

Terminal 24 is at low level and transistor P3 is on.

Transistor Pi is on and terminal 18 is at high level.

However, Vo, , is at a low level. ■, level is 2
．． When greater than OV, transistor N1 is on, transistor P1 is partially on, terminal 22 is low level,
(After sufficient time has elapsed) terminal 24 is at a high level, transistor P3 is off, terminal 18 is at a low level, and terminals 2o and V a m l are at a high level.

In addition to reducing the effect of noise on IVIII, the buffer circuit of the present invention also suppresses ground noise. The return to ground shown in FIG. 1 would be ideal. Typically, in inductance-based high-speed chips, the return to ground is a feeder, just at O
Not v. For example, the ground noise pulse in the positive direction in the buffer circuit of FIG. is equivalent to a noise pulse in the negative direction. If IVlm
If is a logic "1" state of 3, Ov, the circuit can withstand 1.8 V of positive going ground noise before switching incorrectly. Similarly, if V, , is in the logic "0" state of OV, a negative going noise pulse of up to 2.4 V will not result in an erroneous logic operation.

[Effects of the Invention] In this way, the TTL-CMO 5-person cover buffer of the present invention effectively prevents erroneous logic switching operations caused by noise signals up to 4V.

Also without departing from the spirit and scope of the invention.

It should be understood that modifications may be made to the embodiments described in Section 22.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a TTL-CMOS buffer circuit according to an embodiment of the present invention, FIG. 2 is an AC transition curve of the buffer circuit of the present invention, and FIG. 3 is a DC transition curve of the buffer circuit of the present invention. 10...first bus, 12...second bus, 14.
...Input terminal, 16...Output terminal, 18, 20, 22
゜24.26...Inverter terminal. riC transition curve

Claims (1)

[Claims] 1. An input terminal; an output terminal; a first circuit connected between the input terminal and the output terminal and having at least one switching element; connected between the input terminal and the output terminal; and a second circuit connected to the first circuit to effectively control the operation of the switching element. 2. Further comprising a charging means connected to the switching element and the second circuit, the second circuit applying a charging current to the charging means and controlling the charging means to either high voltage or low voltage. 2. The buffer circuit according to claim 1, further comprising charging current supply means for charging to said voltage. 3. The first circuit includes the switching element,
and a first inverter having an input end connected to the input terminal; and a second inverter having an input end connected to the output end of the first inverter and an output end connected to the output terminal; 3. The buffer circuit according to claim 2, further comprising a buffer circuit. 4. The output buses of the first inverters are connected in series, and each gate is connected to the input terminal.
4. The switching element includes first and second transistors, and the switching element has an output circuit connected between the output circuits of the first and second transistors and a voltage source. buffer circuit. 5. The current supply means includes a third transistor which is activated when charging the charging means to one of the voltages at a first low rate; 5. A buffer circuit according to claim 4, further comprising: a fourth transistor which is activated when charging the means. 6. The buffer circuit according to claim 5, wherein the fourth transistor has a W/L ratio higher than that of the third transistor. 7. The output circuits of the third and fourth transistors are connected between a voltage source and a reference voltage line, the connection point of the output circuits constitutes an output point, and the output point is connected to the charging means. 7. The buffer circuit according to claim 6, wherein the buffer circuit is connected to the buffer circuit. 8. The second circuit has a third circuit connected to the input terminal.
8. The buffer circuit according to claim 7, further comprising: an inverter; and a fourth inverter connected to the output of the third inverter and including the third and fourth transistors. 9. a fifth inverter provided in the second circuit and having an input terminal connected to the output terminal; a gate connected to the fifth inverter;
9. The buffer circuit according to claim 8, further comprising: a fifth transistor connected to the output of the fourth inverter, the output of which is connected to the charging means and the output point of the fourth inverter. 10. a first transistor that is activated when said current supply means charges said charging means to a first voltage at a relatively slow first rate; 3. The buffer circuit according to claim 2, further comprising: a second transistor that becomes effective when charging said charging means. 11. The buffer circuit according to claim 10, wherein the second transistor has a higher W/L ratio than the first transistor. 12. The output paths of the first and second transistors are connected in series between a voltage source and a reference voltage line, their common output connection point constitutes an output point, and the output point of the inverter is connected to the 12. The buffer circuit according to claim 11, wherein the buffer circuit is connected to charging means. 13. The first circuit includes a first inverter whose input is connected to the input terminal and includes the switching element, and the second circuit is connected to the switching element and controls the operation of the switching element. 2. The buffer circuit of claim 1, further comprising control means for controlling operation of said first inverter in response to short duration noise at said input terminal. 14. The control means includes means connected between the switching element and the second circuit, and the second circuit further causes the control means to apply a control voltage to one of two voltage levels. 14. The buffer circuit according to claim 13, further comprising voltage establishing means for establishing the voltage. 15. The control means includes charging means, and the voltage establishing means supplies current to the charging means to charge the charging means to one of the voltage levels at a first fast rate, and 15. A buffer circuit as claimed in claim 14, including current supply means for charging said charging means to a second voltage level at a second slow rate. 18. A first transistor which is activated when the current supply means charges the charging means to the one of the voltages at the first rate;
16. The buffer circuit according to claim 15, further comprising a second transistor that becomes effective when charging to a voltage of . 17. The buffer circuit according to claim 16, wherein the second transistor has a higher W/L ratio than the first transistor. 18. Output paths of the first and second transistors are connected between a voltage source and a reference voltage line, a connection point of the output paths constitutes an output point of an inverter, and the inverter output point is connected to the charging means. 18. The buffer circuit according to claim 17, wherein the buffer circuit is connected to. 19. The first inverter includes first and second transistors whose output paths are connected in series and whose respective gates are connected to the input terminal, and the switching element is connected to a voltage source and the first transistor. 15. The buffer circuit according to claim 14, further comprising an output path connected between the buffer circuit and the output path of the second transistor. 20, the second circuit includes a third inverter having an input connected to the input terminal, the first inverter includes first and second transistors, and the third inverter includes third and second transistors; 4 transistors, the first and second transistors having a higher W/L ratio than the third and fourth transistors, such that the first inverter has a higher W/L ratio than the third inverter. 4. The buffer circuit according to claim 3, wherein the buffer circuit also has a high switching point. 21, an input is connected to the output of the third inverter,
21. The buffer circuit according to claim 20, further comprising a fourth inverter having an output connected to the switching element. 22, a fifth inverter having an input connected to the second inverter; an output path being connected between a voltage source and an output of the fifth inverter; and a control gate connected to the output of the fifth inverter; 22. The buffer circuit of claim 21, further comprising: a fifth transistor connected to the buffer circuit. 23. The first circuit includes a first inverter having an input connected to the input terminal and having a first switching voltage; and the second circuit has an input connected to the input terminal and includes a first inverter having a first switching voltage. , a second inverter having a second switching voltage lower than the first switching voltage. 24, each of the first and second inverters includes a pair of complementary transistors, and the transistor included in the first inverter has a larger W/
24. The buffer circuit according to claim 23, having an L ratio. 25. The buffer circuit according to claim 23, wherein the switching element is included in the first inverter. 26. further comprising a charging means connected to the switching element and the second circuit, the second circuit supplying a charging current to the charging means and charging the charging to either a high or low voltage; 26. The buffer circuit according to claim 25, further comprising current supply means for charging the buffer circuit. 27. The first inverter includes first and second transistors whose output paths are connected in series and whose respective gates are connected to the input terminal, and wherein the switching element is connected to the voltage source and the first transistor. 26. The buffer circuit according to claim 25, further comprising an output circuit connected between the first transistor and the output circuit of the second transistor. 28. a third transistor operative when said current supply means charges said charging means to one of said voltages at a first slow rate; said charging means to a second voltage at a faster second rate; 28. The buffer circuit of claim 27, further comprising: a fourth transistor that becomes effective when charging the buffer circuit. 29. The buffer circuit of claim 28, wherein the fourth transistor has a higher W/L ratio than the third transistor. 30. Output circuits of the third and fourth transistors are connected between a voltage source and a reference voltage line, a connection point of the output circuit constitutes an output point, and the output point is connected to the charging means. 30. The buffer circuit according to claim 29, characterized in that: 31, the second circuit includes a third inverter connected to the input terminal; and a fourth inverter connected to the output of the third inverter and including the third and fourth transistors. 31. The buffer circuit according to claim 30, comprising: and; 32, a fifth inverter having an input connected to an output terminal in the second circuit, a gate connected to an output of the fifth inverter, and an output connected to the charging means and the fifth inverter; 32. The buffer circuit according to claim 31, further comprising a fifth transistor connected to the output point.