JPH034342A - Memory controller - Google Patents

Abstract

PURPOSE:To execute an automatic return to an I/O access control when the memory access control is completed by executing the memory access control even in the course of an I/O access control mode. CONSTITUTION:When a down counter 150 counts '1', the second access pulse is inputted. Then, the output of an AND circuit 195 is changed from 'H' to 'L'. As a result, when a next reference signal is inputted, the output of a flip- flop circuit 120 goes to 'L' level, and a clock input to the down counter 150 is inhibited. Instead, the output of a flip-flop circuit 220 goes to 'H' level, the chip selection of a RAM 500 is maintained, and simultaneously, a changeover is executed so as to select a latch circuit 410 by a selector 420. At such a time, at a flip-flop circuit 210, a clearance is executed by the output of an AND circuit 230.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a memory control device that is effective when equipped with two types of circuits as memory access control circuits.

(Prior Art) As a control circuit for a random access memory (hereinafter referred to as RAM), there are an I/O access control method and a memory access control method. The I/O access control method is CPU
After the initial value is loaded into the counter from the central processing unit (central processing unit), the address is automatically updated at the timing of the access reference signal. On the other hand, the memory access control method is a method in which an address from the CPU is directly given to the RAM through a latch circuit.

Conventionally, there is a system in which the above two types of systems are installed in the same RAM.

FIG. 3 shows a conventional memory control device, and FIG. 4 shows an example of an operation timing chart of this device.

500 is a RAM, and the data bus, read, and write pulse terminals are omitted from the illustration.

The address to RAM 500 is given via selector 420. The selector 420 selects the address generated from the counter 400 and supplies it to the RAM 500 when in the I/O access control mode, and selects the address latched by the latch circuit 4/O when in the memory access control mode. RAM, 1 for every 500 is provided.

The initial value to the counter 400 is set on the data bus (Fig. 4(b)
)) is given from the CPU.

Also, the address to latch circuit 4/O is
1 via the address bus (see FIG. 4(a)).

On the other hand, /O0 is an I/O access control circuit, and the counter 140 is supplied with data representing the number of address update times (see FIG. 4(b)) from the CPU via the data bus. This example shows a case where "2" is given. The configuration and operation of the I/O access control circuit /O0 will be explained first.

When the latch circuit 140 receives a latch pulse (see FIG. 4(C)) from the CPU via the input section 13, it latches the data (see FIG. 4(d)) and sends its output to the down counter 150. give.

When the down counter 150 is given the first access pulse (see FIG. 4(h)) from the CPU through the input unit 11, it loads the output of the latch circuit 140 and downcounts at the clock timing (see FIG. 4(h)). (see e)). The output of the down counter 150 is supplied to a negative logic AND circuit 160. The output of the negative logic AND circuit 160 (see FIG. 4(f)) becomes high ("H") level when the output of the down counter 150 is all zero. Therefore, the low ("L") level output period of the negative logic AND circuit 160 indicates the period during which the address is updated. The output of the negative logic AND circuit 160 is the output of the down counter 150.
It is supplied to the clear terminal of , and also to the AND circuit 130 .

The AND circuit 130, together with the flip-flop circuit 1/O and 1201 inverter 170, and the NAND circuit 180,
This is a circuit that creates a clock for the down counter 150.

The first access pulse (see FIG. 4(h)) is also supplied to the clock input terminal of the flip-flop circuit 1/O. Then, the flip-flop circuit 1/O latches the "H" level data (see FIG. 4(i)), outputs the output to the BUSY terminal 2°, and supplies it to the data input terminal of the flip-flop circuit 120. do. A reference signal (see FIG. 4(g) a) is supplied to the clock input terminal of the flip-flop circuit 120 through the input section 14. The reference signal is a signal that serves as a reference for accessing the RAM 500. The reference signal is supplied to one side of the NAND circuit 180 via the inverter 170, and the output of the flip-flop circuit 120 is supplied to the other side of the NAND circuit 180.

Therefore, the output of the NAND circuit 180 (see FIG. 4(r))
outputs a pulse in response to the reference signal while the output of the flip-flop circuit 120 is at the "H" level, but is always at the "H" level while the output of the flip-flop circuit 120 is at the "L#" level.

Therefore, the output of the NAND circuit 180 is applied as a clock to the previous down counter 150 to advance the number of address updates, and the output of the NAND circuit 180 is applied as a clock to the counter 400 to update the address (the fourth
(See figure (s)). This realizes an I/O access system and enables address access to the RAM 500.

Further, the output of the flip-flop circuit 120 is the OR circuit 3
It is also supplied to the chip select terminal of the RAM 500 via 00.

Next, the memory access control circuit 200 will be explained.

The memory access control circuit 200 includes flip-flop circuits 2/O and 220 and an AND circuit 230. When the second access pulse (see FIG. 4 (m)) is supplied from the CPU via the input unit 12, the latch circuit 4/O receives the address from the CPU (see FIG. 4 (a),
In this example, "20" is set.)
is loaded, the output of the flip-flop circuit 2/O (see FIG. 4(n)) becomes "H° level" and is supplied to the flip-flop circuit 220.
Reference numeral 20 synchronizes the switching timing of the selector 420 with the reference signal, and its output (see FIG. 4(o)) is supplied to the control terminal of the selector 420 and to one side of the AND circuit 230. . The output of the AND circuit 230 (see FIG. 4(p)) is the flip-flop circuit 2/O
is supplied to the clear input terminal of As a result, every time the second access pulse is input, the latch circuit 4/O receives CP.
The address from U is loaded and the latch circuit 4/O
The output address (see FIG. 4 (1)) of the selector 42
0 to the RAM 500. Note that the chip select signal for the RAM 500 is realized by supplying the output of the flip-flop circuit 220 via the OR circuit 300. FIGS. 4(U) and 4(V) show the chip select signal and designated address of the RAM 500.

When accessing the RAM 500 as described above, there are two methods that can be used to access the RAM 500, but if both methods operate simultaneously, confusion will occur. Therefore, conventionally, BUSY terminal 2
0 is at the "H° level," and in this case, the I/
Since this is the O access control mode, the program is controlled so that both the first and second access pulses are not input.

(Problems to be Solved by the Invention) As mentioned above, according to the conventional memory control device, 0, BU
The level of the SY terminal 20 is monitored, and in the I/O access control mode, control is performed so that no access pulse is output from the CPU. As a result, I/O access #A
In the aill mode, interrupt processing is not possible, and there is a problem in that flexibility in program configuration is poor.

Further, an extra program for monitoring the level of the BUSY terminal 20 is required.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a memory control device that is capable of controlling memory access even in I/O access control mode, providing interrupt access, improving flexibility, and reducing the number of monitoring programs by one. With the goal.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a random access memory, and an address generated by a counter and an address output from a latch circuit for an address input section of the random access memory. an I/O that generates a clock at the timing of a memory access reference signal and advances the address given to the counter a number of times equal to a preset value since the first access pulse is supplied; access control means; memory access control means for loading the address of the address bus into the latch circuit when a second access pulse is supplied; and while the I/O access control means is advancing the address; The second access reference signal (when inputted, forcibly stops generation of the clock of the I/O access control means in synchronization with the access reference signal, and controls access by the memory access control means). It provides a means to prioritize.

(Function) With the above means, memory access control can be performed even in the middle of I/O access control mode, and when this memory access control is finished, it is possible to automatically return to I/O access control. .

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the actual flow side of the memory control device of the present invention, and FIG. 2 is a timing chart shown to explain its operation.

The difference between the device of the present invention and the conventional device (the circuit shown in FIG. 3) is that the information of the memory access control circuit 200 (
The output of flip-flop circuit 2/O) is the output of inverter 1
90 to one side of the AND circuit 195;
5 is input to the flip-flop circuit 120. The rest of the configuration is the same as the circuit shown in FIG. 3, so the same reference numerals as in FIG. 3 are given and the explanation will be omitted.

The operation of the circuit shown in FIG. 1 will be explained with reference to FIG.

“2” is sent from the CPU to the latch circuit 140 via the data bus.
” is set, and “/O” is set in the counter 400 (Fig. 2(b) (c)
(See (d)) Then, assume that there is an interrupt while operating in the I/O access control mode, and "20" is set in the latch circuit 4/O (see Figure 2 Ca))
. When the first access pulse (FIG. 2(h)) is supplied to the down counter 150, this counter 150 advances the down count at the timing of the reference signal (FIG. 2(g)).

Here, it is assumed that the second access pulse (FIG. 2(m)) is input when the down counter 150 has counted "1". Then, as shown in Figure 2 (j),
The output of the AND circuit 195 changes from "H" to "L". As a result, at the time (T1) when the next reference signal is input, the output of the flip-flop circuit 120 becomes 'L' level, and the clock input to the down counter 150 is prohibited.Instead, the output of the flip-flop circuit 220 is becomes "H" level (FIG. 2 (0)), the chip select of the RAM 500 is maintained, and the selector 420 is switched to select the latch circuit 4/O. /O is cleared by the output of the AND circuit 230 (Fig. 2(p)).
Figure 2(n).

Therefore, at the time (T2) when the next reference signal is input,
The output of the flip-flop circuit 220 becomes "L level", and the selector 420 selects the counter 400 side.The output of the AND circuit 195 becomes high level at the time point (T1), as shown in FIG. 2(j). Therefore, at time T2, when the reference signal is input, the NAND circuit 180
A pulse is obtained (FIG. 2(r)), and its fall causes the count of the down counter 150, which had been stopped until now, to advance. Therefore, the output of the selector 420 is "/O" and "11" as shown in FIG. 2(V).
, "20", "12" and so on, with 1 in between.
20'' address will be given.

As described above, in the device of the present invention, the operation of the memory access control circuit 200 can be prioritized by simple means. That is, if the second access pulse is given as an interrupt, it is not necessary to wait until the access of the I/O access control circuit /O0 is completed, and an interrupt address can be given.

Once the interrupt access is completed, the I/O access control mode can be continued.

According to the memory control device that operates in this manner, when constructing an entire program for a microcomputer, there is no restriction as in the conventional method, and thus the program can be easily constructed. Furthermore, since interrupt access is possible, it is highly flexible and effective in improving data processing speed.

[Effects of the Invention] As explained above, the present invention enables memory access control even in the I/O access control mode, provides interrupt access, improves flexibility, and allows only one monitoring program to be used. It can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing chart shown to explain the operation of the device of the present invention, FIG. 3 is a circuit diagram showing a conventional memory control device, and FIG. FIG. 4 is a timing chart shown to explain the operation of the circuit shown in FIG. /O0...I/O access control circuit, 200...Memory access control circuit, 1/O. 120.2/O. 22
0...Flip-flop circuit, 130.195.23
0...AND circuit, 140.4/O...Latch circuit, 150...Down counter, 160...Negative logic AND circuit, 170.190...Inverter, 180...
...NAND circuit, 300...OR circuit, 420...
Selector, 500... Random access memory (RA
M).

Claims (1)

[Scope of Claims] A random access memory; a selector that selectively provides an address generated by a counter and an address output from a latch circuit to an address input section of the random access memory; and a first access memory. I/O access control means for generating a clock and advancing an address given to the counter at the timing of a memory access reference signal a number of times equal to a preset value since the pulse is supplied; and a second access pulse is supplied. memory access control means for loading the address of the address bus into the latch circuit when the I/O access control means advances the address; and the second access pulse is inputted while the I/O access control means is advancing the address. and means for forcibly stopping generation of the clock of the I/O access control means in synchronization with the access reference signal to prioritize access by the memory access control means. Control device.