JPH0343650B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] When a physical page address obtained by address translation processing of a logical page address is stored in a local memory having a data bit width smaller than the physical page address, an excess address bit register is separately set. established in
The bit portion of the physical page address that is within the data bit width of the local memory is stored in a specific area in the local memory, and the bit portion of the physical page address that exceeds the bit width is stored in an excess address bit register. As a result, a physical page address having a larger number of bits can be stored using the local memory without increasing the data bit width of the local memory.

[Industrial application field]

The present invention provides a converted address storage method in which a physical page address obtained by address conversion processing of a logical page address is stored in a specific area in a local memory. This paper relates to a method for storing converted addresses when the number exceeds .

[Conventional technology]

In information processing devices, address translation processing is performed to create a physical page address from a logical page address when actually accessing buffer storage or main memory, and this address translation is performed using dynamic address translation (DAT: Dynamic
This is done dynamically during program execution by the Address Translation mechanism, and
It is well known that, for example, a translation lookaside buffer (TLB) is used to perform DAT at high speed.

A logical page address and a corresponding physical page address are registered in the TLB as a pair. Therefore, if the target physical page address is registered in the TLB, the physical page address can be immediately obtained from the logical page address by simply referencing the TLB.

In this way, by using TLB etc., address translation is speeded up, but in order to further speed up this address translation, the physical page address as a result of address translation is Since addresses are usually not translated many times, a translated address storage method has been proposed in which once a physical page address is obtained, it is stored in a specific area in local memory for use.

FIG. 3 is a block diagram showing the structure of this conventional translated address storage system.

In FIG. 3, 210 is a local memory;
It is provided in the CUP, and stores therein data such as arithmetic circuits during information processing and physical page addresses obtained through address conversion processing by TLB and the like. The physical page address is local memory 2
It is stored in a specific area within 10.

220 is an address selection circuit that selects a normal address (a side) that accesses a normal data area stored in the local memory 210 and a physical page access address (b side) that accesses an area where a physical page address is stored. side).

230 is an address register input selection circuit that selects either the physical page address (b side) obtained by address conversion processing by a TLB or the like (not shown) or the physical page address (a side) read from the local memory 210. and sets it in the address register 240.

In the address register 240, the physical page address input from the address register input selection circuit 230 and the intra-page address among the logical addresses are set. The physical page address portion is extracted and input to write data selection circuit 250, and the physical page address and intra-page address together form a real address for accessing main memory (not shown).

The write data selection circuit 250 selects the physical page address (b side) read from the address register 240 and normal data (a
side) and stores it in the local memory 210.

260 is an OR circuit which inputs a clock to the local memory 210 for storing normal data in the local memory 210.

In this configuration, when storing normal data in the local memory 210, the selection circuits 220 and 250 select the normal data side a.

For normal data, write data selection circuit 25
0 to local memory 210.
On the other hand, since the normal address is added to the local memory 210 through the address selection circuit 220, the input normal data is transferred to the predetermined address in the local memory 210 in synchronization with the normal data set clock applied from the OR circuit 260. Store in address area.

When reading normal data, the address selection circuit 220 selects the normal address side a to access the local memory 210. Normal data read from the local memory 210 is transferred to an arithmetic circuit (not shown) through a terminal T.

Next, set the physical page address to local memory 2.
10, each selection circuit 220, 23
0 and 250 select physical page address side b.

The physical page address obtained by the address conversion process is sent to the address register input selection circuit 23.
After being set in address register 240 through 0, it is applied to local memory 210 through write data selection circuit 250.

On the other hand, the physical page access address is transferred to the local memory 210 through the address selection circuit 220.
is added to the physical page address set clock sent from the OR circuit 260.
The input physical page address is stored in the predetermined address area in the local memory 210.

When reading the physical page address from the local memory 210, the address selection circuit 220 selects b
The address register input circuit 230 selects the a side.

The physical page address read from the local memory 210 by the physical page address access address applied from the address selection circuit 220 is set in the address register 240 through the address register input circuit 230.

The physical page address and the in-page address in the logical address are set in the address register 240, and both are taken out to form a real address for accessing main memory (not shown).

As described above, once a physical page is obtained by address translation, it is transferred to the local memory 21.
When storing data in a specific area in 0 and accessing the same page, the physical page address of this local memory 210 is used unless a page cross occurs, and only the address within the page is created. Since the real address for accessing the TLB can be obtained, the address translation process can be made faster than when referring to the TLB.

Further, efficient firmware can be constructed by utilizing the fact that the physical page address after address conversion is stored in a specific area in the local memory 210. That is, if the physical page address of the specific area in the local memory 210 is used when the physical page address is needed during the processing of a certain macro instruction,
Since the address conversion process can be shared, the firmware can be simplified and the address conversion process can be speeded up.

[Problem that the invention seeks to solve]

As mentioned above, the conventional translated address storage method is
By storing the physical page address obtained by address conversion in a specific area in the local memory 210, the speed of the address conversion process is further increased.

Incidentally, this local memory 210 is normally used as a temporary storage area for the results of other processes, such as ALU operations. The bit width of data stored in this local memory 210 is the same at any address in the local memory 210. Therefore, this local memory 210
The bit width of the physical page address stored in the local memory 210 is limited by the bit width of the local memory 210. If the bit width of the physical page address exceeds the bit width of the local memory 210, the conventional In this method, it was necessary to increase the data bits by the insufficient bit width for all addresses in local memory.

Therefore, in the conventional system, when the bit width of the physical page address exceeds the bit width of the local memory 210, there is a problem in that the number of data bits in the local memory 210 must be significantly increased.

In the present invention, even if the bit width of the physical page address exceeds the bit width of the local memory,
To provide a converted address storage system capable of storing a physical page address with a larger bit width by using a conventional local memory without increasing the bit width of the local memory.

[Means for solving problems]

Means taken by the present invention to solve the above-mentioned problems in the conventional translated address storage method, and the first
This will be explained with reference to the figures.

FIG. 1 is a block diagram showing the structure of the present invention.

In FIG. 1, 110 is a local memory;
A physical page address obtained by address translation processing is stored in a certain specific area along with data during normal information processing.

Reference numeral 120 denotes an excess address bit register in which the bit portion of the physical page address exceeding the data bit width of the local memory 110 is stored.

Reference numeral 130 denotes a physical page address processing means for processing local memory 1 in the input physical page address.
The bit portion within the data bit width of 10 is stored in a specific area in the local memory 110, and the bit portion of the physical page address exceeding the data bit width of the local memory 110 is stored in the excess address bit register 120.

[Effect]

When the physical page address obtained by the address conversion process is input to the physical page address processing means 130, the physical page address processing means 13
0 stores the bit part within the data bit width of the local memory 110 in the input physical page address at a specific address in the local memory 110,
The bit portion of the physical page address that exceeds the data bit width of the local memory 110, that is, the excess address bit portion, is stored in the excess address bit register 1.
Store it in 20.

In this case, the excess address bit portion is not specified by the upper or lower bits of the physical page address, but may be any portion of the physical page address.

When extracting a physical page address, the physical page address portion read from the local memory 110 and the excess address bit portion read from the excess address bit register 120 are combined to return the original physical page address. Furthermore, a real address for accessing the main memory (not shown) is created from this physical page address and intra-page address.

As described above, by storing only the excess address bit portion of the physical page address that could not fit into the local memory 110 in the excess address bit register 120 that is separate from the local memory 110, it is possible to use the conventional local memory 110. , it is possible to store a physical page address that has more bits than the data bit width.

〔Example〕

An embodiment of the present invention will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention.

(A) Configuration of Embodiment In FIG. 2, the local memory 110, excess address bit register 120, and physical page address processing means 130 are as described in FIG.

In the physical page address processing means 130,
131 is an address selection circuit, which selects local memory 1.
One of the normal address (a side) that accesses the normal data area stored in the 10 and the physical page access address (b side) that accesses the area where the physical page address is stored is selected.

Reference numeral 132 denotes an address register, which includes an excess address part in which the excess address bit part in the physical page address is set, and a page address body part in which the physical page address part (physical page address body part) stored in the local memory 110 is set. and an intra-page address section in which an intra-page address is set. In this embodiment, the physical page address is stored in the local memory 110 in order from the lower part, so that the upper address bit part of the physical page address that cannot fit into the local memory 110 becomes the excess address bit part. By doing this, it is possible to easily distribute and set the physical page address to the page address body part and the excess address part of the address register 132, and it is also easy to read out the excess address part and the page address body part. Furthermore, creation and reading of physical pages can be easily performed.

133 is a first address register input selection circuit (ADRSEL(1)), which selects the address part (b side) set in the page address body part of the physical page address and the physical page address body part read from the local memory 110. Select one (side a) and set it in the page address body.

134 is a second address register input selection circuit (ADRSEL(2)), which selects the excess address bit part (b side) in the physical page address and the excess address bit part (a side) read from the excess address bit register 120. Select one and set it in the excess address section. ADRSEL(1)133 and
ADRSEL(2) 134 operates on a common selection signal. T ₁ is an output terminal for normal data read from the local memory 110, and T ₂ is an output terminal for real addresses.

140 is a write data selection circuit that selects either the physical page address (b side) read from the address register 132 or the normal data (a side) from the arithmetic circuit, etc., and writes the data to the local memory 11.
Store at 0.

150 is an OR circuit which inputs to the local memory 110 a clock for storing normal data in the local memory 110 and a clock for storing the physical page address body part in the local memory 110.

(B) Operation of the embodiment The operation of the embodiment is a normal data storage operation,
The operations will be explained separately into a data read operation, a physical page address storage operation, and a physical page address read operation.

Normal data storage operation The address selection circuit 131 and the write data selection circuit 140 select the normal data side a. Normal data is applied to local memory 110 through write data selection circuit 140.

On the other hand, since the normal address is added to the local memory 110 through the address selection circuit 131, the input normal data is transferred to the predetermined address in the local memory 110 in synchronization with the normal data set clock applied from the OR circuit 150. Store in address area.

Normal data read operation The address selection circuit 131 selects the normal address side a to access the local memory 110. Normal data read from the local memory 110 is transferred to an arithmetic circuit (not shown) through the output terminal _T1 .

Physical page address storage operation Address selection circuit 131, ADRSEL(1)1
33, ADRSEL(2) 134 and write data selection circuit 140 both select the physical page address side b.

The physical page address obtained through address conversion processing is ADRSEL(1)133 and ADRSEL
(2) When input to 134, ADRSEL(1)133
selects the following physical page address part stored in the local memory 110, that is, the physical page address body part, and stores it in the address register 1.
32 page address body. On the other hand, ADRSEL(2) 134 is local memory 1
The upper physical page address portion that cannot fit into 10, that is, the excess address bit portion, is selected and set in the excess address portion of the address register 132.

When the physical page address body part set in the page address body part of the address register 132 is taken out, it is added to the local memory 110 through the write data selection circuit 140.

On the other hand, the physical page access address is passed through the address selection circuit 131 to the local memory 1.
10, the input physical page address body part is stored in the predetermined address area in the local memory 110 in synchronization with the physical page address set clock sent from the OR circuit 150.

The excess address bit portion set in the excess address portion of address register 132 is taken out and set in excess address bit register 120.

Physical page address read operation The address selection circuit 131 selects the b side,
ADRSEL(1) 133 and ADRSEL(2) 134 both select the a side. Write data selection circuit 1
40 does not work.

The physical page address body part read from the local memory 110 by the physical page address access address added from the address selection circuit 131 is sent to the page address body part of the address register 132 through the ADRSEL(1) 133. is set.

On the other hand, the excess address bit portion in excess address bit register 120 is set to the excess address portion of address register 132.

Furthermore, a predetermined intra-page address is set in the intra-page address field of the address register 132.

The physical page address set in the excess address section and the page address main section, and the intra-page address set in the intra-page address section are taken out together to the output terminal _T2 , and are used as a real address for accessing the main memory (not shown). form.

Although one embodiment of the present invention has been described above,
Each configuration of the present invention is not limited to each configuration of this embodiment.

As already stated, the excess address bit portion of the physical page address is not limited to the upper bit portion of the physical page address, but may be any portion of the physical page address.

Furthermore, the excess address bits are not limited to one specific address in the local memory, but may exist in a plurality of addresses in the local memory.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects can be obtained.

(b) Even if the number of bits of the input physical page address exceeds the data bit width of the local memory, the local memory can be used for storage without increasing the data bit width of the local memory.

(b) Since an excess address bit register is provided, the increase in hardware can be significantly reduced compared to the conventional method in which the data bit width of the local memory is increased.

[Brief explanation of drawings]

Fig. 1...Explanatory diagram of the configuration of the present invention, Fig. 2...
FIG. 3 is an explanatory diagram of the configuration of an embodiment of the present invention. In FIGS. 1 and 2, 110... local memory, 120... excess address bit register, 130...Physical page processing means, 140...
Write data selection circuit.

Claims (1)

[Claims] 1. Physical page address local memory 11 obtained by address conversion processing of logical page address
In the converted address storage method in which the converted address is stored in a specific area in 0, (a) an excess address bit register 120 that stores the bit portion of the physical page address that exceeds the data bit width of the local memory 110, and (b) an The bit portion of the physical page address that is within the data bit width of the local memory 110 is stored in a specific area within the local memory 110, and the bit portion of the physical page address that exceeds the data bit width of the local memory 110 is stored in the excess address bit register 120. A translated address storage method comprising: physical page address processing means 130 for storing physical page addresses in a physical page address storage system.