JPH0343837A - Debugging device - Google Patents

Abstract

PURPOSE:To smoothly carry out a debugging operation via an emulator even if the hardware of a user system includes a defective area by outputting the logical result of the signal extracted from an optional area of the user system via a leased memory contained in an emulator. CONSTITUTION:A rewritable memory ERM is added into an emulator and a sampling means HMPU is connected to an address input terminal and a data input/output terminal of the ERM via the signal switch circuits ACG and DCG. At the same time, such data that is set in a desired output state in a prescribed address input state is previously written into the ERM. Then the signal sampled out of a user system is inputted to the address input/output terminal of the ERM, and the data signal read out of the ERM is sent back to a prescribed area of the user system as a logical output signal. As a result, the ERM can be used as a substitute circuit for a logic circuit in the user system. Thus the emulation can be carried out even if the user system includes a defective area.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a debugging technique and a technique for evaluating a microcomputer system to be debugged, and relates to a technique that is effective when applied to an in-circuit emulator, for example. It is something.

[Conventional technology] In the development of microcomputer application equipment.

In-circuit emulators are used to debug the application system and perform detailed evaluation of the system. An in-circuit emulator is connected between a system development device such as a parent computer (host computer) or console for software development and an application device under development, and is connected to a microprocessor (hereinafter referred to as a target processor) included in the application device. It has the same functions as the debugger 1 while acting on behalf of the functions of the debugger 1.

In such an in-circuit emulator, the plug at the end of a cable extended from the main body is connected to the target microprocessor socket 1 provided in the application equipment, so that the emulation microprocessor can be connected to the target microprocessor. It has an emulation function that takes over the functions of a microprocessor. Furthermore, there is a real-time 1-race function that samples various data and status signals Z in real time during emulation and stores them in the trace memory section, and controls operation of applied equipment using the emulation microprocessor. Equipped with various debugging functions such as a break function that effectively stops the
(See I Handbook JP 562-563).

In addition, in order to enable debugging even when the user system is unfinished, conventional emulators provide services called lent memory, ■/○ lent, etc., in which the functions of the supported microprocessor are substituted by the emulator's internal functions. Functions are provided. With this lending function, you can develop programs for the mask ROM part and
The debugging efficiency of hardware related to ○ will be improved.

[Problems to be Solved by the Invention] However, in conventional emulators, the hardware for ROM and Ilo related to the functions of the microprocessor itself to be emulated is prepared inside the emulator, and the hardware is transferred to the user as needed. It was simply made available for use.

But when using the emulator in reality.

The hardware of the user system (for example, a logic circuit attached externally to a microprocessor) is incomplete, or
May contain defects. In such cases, with conventional emulators, you have to completely remove the hardware, or
Another problem was that emulation could not be performed without modifying the hardware.

An object of the present invention is to shorten the system development period by enabling debugging using an emulator without any problem even if the hardware of a user system includes unfinished parts or defective parts.

The features of this invention as well as other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[Step F for Solving 51 Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a rewritable memory such as a RAM is provided inside the emulator, and the address input terminal and data input/output terminal of this memory are connected to a host 1 to a microprocessor or a probe through a signal switching circuit such as a multiplexer. A sampling means can be connected, data is written in advance into the memory by the host 1 to the microprocessor so that a desired output state will be obtained in a predetermined address input state, and the data is connected to the address input/output terminal of the memory. The signal sampled from the user system by the probe is manually read out from the memory (No. 8 is used as a logic output signal) to be returned to a predetermined part of the user system via the probe. .

[Operation] According to the above-described means, the logical result of the signal extracted from any part on the user system can be output from the rental memory inside the emulator, and since the rental memory is a rewritable memory. , it is possible to output any logical operation result for the input, and the loaned memory operates as a pseudo logic circuit, and can be used as a substitute circuit for a desired logic circuit in the user system. This allows emulation to be executed even if the user system is incomplete or contains design errors.

[Embodiment 1] An embodiment in which the present invention is applied to an emulator will be described below with reference to the drawings.

First, the overall configuration of an emulator to which the present invention is applied will be explained with reference to the block diagram shown in FIG.

That is, the emulator of this embodiment includes a slave microprocessor 11 for emulation that performs the functions of the target microprocessor, an emulation control unit 12 that executes emulation and various debugging functions, and a processor that executes the progera 11 and stops tracing. A break control unit 13 that sets conditions and stops the program or trace when one condition is met, a trace memory unit 14 that sequentially stores signals on the bus during emulation execution, and memory for the application device (user system) are prepared. If not, the proxy memory unit 15. It consists of a serial interface 16 for data communication over 1 m with the parent computer and console 10, and a host microprocessor 17 for controlling them.

In the emulator, the tip of a cable extended from the main body of the emulator is connected to a microprocessor socket provided in an application device, so that the slave microprocessor 11 acts as a target microprocessor. slave microprocessor 1
1 performs proxy control (emulation) of the user's actual device, the slave microprocessor 11 is separated from the control of the mask microprocessor 17, and is broken when the control operation state of the slave microprocessor 11 reaches a predetermined state. When the microprocessor is activated, it is placed under the control of the master microprocessor. Furthermore, there is a 1-to-receive function that samples various data and status signals during emulation execution and stores them in the trace memory 15, etc., and a break function that stops the slave microprocessor 11 from controlling the application equipment. It has various debugging functions such as.

These functions are executed according to commands from the console 10.

FIG. 1 shows an embodiment of an emulation control section which is a main part of an emulator according to the present invention.

In this embodiment, separately from the proxy memory 15, a rewritable memory ERM such as a RAM (random access memory) serving as a lending logic circuit is connected to the host data bus HD via signal switching circuits DCG and ACG.
T and host address bus HA 13.

A probe Pi (Bl) is connected to the second output terminal of the signal switching circuit DCG on the data bus side.
The output data signal of the memory ERM for lending logic can be applied to any part of the user real layer (layer) via the probe PRBI. Input terminals include target bus TDT, '1' A B or probe FRB.
2 is connected so that any signal on the user system can be input to the address input terminal of the lending logic memory ERM.

As the signal switching circuit ACG, a circuit such as a multiplexer can be used, and as the signal switching circuit 17'M path DCG, a circuit such as a selector consisting of a transfer gate can be used.

Note that during emulation, the above loaned logic memory E
The chip select signal C8 that puts the RM in the selected state and the write enable signal WE that puts the RM in the read state are formed by external circuits (not shown) by the emulation switching m3 output from the host microprocessor II MPU. There is.

Next, the operation of the emulator of the above embodiment will be explained.

First, the signal switching IrIJ paths DCG and ACG are switched to the host bus side by a signal output from the host microprocessor II MPU (the output signal of the decoder DEC in the figure may also be used). At this time, the address input terminal of the rental logic memory ERM is connected to the address bus HA of the host microprocessor)-IMPU.
B, the C8 input terminal receives the decoded signal of the decoder DEC, and the WE input terminal receives the decoded signal of the host microprocessor II.
The read/write signal R/W from MPU is DATA
A data bus (IDT) of the host microprocessor HMPU is connected to the input/output terminal. This allows the host microprocessor II MPU to freely access the lending logic memory ERM. In this state, data corresponding to a logic signal to be applied to a predetermined part of the user system is written into a predetermined address of the rental logic operational memory ERM.

In this case, if the number of bits of the input logic signal to be sampled from the user system is smaller than the number of bits of the address signal 8, the input logic signal is input to the lower side (or upper side is also possible) of the address input terminal. ),
Desired logical output data may be written in all addresses corresponding to the desired logical output data.

Once the setting of the rental logic memory ERM is completed, connect the probe PRB 2 connected to the signal switching circuit ACG to the input of an unfinished logic circuit section on the user system or a circuit that is expected to have a design error. It is brought into contact with the terminal side, and the credentials to be input there can be input to the address input terminal of the lending logic memory ERM. Further, the probe PRB1 is connected to the output terminal side of the unfinished or defective circuit.

Start emulation after these preparations are complete.

Note that during emulation, the signal switching circuits DCG and ACG are switched to the probe side.

Then, the lending logic memory ERM is accessed by the input logic signal sampled from the user system, and a logic logic corresponding to the result of AND, OR, exclusive OR, or other preset desired logic operation is output, and the logic signal is output to the user system. is supplied to a predetermined part of the body. therefore.

Even if the logic circuit of the user system is incomplete or has a defect due to a single design error, emulation can be executed and debugging efficiency is improved. Also,
Even when it is desired to change a part of the user system, the same emulation result can be obtained 91) without changing the hardware, and the system development period can be shortened.

Furthermore, in the emulator of the above embodiment.

Logic memory ERM lends signals on the target bus connected to the user system via the signal switching circuit ACG.
For example, if the address decoder of the user system is expected to be defective, the signal on the target address bus TAB can be input to the memory E.
If the RM is operated manually and its output is returned to the user system as a decoded signal, the address decoder can be easily checked.

In the above embodiment, a RAM is used as the rental logic memory ERM, but a rewritable EP ROM or EEPROM may be used instead of the RAM. In that case, the data may be written in the emulator 7 by the host microprocessor, or it may be written using another FROM writer and then inserted into the emulator board.

Also, in the above embodiments, a memory is used as a lending logic circuit, but for example, how about using a memory element such as MNOS that constitutes an EPROM or an EEPROM as the memory of the ROM? , it is also possible to use a CPLA (programmable logic array).

As explained above, in the above embodiment, a rewritable memory such as a RAM is provided inside the emulator, and
A host microprocessor or sampling means such as a probe can be connected to the address input terminal and data output terminal of this memory through a signal switching circuit such as a multiplexer, and a predetermined address input terminal is input to the memory by the host microprocessor. Write data in advance that will result in a desired output state when the current state is active, input the signal sampled from the user system using a probe to the address input/output terminal of that memory, and read the data signal from the memory. Since the logic output signal is returned to a predetermined part of the user system via the probe, the rental memory operates as a pseudo-logic circuit that outputs the logical operation result for the input.

It can be used as a replacement circuit for a desired logic circuit in the user system, and this has the effect that emulation can be performed even if the user system is unfinished or contains design errors.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the embodiment, the loan logic memory.

Although we have described the case where the circuit operates as an alternative to a combinational logic circuit in which one set of output signals is determined for one set of input signals, multiple RAMs are cascaded, that is, the output of the previous memory is By connecting it to the address input terminal of the memory in the second stage,
It is also possible to configure it to operate as a logic circuit that outputs sequential signals.

Furthermore, in the above embodiment, the present invention is applied to a 2-CPU type emulator consisting of a target processor that executes the kneezabumigram and a host processor that controls the entire system, but an IC:PU type emulator that performs all controls only by the target processor The present invention can be similarly applied to. Furthermore, the present invention can be applied not only to microprocessors but also to single-chip microcomputers.

In the above explanation, the invention devised by the present inventor was mainly applied to an in-circuit emulator, which is the background field of application. It can be used in debugging tools, simulators, and other data processing systems with emulation functions.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, even if the hardware of the user system includes unfinished parts or defective parts, debugging can be performed by the emulator without any problem, and the system development period can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of essential parts of an emulator according to the present invention. FIG. 2 is a block diagram showing a schematic configuration example of the entire emulator to which the present invention is applied. HMPU...Host microprocessor, TM
PU...Target microprocessor, ERM...
...Loaned logic memory, ACG, I)CG...
Signal switching circuit, DEC...decoder, PRBL, P
RB2... Probe ((3 sand sampling means). Figure

Claims (1)

[Claims] 1. In a debugging device having a first microcomputer that performs functions of a system to be emulated and a second microcomputer that controls debugging, the preset values are set as described above. A debugging device characterized by having a rewritable logic means that outputs an output according to a signal output from a first microcomputer or a signal supplied from outside the device. 2. The device according to claim 1, further comprising a signal sampling means for extracting a signal from an arbitrary part of the external device, and a signal supplying means for supplying the value outputted from the logic means to the external device. debug equipment. 3. The debugging device according to claim 1 or 2, wherein said logic means is a random access memory, and a predetermined value is written in advance by said first microcomputer.