JPH0343863B2 - - Google Patents

Description

[Detailed description of the invention]

Relationship to Related Applications This application is related to U.S. Patent Application Nos. 626,999, 626,982, and 627,000, filed July 2, 1984. BACKGROUND OF THE INVENTION The present invention switches an AC motor from receiving power directly from a power bus to receiving power from a solid-state inverter, and
The present invention relates to control for switching an AC motor from a state in which it receives power from a solid-state inverter to a state in which it receives power directly from a power supply bus. In some applications, such as static starters for gas turbines, the purpose of variable speed solid state power converters is to replace diesel engines. This brings the turbine/generator up to a self-sustaining speed, at which point it fires the turbine and brings the generator up to speed such that it can be synchronized and switched to the power grid. An advantage of using solid state power converters is that one converter can be used to start one turbine and then switch to starting another turbine. In other applications, such as variable speed fan and pump drives, power converters are used to achieve variable speed operation, but it may be desirable to switch the electric motor to the power bus for sustained operation at high speeds. There is. In this type of drive device, if the power converter fails, the support device switches the motor to the power bus,
It is often used in critical applications where the process is designed to be controlled by some mechanical throttling means. In this case, the power converter is faulty, so switching is bumpless.
The power converter is disconnected from the circuit and the motor is switched to the power line. Shockless switching is defined as switching without causing unwanted current transients in the motor, inverter or power supply bus. Normal switching of a non-faulty power converter is to equalize the voltage and phase of the motor with the power bus, then make-before-break the motor with respect to the power bus.
This is done without impact by switching to the break method. The other half of the problem is to be able to switch the motor from the power supply bus to the power converter without shock. The purpose of this invention is to provide a phase-locked loop for controlling the firing of the transducer.
To provide control for shock-free switching of a motor from a power conditioner to a power source bus or from a power source to a power conditioner without requiring extra hardware in a motor drive device having a power source side converter and a load side converter. That's true. SUMMARY OF THE INVENTION In one aspect of the invention, an alternating current source powered from a power conditioner such that the power side converter and the load side converter of the power conditioner each use a phase-locked loop to control their respective firings. A method is provided for synchronizing a motor to a power bus. The method includes synchronizing a phase-locked loop of a power-side converter with an integrated power supply bus voltage and synchronizing a phase-locked loop of a load-side converter with a motor flux. Next, the phase error between the outputs of both phase-locked loops is determined and amplified. Add the amplified phase error and speed regulator setting. The set value of the speed regulator is the frequency of the power supply bus, so the speed regulator becomes an inverter frequency regulator. The voltage on the power supply side is compared with the pressure of the integral motor, and the difference is supplied to the magnetic flux regulator. This flux conditioner changes the magnetic flux to reduce this difference. After this, the AC motor is switched to the power bus. Another aspect of the invention provides a method for synchronizing an AC motor powered from a power bus to a power conditioner. The source and load side converters of the power conditioner each use a phase-locked loop to control the firing of their respective converters. The method includes coupling the power conditioner to the power supply bus without firing a controllable switch of the power conditioner's converter while the motor is still coupled to the power supply bus. The speed regulator should be deactivated. The phase-locked loop of the power-side converter is synchronized with the integrated power supply bus voltage, and the phase-locked loop of the load-side converter is synchronized with the motor flux. The motor current is then measured and used to generate torque commands for the power and load side transducers. In response to the torque command, a controllable switch in the load-side transducer is fired. The current supplied by the power-side converter is ramped upward to the same value being supplied to the motor in response to the torque command. The current provided by the power conditioner is compared to the motor current. When the current supplied by the power conditioner and the motor current are the same, the power bus is disconnected from the motor.
The speed regulator and flux regulator of the power conditioner are activated at the same time as the power bus is disconnected. The output of the speed regulator is initialized to the value of the current being supplied, and the set point of the flux regulator ramps downward to the value commanded by the torque vs. flux profile. While novel features of the invention are set forth in the claims, the structure, operation, and other objects and advantages of the invention will be best understood from the following description of the drawings. DETAILED DESCRIPTION OF THE INVENTION In Figures 1A-1D, an induction motor drive is shown that includes two parallel converters. The first converter in parallel is composed of a power-side converter, which is a phase-controlled rectifier 1 in this example, and a load-side converter, which is a current-controlled automatic successive commutation inverter 2 in this example. There is. During motor operation,
A phase-controlled rectifier 1 supplies a DC current of variable magnitude to an inverter 2 via a DC line reactor 5 . The first converter in parallel is also referred to in this specification as the master channel. The second converter in parallel, called the slave channel, consists of the same elements as the master channel, namely a phase-controlled rectifier 1' and an automatic successive commutation inverter 2', coupled by a DC line reactor 5'. It is configured. Primary side of triangular connection, secondary side of triangle connection, and 2nd side of Y connection
A three-phase transformer 7 with a secondary side couples the external three-phase power supply to the master and slave channels, respectively. The inverters 2 and 2' are Y-connected and triangularly connected.
It operates to supply 12 pulses, 6-phase power to the induction motor 9 via a 3-phase transformer 11 having a triangularly connected secondary side. The primary side of the wye connection is coupled to inverter 2 of the master channel, and
The primary side of the square connection is coupled to the inverter 2' of the slave channel. Commanded speed ω _r ^* is an input signal to the AC motor drive controller and is supplied to rate limiter 18 via switch SW1. The output of the rate limiter is compared in adder 19 with the speed reference signal ω _r . The speed reference signal ω _r is calculated by a slip calculator 20 from the motor current, magnetic flux, and firing angle of the master channel, and this slip is calculated by the switch.
It is generated by coupling via SW2 to a summing point 21 and subtracting it from the frequency ω _e of the power supplied to the induction motor 9 at the summing point 21 . The error signal emerging from the summing point 19 is supplied to a speed regulator circuit 25 having a transfer function of k(1+τs)/s, where s is the Laplace operator. The output of the speed regulator is the torque command T ^* . This torque command is sent to three control paths via switch SW4. The upper control path includes two phase controlled rectifiers 1,
1' current is controlled. The central control path controls the magnetic flux of the induction motor 9 by controlling the firing of the switching devices in the inverters 2, 2'. The center passage applies flux correction to the torque command T ^* supplied to the upper and lower passages.
Function block 33 converts the torque reference signal T ^* into a magnetic flux command ψ ^* . The function performed by function block 33 is to add an offset to ensure that a constant level of flux is obtained when the torque is zero. The flux command is provided via switch SW3 to summing point 35 where it is compared with flux signal ψ _p to form a flux error signal. The magnetic flux signal ψ _p is determined by integrating the output voltage of the inverter 2 with an integrator 37 and passing this signal through a peak detector 38 . The output of summing point 35 is supplied to limiter 43 via gain block 41 and switch SW5. The output of limiter 43 is supplied to addition point 45 together with the magnitude of torque command T ^* output from function block 36. The output of the limiter 43 is when the magnetic flux differs from the commanded value.
The current command is adjusted to convert the upper current control path into a magnetic flux regulator when the torque and command torque are both near zero. The flux error signal from gain block 41 is also provided to offset function block 47. The output signal from block 47 is coupled to multiplier 49 on the lower control path. Offset function block 4
7 produces an output of 1 when the flux error signal is zero. The output of offset function block 47 is when the commanded magnetic flux is greater than the actual magnetic flux.
1, reducing the angle between the motor current and the magnetic flux and diverting more of the available current to the flux generating axis. The flux correction current signal from summing point 45 is provided to function block 51, which generates current command I ^* . This current command is a current feedback signal at addition point 53.
Compared to I _FB . The current feedback signal is
An absolute value block 57 from a current sensor 55 on each of the three lines feeding the phase controlled rectifier 1 of the channel receives the three sensed line currents and provides a current feedback representing the magnitude of the three signals. Generates signal I _FB . Current regulator 59, which can be a proportional-integral regulator, generates voltage command signal V ^* in response to the current error from summing point 53. Voltage to firing angle converter 61, which may be implemented as a lookup table, generates firing angle command α ^* in response to voltage command V ^* received via switch 60. The firing circuit for the phase-controlled thyristor bridge, including the phase-locked loop integrator, zero-crossing detector, cell firing block and reduction counter, is the same as that described in U.S. Pat. No. 4,490,087. The three-phase line voltage supplied to the phase-controlled thyristor bridge is integrated in an integrator 63, and the zero crossing of the integrated voltage is determined in block 65 to generate a synchronized pulse train with a frequency six times the line frequency into a phase-locked loop. Formed against 67. A preferred form of apparatus available for integrating line voltage consists of the circuit described in U.S. Pat. No. 4,399,395.
This circuit operates between broken lines by means of commutation notches that appear in the waveform of each phase voltage during the time that each phase current is switched from one phase to another by appropriate firing of the individual thyristors. It acts to reproduce the voltage waveform. The line voltage reproduction preferred in this invention is as follows:
Adding at least one integrated line voltage with a commutation notch and a signal corresponding to at least one "triangle" current derived from the difference between the two phase currents multiplied by a multiple representing the commutation inductance. It consists of a composite waveform generated by When a zero-crossing signal occurs, the phase-locked loop 6
Read the time counter at 7. The correct reading of the time counter at this time is known, and the difference between the actual and correct values represents the phase error, which is passed through a software proportional-integral regulator. The output of the regulator provides a high frequency clock to the phase-locked loop counter such that the clock frequency from the phase-locked loop counter is 512 times the fundamental frequency of the line voltage supplied to the phase-controlled thyristor bridge. Represents the value used when dividing. The frequency 512 times the fundamental frequency has an angular resolution of 0.703 degrees of the fundamental frequency and acts as the clock frequency for the subtraction counter 69. Commanded firing angle α ^* is added to the cell offset from lookup table 71. By Lutskup Table,
One of six offsets is obtained based on the variable PH, which represents the next pair of cells to fire. Every time a cell fires, the variable PH is incremented. The term cell in this specification refers to a controllable switch or thyristor within a converter.
The variable PH, which can take values from 1 to 6 in total, indicates which pair of cells should be fired next, as shown in the table below. PH ON cell numbers 1 6 and 1 2 1 and 2 3 2 and 3 4 3 and 4 5 4 and 5 6 5 and 6 The bridge cells of converters 1 and 3 are as follows according to their firing order: A number is attached. 1 3 5 4 6 2 Phase A is connected between cells 1 and 4, Phase B is connected between cells 3 and 6, and Phase C is connected between cells 5 and 2.
connected between. The duration of each variable PH
60°, and each cell is fired by a 120° high frequency pulse train. The current count of the time counter in the phase-locked loop 67 on the power supply side is subtracted at a summing point 68 and the resulting value is loaded into a subtraction counter 69. When the subtraction counter 69 reaches zero, a signal is sent to the cell firing block 75 which fires the appropriate thyristor pair of the phase controlled rectifier 1 in the master channel and in block 73 sets the variable PH. Sends a signal to increase the number. To ensure proper load balancing between the master and slave channels, elements 53',
55', 59', 60', 61', 68', 69', 7
A separate current regulator consisting of 1', 73', 75' is coupled to the phase controlled rectifier 1' of the slave channel. The elements shown here with a dash are constructed and operate in the same manner as the equivalent elements previously described, except that the current feedback signal to summing point 53' is fed from the phase-controlled rectifier of the slave channel; At summing point 68' a firing angle offset of 30° is introduced and the cell firing signal for firing the next pair of thyristors from cell firing block 75' is
The difference is that it is coupled to the phase controlled rectifier 1' of the slave channel. A motor current flux angle generator 77 in the lower control path receives the torque command T ^* and generates the desired angle between motor current and motor flux. This motor current flux angle is modified by a multiplier 49 in response to a flux error signal from a gain block 41. The resulting motor current flux angle is converted from the motor current flux angle to the firing angle α by a converter 79
is converted to the equivalent firing angle α. The firing angle α is added in adder 81 to the offset determined by lookup table 83. This lookup table 83 contains one value for each variable PH representing the next pair of cells to fire.
It has 6 offsets. A counter 84 whose variable PH is incremented each time the inverter 2 is turned on.
obtained from. The output of adder 81 is the uncorrected time to fire the array, which is the master
Automatic sequential commutation type inverter 3 in the channel
corresponds to the time (expressed in degrees of angle) until the next pair of cells on the load side are fired. In the adder 87, a current-controlled commutation circuit allows
To compensate for the delay in the thyristor's current pickup when it is fired, a delay angle (in degrees) is subtracted from the uncorrected time to fire the array. This delay angle is determined by measuring the three line currents a, b, c from the master channel inverter using current sensor 89. The difference currents ab, bc, and ca are determined in block 91, which converts line currents into triangular connection currents. A zero crossing detector 93 generates a digital signal when a zero crossing of the difference current occurs and a 3 bit segment number representing the difference current having the zero crossing. These two sets of signals from the zero crossing detectors are provided to a line current pickup detector 95;
This detector determines which thyristor firing is associated with the time of the last zero crossing and current pickup. The difference between the actual current zero crossing and the intended zero crossing is determined in summer 97. The delay angle is input to an integrator 99, and the output of the integrator is clamped by a limiter circuit 101 having upper and lower limits of 0° and 120°, respectively. The “time to ignition” signal from the adder 87 is sent to the adder 105.
, the current count of phase-locked loop 103 is decremented to determine the "time to go." The remaining time is charged to the subtraction counter 107.
This downcounter is clocked by a clock signal from phase locked loop 103. When the down counter 107 times out, the cell firing block 111 fires the next pair of cells in the inverter 2 in the master channel. Integrator 3
7. Zero crossing detector 109, cell firing circuit 111
and reduction counter 107 operate similarly to the corresponding firing circuit described for the upper control loop.
To determine the firing time for inverter 2' in the slave channel, the remaining time from adder 105 is summed with the 30° signal in adder 110.
After 30 electrical degrees from the master channel inverter 2, the slave channel inverter 2' is ignited. When the output transformer 11 is connected as shown in FIG. 1D, the variable PH of the slave channel is one count ahead of the master channel. If the output of transformer 11 is 3
If the secondary side of the square connection is connected to the master channel and the secondary side of the Y connection is connected to the slave channel, the variable PH of the slave channel will lag behind the value of the variable PH of the master channel. The adjusted remaining time is loaded into a down counter 107' which is clocked by phase locked loop 103. Reduction counter 10
When time 7' expires, firing block 111' fires the next pair of cells of inverter 2' in the slave channel. Further details regarding the operation of the power-side ignition control system, including delay compensation, can be found in the aforementioned U.S. patent application Ser. No. 626,999. The primary side of the Y-connection and triangular connection of the transformer 11 is
The case where power is supplied from two parallel converters to a three-phase motor with a relative phase shift of 30° has been illustrated, but without introducing a 30° phase shift by a transformer, It is also possible to feed the phase motors. When using a six-phase motor, the output of each inverter is coupled to a different set of three-phase windings. If a fault condition such as overcurrent or shoot-through occurs on one or both channels, block 113
When detected, a signal is provided to switch controller 115 and via one input of two-input OR gate 117 to switch controller 115', causing switches 60, 60' to control their respective currents. Instead of the regulators 59, 59', converters 61, 61' from voltage command to angle command are used in the inversion limit block 1.
It is coupled to the reversal limit command from 19. The reversal limit command causes the firing pulses supplied to the phase-controlled rectifiers 1, 1' to be sent to the phase-controlled rectifiers up to the reversal limit, thus providing zero current to the two inverters 2, 2'. To ensure proper commutation of inverter 2 during light load conditions, a 6-pulse mode block 121
receives a torque command signal T ^* and a rotor speed signal ω _r and a light load high speed condition exists as determined by the speed exceeding the predetermined value and the torque being less than the predetermined value; Switch 60' is toggled by switch controller 115' to couple voltage command to firing angle command converter 60' to the reversal limit. When only one channel is operating at high speed and light load condition, the load of the remaining inverter 2 increases and its commutation time is kept below 120°,
Guarantees stable operation. The above describes the configuration of FIGS. 1A to 1D in the case of variable speed motor operation. Next, the driving format shown in FIGS. 1A to 1D regarding synchronization will be explained. Synchronization is the time just before switching the AC motor directly to the power supply, during which the phase error between the power supply bus voltage and the motor voltage increases between the signals θ _S and θ _L from the phase-locked loops 67 and 103. directly determined by the instantaneous difference between The signals θ _S and θ _L are compared in adder 125 and the resulting phase error is transferred to adder 1 via simple gain block 127 and switch SW4.
Sent to 29th. The speed command ω _{S YNC} from the phase-locked loop 67 is the switch, not the command speed ω _r ^* .
It is coupled to rate limiter 18 via SW1.
The output of rate limiter 18 is summed with the output of gain block 127 in adder 129. Switch SW
2 disconnects the slip calculator 20. A speed error is determined in adder 19. By comparing the absolute value of the power supply voltage V _S from block 131 multiplied by an appropriate multiplier in gain block 133 with the absolute value of the integrated motor voltage, the voltage amplitude error between the power supply bus and the motor is obtained. It will be done. The switch SW3 disconnects the function block 33, and by this switch,
The absolute value kV _S obtained by multiplying the power supply voltage by an appropriate multiplier is coupled to a summing point 35. Instead of this, the supply voltage V _S
can be integrated to determine its absolute value and compared with the motor flux. The error from summing point 35 is coupled to flux regulator 41 . Typically, the flux regulator settings are determined from the programmed flux versus torque profile of block 33 as dictated by the speed regulation profile of block 25. Inverter contactor 135 couples the secondary of transformer 11 to induction motor 9 when the inverter contactor is closed. The bypass contactor 137 couples the three-phase power bus to the induction motor 9 when the bypass contactor 137 is closed. Before closing the shunt contactor 137, the mains voltage is measured by a transformer (not shown) and this voltage is coupled to the inverting input of the amplifier 139 and output by the transformer (not shown). The measured motor voltage is coupled to the non-inverting input of amplifier 139. The absolute value of the difference signal from amplifier 139 is determined by absolute value circuit 141. Comparator 1
43 compares the output of the absolute value circuit with a reference level,
If the power supply voltage and motor voltage are equal, a logic 1 is generated. Before closing the inverter contactor, the absolute value of the inverter current I _ML of the master channel and the absolute value of the inverter current I _SL of the slave channel are compared in summer 145 with the absolute value of the motor current I _M . An absolute value circuit 147 coupled to the three-phase current by a current sensor 89 determines the absolute value of the master channel inverter current. An absolute value circuit 149 coupled to the three-phase current by a current sensor 151 determines the absolute value of the slave channel inverter current. An absolute value circuit 153 coupled to the motor three-phase current by a current sensor 155 determines the absolute value of the motor current. The difference signal from adder 145 is coupled to absolute value circuit 157. Comparator 159 compares the output of absolute value circuit 159 to a fixed reference level and returns a logic 1 if the motor current is equal to the sum of the master and slave channel inverter currents.
is generated, and the motor current is connected to the master and slave.
Generates a logic 0 when it is not equal to the sum of the channel inverter currents. When switching the motor from the power bus to the power conditioner, the inverter contactor 135
and connect the inverters 2, 2' to the motor.
Open the switch SW5 to disable the magnetic flux regulator 41. Switch SW4 is not a speed command,
It is in a position to generate a torque command based on the motor current I _M that has passed through the rate limiter 161. Comparator 159 tests to determine when the inverter voltage has increased enough to supply the full motor current and bypass contactor 137 can be opened. In the block diagram of Fig. 1, phase control rectifier 1,
A digital implementation of the components responsive to the speed error signal from adder 19 to fire 1' is shown in FIG. 2A. Next, referring to Figure 2A, the Intel 80286 microprocessor (MP) is programmed in the PLM 86 language.
222 is shown, which is manufactured by Intel.
It has a built-in interrupt program controlled by the 8259A interrupt controller 223. The controller 223 generates interrupts in a well-known manner that cause the microprocessor 222 to perform some task or computation and typically set a down counter to the time it takes to perform some future event. Store.
When the down counter reaches zero, the counter generates another interrupt, which starts the event, and after this,
The counter is reloaded with the time until the next event is executed. Referring to FIG. 2A, a software-based phase-locked loop is shown using four calculators. i.e. Phase Locked Loop (PLL)
a counter 224, a time counter 225, a master firing counter 226, and a slave firing counter 227. In operation, 4.9152 MHz output pulses from clock oscillator (OSC) 229 are sent from microprocessor 222 via data bus 230 to create a variable frequency source by phase-locked loop counter 124. Divide by the value N determined by the signal "Preset N". Counter 2
The output of 24 is maintained at a frequency 512 times the frequency of the individual magnetic flux waves ψ'ca, ψ'ab, and ψ'bc in the following manner. The time counter 225 is initially set to the value 512,
Each clock pulse from counter 224 decrements by one. When the counter 225 decreases to 1,
It will be reset to 512. For this reason, the counter 225 is
Provides a guideline for the phase angle for the magnetic flux waveform. The count of time counter 225 is sent via data bus 231 to microprocessor 222 which fires a phase control regulator thyristor (not shown) via firing mask buffers 232, 233. It is used as a phase reference for Synchronization is achieved by passing the pseudo flux waveforms ψ'ca, ψ'ab, ψ'bc through a zero crossing detector 234 which generates a synchronization pulse each time the flux waves cross zero. These pulses are transmitted to the interrupt controller 22.
3, which is supplied to the microprocessor 222
interrupt and start the crossover service program. Zero crossing detector 234 also generates a 3-bit number representing the relative sign of the motor flux waveform, which is sent to microprocessor 222 where it is read to determine which zero crossings cause an interrupt pulse. It is used to check whether an event has occurred. A zero crossover service program reads the value of time counter 225 and compares it to the correct value for a particular flux wave crossing to generate a phase error between counter 225 and the flux number. This error is used to calculate a new "preset N" and this value is used in the phase-locked loop counter 22.
4. The timing of the firing of each thyristor cell in the phase-controlled regulator 1, 1' is determined by a firing counter 22.
6,227. When master firing counter 226 is clocked down to zero, a master trigger interrupt signal is generated and provided to interrupt controller 223 and to firing mask buffer 232.
This buffer is loaded by the microprocessor 222 with an appropriate mask for the pair of cells to be fired next to the phase controlled rectifier 1 of the master channel. Similarly, when the slave firing counter 227 is clocked down to zero, a slave trigger interrupt signal is generated which interrupts the interrupt controller 223 and the firing mask buffer 233.
is supplied to In this buffer, the appropriate mask for the next pair of cells of the phase-controlled rectifier 1' of the slave channel is stored in the microprocessor 222.
It is charged from The microprocessor is A/
It receives the master channel and slave channel DC line current signals (I _MDC and I _SDC ) from the D converter 236 . This converter has a multiplexer (MUX) 2 coupled to these two signals.
38. The microprocessor also receives an error signal from the speed regulator via A/D converter 240. After firing a cell, microprocessor 222 calculates the time until firing the next cell of this phase controlled rectifier. This time is
It is compared with the value of time counter 225 corresponding to the current time. The difference in remaining time is fed via the data bus into a firing counter 226 or 227, which counter then decrements to zero and generates yet another interrupt via the interrupt controller 223, thereby causing the The cell firing program is then started. In the block diagrams of FIGS. 1A to 1D, an adder 19 is used to control the firing of the inverters 2 and 2'.
The digital configuration of the portion responsive to the speed error signal from the oscilloscope is shown in FIG. 2B. FIG. 2B shows an Intel 80286 microprocessor (MP) 302 programmed in the PLM86 language, which runs a built-in interrupt program controlled by an Intel 8259 interrupt controller 303. I have it. Controller 303
generates an interrupt in a well-known manner that causes the microprocessor 302 to perform some task or computation, typically storing time in a down counter until some future event is performed. When the down counter reaches zero, the counter generates another interrupt, which initiates that event, after which the counter is charged with time until the next event is executed. A phase-locked loop in software form is shown in FIG. 2B and uses four counters. namely, a phase locked loop (PLL) counter 304, a time counter 305, a firing counter 306, and a pulse train limit (PTL) counter 307. In operation, clock oscillator 30 is used to create a variable frequency source via phase-locked loop counter 304.
The 4.9152 MHz output pulse train from the microprocessor 302 is divided by the value N determined by the signal "Preset N" sent from the microprocessor 302 via the data bus 309. The output of the counter 304 is
As described below, the individual magnetic fluxes ψ′ca, ψ′ab,
The frequency is maintained at 512 times the frequency of ψ′bc. Time counter 305 is first set to a value of 512 at the crossover of a particular flux wave and is decremented by one on every clock pulse from counter 304. When the counter 305 decrements to 1, the value 51
It is reset to 2. Therefore, the counter 305 provides a measure of the phase angle with respect to the magnetic flux waveform. The count in time counter 305 is sent via data bus 310 to microprocessor 302 where it is used as a phase reference for firing the inverter cells (not shown) via digital I/O port 111. used as. Pseudo magnetic flux waveform ψ′ca, ψ′ab,
Synchronization is achieved by passing ψ'bc through a zero-crossing detector 312, which generates a synchronization pulse each time the flux wave crosses zero. These pulses are sent to interrupt controller 303, which interrupts microprocessor 302 to initiate the crossover service program. Zero crossing detector 312 also generates a 3-bit number representing the relative sign of the motor flux waveform, which is sent to microprocessor 302 for reading and determining which zero crossing was the basis of the interrupt pulse. Used for confirmation. Zero crossover service program time counter 3
05 and compares it to the correct value for the particular flux wave intersection to generate the phase error between the counter 305 and the flux wave. This error is used to calculate the new "Preset N" value,
This value is loaded into phase locked loop counter 304. There can be a significant delay between the time the ignition signal is applied to the thyristor and the time when this thyristor starts conducting in the current-controlled inverter feeding the induction motor, and when the motor speed is high and the motor load is light. Sometimes, especially so. This delay is
This is due to the fact that the commutating capacitor is discharged so that no current flows through it until the particular thyristor that is fired first becomes reverse biased and the commutating capacitor discharges through the load. be. This delay must be compensated for to maintain the desired relationship between motor flux and current.
The time at which current actually flows is measured by a zero crossing detector 313 which monitors the motor line differential current for zero crossings and generates an interrupt signal to the interrupt controller 303 each time a zero crossing is detected. Interrupt controller is microprocessor 3
02 and starts the delay determination program. Zero-crossing detector 313 also generates a 3-bit number representing the relative sign of the motor difference current, which is sent to microprocessor 102 for reading to determine which thyristor is associated with the zero-crossing. used to do. A delay determination program compares the current crossing time to the uncorrected time to firing (based on the angle command and offset) and inputs this value via the gain to the software integrator to determine the delay angle. The delay angle is clamped between 0° and 120°. Since commutation delay is a time-constant phenomenon, the need to compensate for this delay decreases as a function of speed. Therefore, since the sampling rate of the compensator is six times the load frequency, this causes the gain of the regulator loop to substantially track frequency, essentially stabilizing the compensator. The time to ignition is then determined as the uncorrected time to ignition minus the delay angle. The remaining time is determined by subtracting the reading of the hour counter from the time to ignition; therefore, the remaining time, measured in degrees of angle, is loaded into the subtractive counter and When clocked down to count zero, an interrupt is generated requesting the firing of the next cell. The timing of firing of each thyristor cell in inverter 2 is determined by firing counter 306 . After firing one cell, microprocessor 302 calculates the time until firing the next cell. This time is the uncorrected time to ignition minus the integrated delay angle. This time is compared with the value of time counter 305 corresponding to the current time. The difference is the time remaining, which is fed via the data bus into the firing counter 306, which counter then decrements to zero and causes yet another interrupt via the interrupt controller 303; It starts the cell firing program. FIG. 3A shows the sum of the integrated line voltage Vab and the triangular current ab multiplied by a coefficient K proportional to commutation inductance. The waveform of FIG. 3A is generally sinusoidal with well-defined zero crossings, although commutation notches occur in each phase voltage. Figures 3B and 3C show the integrated line voltages Vbc and Vca, respectively, summed with the triangular currents multiplied by appropriate multipliers. The phase-locked loop has two counters (a phase-locked loop counter and a time counter) and three comparators, and these comparators change the state depending on the polarity of the integrated power supply side or load side line voltage. The computer is supplied with three logical bits representing . The outputs of the three comparators are shown at D, E and F, respectively, in FIG. These three bits indicate the instantaneous angular relationship of the three phase voltages within a 60 degree range. The output of the comparator is
It is also used to derive an interrupt pulse in hardware at each zero crossing of the integrated voltage. That is, as shown at G, H, I, and J in FIG. 3, an interrupt is generated every 60 degrees. To explain the operation, the phase-locked loop counter is a subtractive counter that clocks at 5MHz. A value to be divided by N is loaded, the counter subtracts to zero, and then calculates the power supply side or load side voltage. It is designed to generate 512 output pulses per period of the fundamental frequency. To this end, the phase-locked loop counter generates a 360°/512, or 0.703°, clock pulse that is used to run the firing counter, time counter, and, on the load side, the pulse train limit counter. Performs clock operations. All three of these are reducing counters. The time counter on the load side is initially charged with a count of 512 at the time corresponding to the change of the integrated voltage Vbc from the negative side to the positive side. This time also corresponds to a change in the phase-to-phase voltage Vab from the plus side to the minus side. time counter is 1
When the count is down to 512, the 512 is loaded again and continues to decrement by one count per clock pulse.
The operation of the time counter on the power supply side is similar, but for some rather arbitrary reason, it is better to insert 512 into the time counter first than when the phase voltage Vab changes from the negative side to the positive side. The difference is that it is performed when the time counter is shifted by 180 degrees from the time counter or the time counter on the load side. This displacement between the time counters must be taken into account when phase synchronizing the load side voltage with the supply side voltage. The purpose of the phase-locked loop is to adjust the charge of the divide-by-N value to the phase-locked loop counter so that the clock pulses coming out of the phase-locked loop counter are 512 times the fundamental frequency. . Details vary depending on the frequency range of the load from 0 to 120Hz,
There are some differences between the power supply side and the load side, but the idea is the same. When a zero crossing of the magnetic flux wave (integrated line voltage) occurs, a high priority interrupt program is generated and reads the three bits of the time counter and comparator to determine which zero crossing has occurred. . The correct value of the time counter for a particular zero crossing is known, and the difference between the correct value and the actual value represents an error signal that is input to the proportional-integral regulator. The output of the regulator is the updated charge value divided by N for the phase-locked loop counter. The time counter therefore determines the angular position θ with a resolution of 0.703°, and the fundamental frequency of the voltage wave is proportional to a constant multiple of the reciprocal of the charge value divided by N thus calculated. The frequency value thus retrieved is used as a speed feedback signal for the synchronous motor drive of the present invention to compensate for slippage and then used as speed feedback for the induction motor drive. However, when commanded to synchronize with the power supply, the speed regulator is changed to a frequency regulator, so there is no longer load frequency slip correction for the induction motor drive. One purpose of synchronous control is to equalize the frequencies on the power supply side and the load side, which are taken from the charge value divided by N for the phase-locked loop counters on the power supply side and the load side, and after making corrections for any displacement, The purpose is to synchronize the angular positions θ on the power source side and the load side by making the instantaneous values of the time counters on the power source side and the load side equal. FIG. 4 shows a simplified block diagram of the synchronous control device of the present invention. As also shown in FIGS. 1A to 1D, the transformer 7 is connected to a master channel consisting of a power-side converter 1, an inductor 5, and a load-side converter 2, and equivalent elements 1', 5', and 2. ′
and a slave channel configured with a three-phase power supply bus. The transformer 11 connects the two channels to the induction motor 9 via the inverter contactor 135.
join to. The power supply busbar is directly connected to the electric motor via a bypass contactor 137. An integrator 63 is coupled to the master channel power supply voltage to generate an integrated line voltage signal, and a comparator 401 determines the number of segments on the power supply side. A signal equal to six times the fundamental frequency of the 60 Hz power supply is determined from the output of comparator 401 in block 403, a zero crossing detector. An integrator 37 is coupled to the master channel inverter voltage to generate the motor flux signal and a comparator 405 generates the segment number. From the segment number from comparator 405, a zero crossing detector in block 407 determines a signal equal to six times the fundamental frequency supplied to the motor. The absolute values of the integrated voltage wave and magnetic flux wave are determined in blocks 409 and 411, respectively. After the two signals are analog-to-digital converted in blocks 413 and 415, respectively, the two signals are compared at a summing point 417 and supplied to a low-priority program 419 of the microprocessor 222, which is the power supply side control device. A signal representing six times the fundamental frequency of the power supply is coupled to the power supply interrupt chip 223. All signals crossing the dotted line 421 in FIG.
02 and 222 by a communication bus. Power supply interrupt chip 223 provides interrupt signals to low priority program 419 and high priority source program 423. The number of segments from the load controller is provided to the high priority source program 423. Low priority source interrupt program 419
The output of is a flux correction to the firing angle signal which is transmitted to the load control firing angle program 425 of the load side microcomputer and a load speed regulator program 42 also located in the load side microcomputer.
Adjustment of the speed set point for 7. Next, Figure 1A to Figure 1D, Figure 2A, Figure 2B
The operation of the configuration shown in FIG. 4 will be explained. To extract the phase error between the supply voltage and the load voltage, the zero-crossing signal of the "flux" wave on the load side and the 3 bits of the load side comparator indicating which 60° interrupt has occurred are
The signals are sent from adder 417 and block 407 to the power supply side control device, respectively. The zero crossing signal generates a high priority interrupt program 423 in the power side controller, which looks at the 3 bits of the load side comparator and
Read the time counter on the power supply side for zero crossings that represent positive or negative zero crossings of the integrated load voltage. If the supply and load voltages are synchronized, the correct reading of the supply side time counter for any particular load side zero crossing interrupt is known in advance. Thus, the difference between the actual reading of the power supply side time counter and the known correct reading at the time of a particular load side zero crossing interrupt represents the phase error between the power supply voltage and the load voltage. Assume that the motor is being driven by a power conditioner and a command is issued to switch to the power bus. The speed setpoint is changed to a frequency setpoint equal to the power bus frequency and sent to the speed regulator via the rate limiter. The frequency setpoint can be generated from the power supply bus or from a phase-locked loop on the power supply side. When the speed feedback is within a preset tolerance from the speed setpoint,
The phase regulator and voltage equalization regulator are activated simultaneously. The phase adjuster passes the phase error between the power supply and load determined as described above through a gain block, adds the resulting signal to the speed (frequency) setting value, and adjusts the load output frequency to the phase error. so that it changes so that it becomes zero. That is, if the phase of the load lags behind the phase of the power source, the phase error increases the frequency setting value, and the motor torque is increased so that the phase error becomes zero. Although the phase error passes through a simple gain block, the regulator has an inherent integral in the loop due to the velocity-to-position conversion of the phase feedback signal.
This is a type 1 system. Therefore, the loop adjusts the phase error to zero. A unique integral is not recognized, for example, the phase adjuster is a proportional + integral type adjuster,
If a 1 rad/sec speed regulator is supplied with a 0.1 rad/sec crossover, the system will run very sluggishly and the resulting performance will be unacceptable. Using a phase regulator with simple gain, the response of the phase regulator can be compared to that of a speed regulator. For reasons explained later, it has been found that when entering synchronous mode, it is necessary to have a speed regulator gain of approximately 4:1, or a loop crossover of 4 rad/sec. Without increasing the gain of the speed regulator in this way, the phase regulator would tend to change by 30° from its desired value, as if there were a disturbance in the loop trying to move the regulator away from its zero point. be.
This disturbance can be explained with reference to FIGS. 5A-5D. First, consider the 6-pulse current controlled inverter induction motor drive shown in FIG. 5A. Typical DC line voltage waveforms on both sides of the DC line reactor are shown in Figures 5B and 5C. The difference between these two waveforms is the voltage applied to the DC line reactor, which causes a current ripple in the DC line, which causes a small torque disturbance in the motor. If both the source side and load side converters are operating at 60Hz when trying to synchronize, the frequency of the current ripple in this DC line is 720Hz as shown in Figure 5D.
However, when synchronization is just achieved, the instantaneous ripple voltage is at its maximum and its frequency drops to 360Hz.
Both factors result in maximum current ripple in the DC line. As a result, the torque disturbance becomes maximum, and in a load device with small inertia, a small speed disturbance may occur that forces the phase adjuster away from the point at which it is intended to operate. Having extra gain in the speed regulator helped overcome this torque perturbation, eliminating phase modulation around the desired operating point. It should be mentioned that increasing the response of the voltage equalization regulator, which will be explained later, also helps overcome this disturbance, but in the final device of this invention, for other reasons. , chose to have extra gain in the speed regulator. The current controlled inverter induction motor drive of the preferred embodiment is a 12 pulse device and the power conversion bridge is rated for 700 to 900 volts. Since most electric motors drive 4160 volts, we use 4160:800 volt transformers on both the input and output sides of the power converter. Typically, these transformers have a triangular input and triangular and wye-wired secondary sides, producing two sets of three-phase voltages that are 30 degrees out of phase. The control devices of the two channels are similarly displaced by 30°. This results in a 12-pulse operation. That is, the fifth and seventh harmonics are removed from the input and output current waveforms. Channel transformer 11 with triangularly connected secondary winding of transformer 7
Regarding the phase synchronization problem associated with transformer/bridge formats that also have triangularly connected primaries, both six-pulse channels add to the problem:
The problem is twice that of a 6-pulse device. However, by swapping the output transformer windings, i.e.
As shown in Figures 1D and 4, the transformer 1
The triangularly connected primary winding of transformer 11 is connected to a channel having a transformer 7 having a Y-connected secondary, and the Y-connected primary winding of transformer 11 is connected to the triangularly connected primary winding of transformer 7. By connecting the channel with the secondary side and taking this phase shift into account in the controller, a zero phase error between the supply voltage and the load voltage on the high voltage side of the transformer is achieved in the DC line reactor. , it has been found that phase locking is simplified in that it occurs at the time of the minimum ripple current, rather than the time of the maximum ripple current. No problems arise from switching the transformer connections. The invention can work in drives that do not use a transformer to couple the inverter to the motor without switching the transformer connection. As previously stated, when a command is issued to synchronize the motor to the line, and the motor and line frequencies are equal, both the phase adjuster and voltage equalization adjuster are operated simultaneously. The voltage equalization regulator was previously described.
To achieve voltage equalization in the induction motor drive, the set point of the flux regulator is switched from block 33 of the flux versus torque command profile to the integrated or suitably multiplied supply voltage amplitude kV _S of block 133. To prevent current transients, the setting value of the magnetic flux regulator is changed from one state to the other using a ramp function. Flux regulator 41 is a proportional-integral regulator with a crossover of about 1 rad/sec. This regulator is shown in FIGS. 1A-1D. Note that the flux regulator acts on both the source current regulator and the load firing angle regulator. When the load is light, the magnetic flux is adjusted mainly through current, and when the load is heavy, the magnetic flux is adjusted mainly through controlling the angle of the load. Once a command is issued to switch the motor to the track,
The potential transformers 429 of FIG. 4 on each side of the shunt contactor ensure that the voltage across the contactor is zero when both the phase and voltage are equalized within predetermined tolerances. After thorough inspection, close the bypass contactor and then open the contactor between the inverter and the motor. Typically, once the motor reaches 60Hz, approximately 1 second is required for phase synchronization and voltage equalization before closing the shunt contactor. The above describes the case where the motor is switched from the power conditioner to the power bus. The other half of the problem is when an out-of-synchronization command switches the motor back to the power conditioner. To this end, while the bypass contactor is still closed, the contactor from the motor to the power conditioner is closed before firing the thyristor in the power converter. Since the controller is in idle mode and the motor voltage is present, the load-side phase-locked loop is synchronized to this motor (supply voltage). Once the source-side and load-side phase-locked loops are synchronized to their respective voltages within a given tolerance, load-side diammetric circuits can be used to By issuing a command to fire two thyristors connected to the same phase and at the same time issuing a command to the current of the power supply side converter to limit the current flow, both 6-pulse pulses on the load side are Short the channel. The purpose of the anti-phase circuit is to accumulate current in the DC line, fire the appropriate thyristor, and prevent the anti-phase circuit on the load side from firing.
The purpose is to charge the commutating capacitor to such an extent that it commutates the load current upon subsequent ignition. If the load side stops firing its antiphase circuit, the power source side will
The current is increased according to a ramp function up to the value currently flowing in the motor being powered from the power supply bus. During this time, the speed regulator on the power converter is deactivated and the power converter essentially operates as a torque controller. In addition to supplying the correct value of current and synchronizing the load side with the motor voltage,
The load side must fire at the correct angle.
This is determined by using the same firing angle versus torque profile used to operate as the motor drive. That is, the firing angle follows the command torque. When the sum of the currents of the two 6-pulse converter channels is equal to the motor current, the current supplied from the power supply bus is zero, and therefore:
At the same time as opening the bypass contactor, the speed regulator and magnetic flux regulator of the power converter are activated, and the output of the speed regulator is initialized to the currently supplied current, and the setting value of the magnetic flux regulator is also set. From the existing magnetic flux level, block 3 in Figures 1A to 1D
It is responsible for decreasing according to the ramp function to the normal value dictated by the torque vs. flux profile of 3. A preferred embodiment of the invention is a 12-pulse induction motor drive. The present invention can also be used in a 6-pulse AC motor drive system having a power-side converter and a load-side converter, both of which use a phase-locked loop to control the firing of the converter. The same procedure can be used to achieve synchronization in a synchronous motor drive such as that described in U.S. Pat. However, the difference is that there is no need to set an anti-phase path in the load-side converter during the desynchronization process. Since the current is commutated by the inverter load of the synchronous motor drive device, there is no need to provide a commutation capacitor. The above is a motor drive system that has a power-side converter and a load-side converter, each using a phase-locked loop to control the firing of the converter. A control device for switching from a conditioner to a power bus or from a power bus to a power conditioner without impact has been described. Although the invention has been particularly illustrated and described with reference to preferred embodiments, those skilled in the art will recognize that various modifications may be made within the scope of the invention. The following appendix describes the computer program of the software module in the PLM language.

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1 and 1A to 1D are block diagrams of a 12-pulse parallel converter drive device using the present invention, and FIGS. 2A and 2B are power supply side and load side conversions of the drive device of FIG. 1. FIG. 3 is a waveform diagram showing various waveforms with respect to a common time axis to explain the operation of the present invention, and FIG. 4 is a diagram showing the hardware of a digital embodiment of the device control device. FIG. 5A is a simplified block diagram of the synchronous control device of the invention, FIG. 5A is a schematic diagram of a 6-pulse current control inverter induction motor drive device, and FIGS. 5B to 5D are waveform diagrams for explaining the operation of the invention. (Explanation of main symbols), 1: Power supply side converter, 2:
Load side converter, 9: AC motor, 37, 63: Integrator, 67, 103: Phase locked loop, 135:
Inverter contactor, 137: Side path contactor, 40
9: Absolute value circuit (integrated voltage), 411: Absolute value circuit (magnetic flux wave), 417: Addition point, 419: Low priority program, 422: Microprocessor (source side), 423: Power supply side interrupt chip, 42
5: Load side firing angle program, 427: Load side speed regulator program.

Claims (1)

[Claims] 1. An AC motor receives power (voltage and current) directly from a power bus or from a power conditioner connected between the power bus and the AC motor.
the power conditioner has a source-side converter and a load-side converter, each converter having a controllable switch and operating in a motor speed control loop and a motor torque control loop. In a motor control device of the type that controls the conduction state of the controllable switch in response to each phase-locked loop and thereby controls the operating state of the AC motor, the AC motor is connected to the power bus line, the AC motor having the following steps: (a) switching the power conditioner between supplying power from the power source and supplying power from the power conditioner without conducting the switch of the converter of the power conditioner; (b) allowing each of the phase-locked loops to reach a steady state of operation; (c) disabling the speed control loop; (d) measuring motor current and setting it to (e) applying the current feedback signal to the torque control loop to generate a torque command; (f) controlling the power converter in response to the torque command to (g) in response to the torque command, controlling the load-side converter to control the angle at which the controllable switch conducts; (i) when the current supplied by the power conditioner and the current of the motor are substantially the same, the power supply bus is removed from the motor; (j) activating the speed control loop of the power conditioner simultaneously with disconnecting the power supply bus, and initializing the output of the speed regulator to the value of the currently supplied current; 2. The phase-locked loop further operates with a magnetic flux regulation loop, disabling the flux regulation loop when the speed control loop is inactive, and activating the velocity regulation loop when the speed control loop is activated. 2. The method of claim 1, wherein the set point of the magnetic speed regulation loop is changed to the value required by the torque command. 3. The power conditioner includes two paths each having a power side converter and a load side converter,
2. The method of claim 1, wherein the current supplied to the motor by the power conditioner comprises the sum of the two paths of current.