JPH0344128A - Error corrector - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a code error correction device for digital information signals, and in particular to an error correction device that can obtain high error correction performance even when many code errors occur. Regarding equipment.

[Conventional technology]

A conventional code error correction device with high correction capability is disclosed in Japanese Patent Application Laid-open No. 57
- As described in Publication No. 10561, after doubly encoding the transmission data and decoding the @2 error correction block, for errors that cannot be corrected, a pointer is added to each word in the block, and the first By determining the state of this pointer during error correction and block decoding, the error correction capability is improved and the occurrence of error detection errors and erroneous corrections is prevented.

[Problem to be solved by the invention]

The above-mentioned conventional technology only prevents the playback signal from being seriously affected by preventing error detection errors and error corrections from occurring even when there are relatively many code errors. Therefore, no consideration is given to improving the ability to correct code errors even when there are many such code errors, and there is a problem in that the quality of the reproduced signal deteriorates.

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to provide a configuration of an error correction code and a decoding device for the same, which has a high error correction ability with little deterioration in the quality of reproduced imprint codes even when there are many code errors. There is a particular thing.

[Means to solve the problem]

The above purpose is to repeatedly record or transmit multiple encoded transmission data multiple times, and when decoding, for example, 85 times of doubly encoded transmission data is missed and recorded or transmitted. The second error correction block of the recorded or transmitted data is sequentially decoded, and then the second error correction block in which at least a code error exceeding the error correction capability is detected is
For the error correction block, decode the corresponding second error correction block of the second recording or transmission data,
Furthermore, if a code error exceeding the error correction capability is detected in at least the second second error correction block, the fifth recording or decoding of the corresponding second error correction block of the transmitted data is performed. , then these 3
This is achieved by decoding the first error correction block by preferentially combining blocks with no code errors exceeding the correction ability among the six second error correction blocks that have been decoded twice.

[Effect]

According to this method, if there are too many code errors in the transmission data of @1 that cannot be corrected, the erroneous signal is transferred to the second. Corresponding 41 in the fifth data block
Therefore, even if a code with many code errors is input, the possibility that an incorrect number 16 will be mixed into the output can be extremely reduced. [Example] The present invention will be explained below using the drawings. Detailed explanation of.

FIG. 2 is a schematic diagram of a product code block which is an input signal to the error correction circuit of the present invention, in which 15 is a signal group, 14 is an outer code group, and 15 is an inner code group. In contrast, the signal elements a□*att+*&mlk arranged in the first column in the vertical direction in the figure of the signal group 15 arranged in a matrix are converted into outer codes α0. α4
−α is added. Outer codes are also added to signal elements in the second column and below using a similar method. On the other hand, the inner code β, l−β, t are also calculated by Reed-Solomon method etc. for the 4 i sign elements, a++ m att a+n 4, which are arranged horizontally in the figure in the signal group 15.
is added. The inner code is also added to the second and subsequent columns and to the outer code 14.

This credibility group 15. Outer code 14. And from inner code 15,
A product code block is constructed.

FIG. 3 is a block diagram of an error correction circuit according to an embodiment of the present invention. A first product code block is input as an input, and an inner code decoding circuit 21 performs error detection and correction using the inner code. The first product code block signal after error detection and correction is held in the product code block storage circuit 22. At that time, if there is an error that cannot be corrected, the error value is W! An error flag indicating this is stored in a delay circuit 27 which can be configured with a memory or the like, and is delayed until the corresponding data of the @2 product code block is output. Next, the inner code decoding circuit 21 performs error detection and correction on the signal of the second product code block, and the output thereof is recorded on the first product code of the storage circuit 22. At that time, by inputting the error 7 lag of the corresponding signal of the first product code to the overwrite permission signal, the data in the second product code that corresponds to the block is read only when the data of the first product signal block is uncorrectable. It will be overwritten.

The product signal block created in this way is subjected to error correction by the outer code decoding circuit 24 and output.

Changes in code block data during this series of signal processing will be explained using FIG. 1. In the figure, 1 is a first product code block, 2 is a second product code block, and has the same configuration as in FIG. 2, of which 5.8 is a signal, 6.9 is an outer code, 7.10 is the inner code. On the other hand, 5 is the product code block output from the product code block storage circuit 22 in FIG. 5, and 4 is the output of the outer code decoding circuit 24. This is an example in which the A and H signal blocks in the first product code block 1 contain errors that cannot be corrected.

@5 Signal 1 of the first product code block input to the inner code decoding circuit @21 in the figure is subjected to error detection and correction for the signal blocks arranged horizontally in the figure, and the signals A and H are processed. is discovered to have an uncorrectable error. This information is stored in delay circuit 1N123 and signal 5. Outer code 6J
It is held in the product code block storage circuit 22 along with blocks P:, A, and B (arrow ■ in FIG. 1). Next, the signal of the second product code block 2 is also subjected to similar inner code decoding. After that, the signal A, which was uncorrectable in the first product code block,
Only the signals A/ and B/ corresponding to H are overwritten on A and B by the product code block storage circuit 22 (arrow ■ in Figure 1).
.

As a result, a new block 58 created on the product code block storage circuit 22 is sent to the outer code decoding circuit 24, correction is performed using the outer code, and a corrected signal 4 is output.

By having such a configuration, the first. Even if there are many errors in the signal of the second product code block, the correct output can be obtained by selecting the correct signal from both and creating a new block.Furthermore, in this circuit, the two product code blocks However, since only one product code block storage circuit 22 is required, the circuit scale can be reduced.

Figure @4 is a block diagram of an error correction circuit according to another embodiment of the present invention. In this embodiment, after performing inner code decoding on the first product code block and storing it in the product code block storage circuit 22, the inner code decoding circuit 21 performs error detection on the second product code block. Correction is performed, and an error flag is set on an uncorrectable signal in the second product code block. In order to overwrite only the signal without this error flag in the product code block storage circuit 22, it is inverted by the error flag 825 and inputted as an overwrite permission signal, and the data of the second product code block without an error is overwritten. Even with this configuration, a new block can be created by collecting the correct signals in the first and second product code blocks, similar to the circuit shown in Figure 5, so a highly reliable output can be achieved. I can do it. Furthermore, since this circuit does not require the error flag delay circuit 25, the circuit scale can be reduced. FIG. 5 is a block diagram of an error correction circuit according to another embodiment of the present invention. 1. This uses both error flags of the second product code block. In this circuit, the first
The error detected and corrected signal for the product code block in the inner code decoding circuit 21 is recorded in the product code block storage circuit 22, and the error flag at that time is recorded in the delay circuit 25 for the error flag corresponding to the second product code. Delay until sign. Next, the inner code decoding circuit 21 performs error detection on the second product code block.
Make corrections. Then, the signal of the second product code block is
An overwrite permission signal is created so as to be written into the product code block storage circuit 22 only when the corresponding first product code signal has an error flag and the second product code signal does not have an error flag. By doing this, the signal of the second product code block is corrected only when the signal of the first product code block is uncorrectable and the signal of the second product code block is not in error or has an error within the correctable range. 6 is a block diagram of an error correction circuit according to another embodiment of the present invention. Gate 27 in front of
is provided, and inner code decoding is performed only on the part to be used of the signal of the second product code block. All data of the first product code block passes through the gate 27 and is subjected to error detection and correction by the inner code decoding circuit 21. At that time, the error 7 lag indicating that it cannot be corrected is detected by the delay circuit 23.
is delayed to the corresponding signal of the second product code block.

The gate 27 controls the second product code block to pass through only when the signal of the corresponding first product code block cannot be error corrected. Game) 27fi
: The passed second product code block signal undergoes error detection and correction in the inner code decoding circuit 21, and is overwritten on the corresponding signal in the product code block storage circuit 22. At this time,
Since the product code block formed in the product code block storage circuit 22 is the same as that in the case of FIG. Since the time spent there can be shortened as much as possible, the amount of consumed power can be reduced.

FIG. 7 is a block diagram of an error correction circuit according to another embodiment of the present invention. In this circuit diagram, the inner code decoding circuit 21
A gate 278 is provided in front of the inner code to decode only the necessary amount of signals of the second code block, and only correct ones of them are overwritten. All data in the first product code block passes through the gate 27 and is subjected to error detection and correction in the inner code decoding circuit 21. The error flag indicating the uncorrectable state at that time is delayed by the delay circuit 25 to the corresponding signal of the second code block. Gate 27 is
The second code block is controlled to be passed only when the signal of the corresponding first code block cannot be error corrected. The signal of the second product code block that has passed through the gate 27 undergoes error detection and correction in the inner code decoding circuit 21, and an error flag is set for a signal that cannot be corrected in the second product code block.

In order to overwrite only the signal without this error flag in the product code block storage circuit 221, the error flag is inverted and inputted to the overwrite permission signal to be overwritten.

This circuit can create a product code block while reducing power consumption and eliminating erroneous data in the second product code block.

FIG. 8 is a block diagram of an error correction circuit according to another embodiment of the present invention, which determines whether to overwrite the signal of the second product code block depending on the degree of error. In this circuit, the signal whose error has been detected and corrected by the inner code decoding circuit 21 for the first product code block l is stored in the product code block storage circuit 22, and the signal for the second product code block is stored in the product code block storage circuit 22. The inner code decoding circuit 21 performs error detection and correction.

At this time, an error flag weighted according to the amount of error contained in the signal is outputted to the second product code block. For example, in a part of the signal where there are no errors,
The error flag outputs 0, 1 when there is one correctable error, and 9 when there is an uncorrectable error. The value of this error flag is judged by the error amount judgment circuit 28, and if it is less than a predetermined value, an overwrite permission signal is issued and the data of the second product code block is overwritten in the product code block storage circuit 22. . By using such a configuration, it is possible to eliminate signals with many errors even if they are correctable, thereby improving the reliability of the output.

FIG. 9 is a block diagram of an error correction 1gl path according to another embodiment of the present invention. This is a method of writing a second product code block signal at a location where the first product code block is incorrect. First, the inner code decoding circuit 21 corrects the first product code block and stores the corrected signal in the 8 result code block storage circuit 22. At the same time, an error flag 8 indicating the position of an uncorrectable error is stored in the code block storage circuit 22. The delay circuit 231c is stored.

Next, error detection is performed on the second product code block.

Correct it and output the error 7 lag weighted accordingly as in the case of Fig. 8.
Only when there is an uncorrectable error in the product code block and the error in the second product code block is less than a predetermined value, an overwrite permission No. 100 is issued from 26 and the second product code block is The signal of product code block storage circuit 2
Overwrite 2.

By doing this, on the second product code block side,
Even if there are many errors, highly reliable output can be obtained.

FIG. 10 is a block diagram of an error correction circuit according to another embodiment of the present invention, in which only when there is an uncorrectable error in the first product code block, only the corresponding signal in the second product code block is corrupted. This method performs inner coding and overwrites only when the number of errors in the second product code block is less than or equal to a certain value.

All data of the first product code block is sent to the inner code decoding circuit 21 through the gate 27, where error detection and correction are performed, and the data is stored in the product code block storage circuit 22.

At this time, an error flag indicating an uncorrectable error is stored in the delay circuit 25. Using this signal, the gate 27 is controlled so that the second product code block data is input to the inner code decoding circuit 21 only when the corresponding signal of the first product code block is an error.

The signal of the second product subblock that has passed through here is subjected to error detection and correction by the inner code decoding circuit 21, and then a weighted error flag is calculated in the same manner as in the case of FIG. This error amount is determined by the error determination circuit 54, and if it is less than a predetermined value, an overwrite permission signal is output to the product code block storage circuit 22 to overwrite the signal of the second product code block. By adopting such a configuration, it is possible to obtain the same effect as the circuit shown in FIG. 9 while reducing power consumption in the inner code decoding circuit 21.

FIG. 11 is a block diagram of an error correction circuit according to another embodiment of the present invention, in which a weighted error flag is also applied to the first product code block. The first product code block undergoes error detection and correction in the inner code decoding circuit 21 and is stored in the inner code decoding circuit 21. At that time, the 8th
As in the case shown in the figure, a weighted error flag is calculated and stored in the delay circuit 231. Next, the inner code decoding circuit 21 performs error detection and correction on the second product code block,
Compute similarly weighted error flags. The comparison circuit 2 compares this second error flag with the first error flag.
9, and only when it is determined that the second product code has fewer errors, an overwrite permission signal is output and the signal of the second product code block in that part is stored in the product code block storage circuit 2.
Overwrite 2. By configuring like this, the first
product code block.

Since a new product code block is created by collecting data that is more reliable than the second product code block, and outer code decoding is performed on the new product code block, highly reliable data can be obtained. From Fig. 3 above, in the circuit explained in Fig. 11, we have explained the case where the same signal is transmitted twice or recorded and reproduced, but the case where the same signal is transmitted three or more times or recorded and reproduced four times is explained. Even more reliable output can be obtained using a similar method.

〔Effect of the invention〕

As described above, in the present invention, the same product code 82
Even when there are many errors in both blocks when transmitting or recording/reproducing more than one time, error correction is possible by collecting correct data and creating a new block.This makes it possible to create an error correction device that is better than before and is a smaller circuit than before. This made it possible to achieve this on a scale of scale.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of signal processing of an error correction device according to an embodiment of the present invention, and FIG. 2 is a schematic diagram of a product code block that is an input signal to the error correction device of the present invention. Figures are block diagrams of error correction devices according to various embodiments of the invention. 1... First product code block 2... Second product code block 5... Product code block 4 input to the outer code decoding circuit...
Output product code block 5.8.11...Signal d, 9.12...Outer code 7.10...Inner code A, B...Block A containing an error in the first product code block ', B'... Second product code block corresponding to A, B Signal man 2 road procedure amendment (voluntary) agP with 11 people who amend the display of the incident

Claims (1)

[Claims] 1. In an apparatus for transmitting or recording/reproducing a product code block by adding outer code parity and inner code parity for error detection and correction to each predetermined amount of a digital information signal, For product code blocks with the same content that are transmitted or recorded two or more times and are received or reproduced multiple times, after decoding the inner code of the first product code block, the second product code block and subsequent product code blocks are The inner code is sequentially decoded,
Only for the inner code blocks that cannot be error corrected among the inner code blocks constituting the first product code block,
After sequentially replacing the corresponding inner code blocks after the second product code block and completing the decoding of all inner codes of multiple product code blocks with the same content, the first product code block for which replacement of the inner code blocks has been completed. An error correction device characterized in that it decodes an outer code of. 2. In a device that adds outer code parity and inner code parity to each predetermined amount of digital information signals for error detection and correction to form product code blocks for transmission or recording/reproduction, two or more of the same product code blocks For product code blocks with the same content that are transmitted or recorded multiple times and received or reproduced multiple times, after decoding the inner code of the first product code block, the inner codes of the second product code block and subsequent ones are sequentially decoded. ,
Among the inner code blocks after the second product code block, only the inner code blocks in which no errors are detected or errors are corrected replace the corresponding inner code blocks of the first product code block, and multiple inner code blocks with the same content are replaced. An error correction device characterized in that after decoding of all inner codes of a product code block is completed, an outer code of a first product code block is decoded. 3. In a device that adds outer code parity and inner code parity to each predetermined amount of digital information signal for error detection and correction to form a product code block for transmission or recording/reproduction, one of the product code blocks is For the product code block of one content that is transmitted or recorded multiple times and received or reproduced multiple times, after decoding the inner code of the first product code block, the inner codes of the second product code block and subsequent ones are sequentially decoded. decrypt,
For inner code blocks that cannot be error corrected among the inner code blocks constituting the first product code block, no error is detected or the error is corrected in the corresponding inner code blocks after the second product code block. , the inner code block is replaced with this inner code block, and the outer code of the first product code block is decoded after the decoding of all the inner codes of the plurality of product code blocks of one content is completed. Characteristic error correction device. 4. In a device that adds outer code parity and inner code parity for error detection and correction to each predetermined amount of a digital information signal to form a product code block for transmission or recording/reproduction, one of the product code blocks is Regarding the product code block of one content transmitted or recorded multiple times and received or reproduced multiple times, after decoding the inner code of the first product code block, each inner code block constituting the first product code block is Among the code blocks, only for the inner code block whose error cannot be corrected, the corresponding inner code blocks after the second product code block are decoded and successively replaced with the inner code blocks,
An error correction device characterized in that an outer code is decoded for a first product code block after completion of replacement. 5. In a device that adds outer code parity and inner code parity for error detection and correction to each predetermined amount of a digital information signal to form a product code block for transmission or recording/reproduction, one of the product code blocks is Regarding the product code block of one content transmitted or recorded multiple times and received or reproduced multiple times, after decoding the inner code of the first product code block, each inner code block constituting the first product code block is Only for the inner code block whose error cannot be corrected among the code blocks, the corresponding inner code blocks after the second product code block are decoded, and as a result, if no error is detected or the error is corrected, this An error correction device characterized in that an inner code block is replaced with an inner code block, and an outer code is decoded for a first product code block after the replacement is completed. 6. Weighting is performed based on the number of code errors detected and corrected when decoding inner code blocks after the second product code block, and error correction is performed among each inner code block constituting the first product code block. A claim for replacing an inner code block only when the weight of the inner code blocks after the second product code block corresponding to the inner code block that has become disabled is less than or equal to a predetermined weight. Section 2
, 3 or 5. The error correction device according to . 7. When decoding each inner code block, weighting is performed based on the number of code errors detected and corrected, and if no errors are detected or errors are corrected in each inner code block constituting the first product code block. Regarding the inner code blocks that have been weighted, if no errors are detected in the corresponding inner code blocks after the second product code block, or if the errors are corrected and the assigned weights are smaller,
Claim 1, wherein the inner code block is replaced with the inner code block.
7. The error correction device according to 2, 3 or 6. 8. Construct a product code block by adding outer code parity and inner code parity for error detection and correction to each predetermined amount of digital information signal, and transmit or record one product code block two or more times each. An error correction device for decoding a reproduced signal includes a storage means for temporarily storing the first product code block after inner code decoding, and an uncorrectable error exists in each inner code block stored in the storage means. and a control means driven by the error indicating means to control signal storage in the storage means, and successively decodes each inner code block after the second product code block. However, if the error indicating means indicates that an uncorrectable error exists in the corresponding inner code block stored in the storage means, the inner code block stored in this storage means is stored in the second inner code block.
The storage means is controlled to replace the product code block with the corresponding inner code block that has been successively decoded after the product code block, and after the decoding of all the inner codes of each product code block of the inner one content is completed, the storage means 1. An error correction device characterized in that an outer code is decoded for a product code block left in the product code block. 9. Construct a product code block by adding outer code parity and inner code parity for error detection and correction to each predetermined amount of digital information signal, and transmit or record/play back the same product code block two or more times. In an error correction device that decodes a signal obtained by decoding an inner code, the error correction device includes a storage means for temporarily storing the first product code block after inner code decoding, and an uncorrectable error correction device for each inner code block after at least the second product code block. and a control means driven by the error detection means to control signal storage in the storage means, and sequentially read each inner code block after the second product code block. During decoding, if the error detection means indicates that there is no uncorrectable error in each inner code block after the second product code block sequentially decoded, the inner code block is stored in the corresponding storage means. Control is performed to replace the stored inner code blocks, and after the decoding of the inner codes of each product code block having the same content is completed, the outer code is decoded for the product code blocks remaining in the storage means. An error correction device characterized by: 10. Construct a product code block by adding outer code parity and inner code parity to each predetermined amount of digital information signal for error detection and correction, and transmit or record and reproduce the same product code block two or more times. In an error correction device that decodes a signal obtained by decoding an inner code, a storage means for temporarily storing a first product code block after inner code decoding, and a storage means for determining whether an uncorrectable error exists in each inner code block stored in the storage means. an error indicating means for indicating whether or not an uncorrectable error exists; an error detecting means for detecting whether or not an uncorrectable error exists for each inner code block after at least the second product code block; the error detecting means and the above error; and control means for controlling signal storage in the storage means driven by the instruction means, and the error indication means is stored in the storage means while successively decoding each inner code block after the second product code block. indicates that an uncorrectable error exists in the corresponding inner code block, and indicates that there is no uncorrectable error in each inner code block subsequent to the second product code block sequentially decoded by the error detection means. In this case, the inner code block is controlled to replace the inner code block stored in the corresponding storage means, and after the decoding of the inner code of each product code block of the inner code is completed, the inner code block is replaced with the inner code block stored in the corresponding storage means. An error correction device characterized in that an outer code is decoded for a product code block left in the error correction device. 11. A product code block is constructed by adding outer code parity and inner code parity for error detection and correction to each predetermined amount of digital information signal, and the same product code block is transmitted or recorded and reproduced two or more times. In an error correction device that decodes a signal generated by an inner code, the error correction device includes a storage means for temporarily storing the first product code block after inner code decoding, and a storage means for determining whether an uncorrectable error exists in each inner code block stored in the storage means. an error indicating means for indicating whether or not the error indicating means is correct; and while referring to the output of the error indicating means, among the inner code blocks after the second product code block, the error indicating means selects a corresponding inner code block stored in the storage means; a decoding means for selectively decoding only the inner code block in which an uncorrectable error has been shown to exist; 2. An error correction device characterized in that the product code block remaining in the storage means is decoded as an outer code after the replacement is completed. 12. Construct a product code block by adding outer code parity and inner code parity for error detection and correction to each predetermined amount of digital information signal, and transmit or record and reproduce the same product code block two or more times. In an error correction device that decodes a signal obtained by decoding an inner code, a storage means for temporarily storing a first product code block after inner code decoding, and a storage means for determining whether an uncorrectable error exists in each inner code block stored in the storage means. an error indicating means for indicating whether or not the error indicating means is correct; and a corresponding inner code block in which the error indicating means is stored in the storage means among each inner code block after the second product code block while referring to the output of the error indicating means; a decoding means for selectively decoding only the inner code block in which it is shown that an uncorrectable error exists in the inner code block; and a control means driven by at least the error detection means to control the storage of the signal in the storage means, and the error detection means detects whether or not the above error exists as a result of selective decoding by the decoding means. Each inner code block in which an uncorrectable error has not been detected by the detection means is used to replace the corresponding inner code block in the storage means, and after the replacement is completed, the outer code is stored in the product code block remaining in the storage means. An error correction device characterized in that the error correction device performs decoding. 15. The error detection means for detecting whether uncorrectable errors exist in each of the inner code blocks after the second product code block includes weighting that counts the number of errors corrected in each inner code block. and a comparison means for comparing the counted value by the weighting means with a predetermined value, so that the corresponding inner code block is not replaced when the weighted counted value is greater than or equal to the predetermined value. 13. The error correction device according to claim 9, 10 or 12. 14. Weighting means for counting and adding the number of errors detected and corrected when decoding each inner code block to a decoder that decodes the inner code, and correspondence between the plurality of product code blocks added by the weighting means. a comparison means for comparing the count values of the inner code blocks that constitute the first product code block, and compares the weighted count values of each inner code block constituting the first product code block with the corresponding inner code blocks subsequent to the second product code block. 14. The error correction apparatus according to claim 8, 9, 10, or 13, wherein the control means is operated to replace the code block with an inner code block when the weighting count value added to the code block is small.