JPH0344214A - Circuit for preventing indefinite phase at momentary interrupt of input reference signal in phase synchronizing oscillation circuit - Google Patents
Circuit for preventing indefinite phase at momentary interrupt of input reference signal in phase synchronizing oscillation circuitInfo
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- JPH0344214A JPH0344214A JP1179711A JP17971189A JPH0344214A JP H0344214 A JPH0344214 A JP H0344214A JP 1179711 A JP1179711 A JP 1179711A JP 17971189 A JP17971189 A JP 17971189A JP H0344214 A JPH0344214 A JP H0344214A
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- input
- reference signal
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Abstract
Description
【発明の詳細な説明】
〔概 要〕
伝送路を介して送られる入力基準信号に自局の基準信号
を同期させる際に使用する位相同期発振回路における入
力基準信号の瞬断時位相不定防止回路に関し、
伝送路において、入力基準信号の瞬断が起きた場合にも
、位相同期発振回路の出力の位相が瞬断前の位相から大
きくずれないようにすることを目的とし、
基準入力信号の周波数を所望の周波数に変換する入力分
周回路と、前記基準六方信号の瞬断あるいは復旧により
回路を切り換える選択回路と、前記入力分周回路から出
力する基準信号が前記選択回路を介して人力し、この基
準信号周波数に同期して基準信号を発生する位相同期発
振回路と、当該位相同期発振回路の閉ループ回路の出力
を反転してその出力信号を選択回路に人力する反転回路
と、前記基準入力信号の瞬断あるいは復旧を検出して、
前記入力分周回路のリセットおよび前記選択回路の切り
換えを制御する入力瞬断・復旧検出制御回路とから構成
する。[Detailed Description of the Invention] [Summary] A circuit for preventing phase instability during instantaneous interruption of an input reference signal in a phase synchronized oscillator circuit used to synchronize the reference signal of its own station with the input reference signal sent via a transmission line. Regarding the frequency of the reference input signal, the purpose is to prevent the phase of the output of the phase synchronized oscillator circuit from significantly deviating from the phase before the momentary interruption even if a momentary interruption of the input reference signal occurs in the transmission path. an input frequency divider circuit that converts the reference hexagonal signal into a desired frequency; a selection circuit that switches the circuit upon momentary interruption or restoration of the reference hexagonal signal; and a reference signal output from the input frequency divider circuit that is manually inputted via the selection circuit; a phase-locked oscillation circuit that generates a reference signal in synchronization with the reference signal frequency; an inversion circuit that inverts the output of the closed-loop circuit of the phase-locked oscillation circuit and inputs the output signal to the selection circuit; and the reference input signal. Detects instantaneous interruption or restoration of
and an input instantaneous interruption/recovery detection control circuit that controls the reset of the input frequency divider circuit and the switching of the selection circuit.
本発明は、伝送路を介して送られる入力基準信号に自局
の基準信号を同期させる際に使用する位相同期発振回路
における入力基準信号の瞬断時位相不定防止回路に関す
る。The present invention relates to a circuit for preventing phase instability during instantaneous interruption of an input reference signal in a phase synchronized oscillator circuit used to synchronize a reference signal of its own station with an input reference signal sent via a transmission path.
第3図を参照しつつ従来例における位相同期発振回路を
説明する。A conventional phase synchronized oscillation circuit will be explained with reference to FIG.
図において、11は、自局内の基準信号を同期させるた
めに、マスク局から伝送路を介して送られてきた入力基
準信号INを分周する入力分周回路である。そして、位
相比較回路13、低域フィルタ14、電圧制御発振器1
5および分周回路16で位相同期発振回路(PLO)1
7を構成している。In the figure, reference numeral 11 denotes an input frequency dividing circuit that divides the frequency of the input reference signal IN sent from the mask station via the transmission line in order to synchronize the reference signal within the own station. Then, a phase comparison circuit 13, a low-pass filter 14, a voltage controlled oscillator 1
5 and the frequency divider circuit 16 to form a phase-locked oscillator (PLO) 1.
7.
したがって、マスク局から伝送路を介して送られてきた
人力基準信号IN、たとえば、6J12MHzあるいは
1.544Hzの信号は、入力分周回路11により1.
/789あるいは1 /193に分周されて8KHzに
変換される。この8KHzの基準信号は、電圧制御発振
器15の出力を分周回路16で分周した半周期前の信号
と位相比較回路13で比較される。Therefore, the human reference signal IN, for example, a 6J12MHz or 1.544Hz signal, sent from the mask station via the transmission line is converted to 1.
The frequency is divided by /789 or 1/193 and converted to 8KHz. This 8 KHz reference signal is compared in the phase comparison circuit 13 with a signal obtained by dividing the output of the voltage controlled oscillator 15 by a frequency dividing circuit 16 and half a period earlier.
位相比較回路13で比較された前記各信号の位相差は、
低域フィルタ14により電圧レベルに変換される。そし
て、この電圧レベルにより電圧制御発振器15の発振周
波数を制御して、マスク局から送られてくる入力基準信
号INに同期した自局内の基準信号を生成する。The phase difference between the signals compared by the phase comparison circuit 13 is:
It is converted to a voltage level by a low pass filter 14. Then, the oscillation frequency of the voltage controlled oscillator 15 is controlled by this voltage level to generate a reference signal within the local station that is synchronized with the input reference signal IN sent from the mask station.
このようにして、位相同期発振回路17は、常にマスク
局の人力基準信号INに同期した自局内の基準信号を発
生することができる。In this manner, the phase synchronized oscillation circuit 17 can always generate a reference signal within its own station that is synchronized with the human-powered reference signal IN of the mask station.
しかし、伝送路において、何等かの擾乱があった場合、
人力基準信号は瞬断することがある。このような場合、
位相同期発振回路は自走するため、時間の経過につれて
、だんだんとマスク局の入力基準信号INと同期がずれ
たものとなる。However, if there is some kind of disturbance in the transmission path,
The human reference signal may be momentarily interrupted. In such a case,
Since the phase-locked oscillator circuit runs free, it gradually becomes out of synchronization with the input reference signal IN of the mask station as time passes.
本発明は、伝送路において、人力基準信号の瞬断が起き
た場合にも、位相同期発振回路の出力の位相が瞬断前の
位相から大きくずれないようにすることを目的とする。An object of the present invention is to prevent the phase of the output of a phase synchronized oscillation circuit from significantly shifting from the phase before the instantaneous interruption even when a momentary interruption of a human input reference signal occurs in a transmission path.
第1図は本発明における原理ブロック構成図である。 FIG. 1 is a block diagram of the principle of the present invention.
第1図において、入力分周回路lは、伝送路を介して入
力される入力基準信号INの周波数を所望の周波数に変
換する。選択回路2は、前記入力基準信号が瞬断あるい
は復旧した場合に回路を切り換える。前記入力分周回路
1から出力する信号が、前記選択回路2を介して位相同
期発振回路3に入力し、位相同期発振回路3は、入力基
準信号INに位相同期した基準信号を発生する。反転回
路4は、前記位相同期発振回路3の出力を反転してその
出力信号を選択回路2に入力する。In FIG. 1, an input frequency divider circuit 1 converts the frequency of an input reference signal IN input via a transmission line to a desired frequency. The selection circuit 2 switches the circuit when the input reference signal is momentarily interrupted or restored. The signal output from the input frequency divider circuit 1 is input to the phase synchronized oscillation circuit 3 via the selection circuit 2, and the phase synchronized oscillation circuit 3 generates a reference signal phase-synchronized with the input reference signal IN. The inversion circuit 4 inverts the output of the phase synchronized oscillation circuit 3 and inputs the output signal to the selection circuit 2.
入力瞬断・復旧検出制御回路5は、前記入力基準信号の
瞬断あるいは復旧を検出して、前記入力分周回路1をリ
セットするリセット回路6および前記入力分周回路1の
出力信号と反転回路4の出力信号とを切り換える前記選
択回路2とを制御する。The input instantaneous interruption/recovery detection control circuit 5 includes a reset circuit 6 that detects an instantaneous interruption or restoration of the input reference signal and resets the input frequency dividing circuit 1, and an output signal of the input frequency dividing circuit 1 and an inverting circuit. 4 and the selection circuit 2 which switches between the four output signals.
本発明の作用を第1図の原理ブロック構成図を参照しつ
つ説明する。The operation of the present invention will be explained with reference to the principle block diagram shown in FIG.
マスク局から伝送された入力基準信号は、入力分周回路
1で8KHzに分周され、伝送路における入力基準信号
に瞬断がない場合には、入力瞬断・復旧検出制御回路5
からの出力は、選択回路2を通常の位置にする。このた
め、分周された8KHzの基準信号は、選択回路2をそ
のまま通って位相同期発振回路3に入力する。この位相
同期発振回路3は、マスク局の人力基準信号INに位相
同期のとれた自局内の基準信号を発生する。The input reference signal transmitted from the mask station is frequency-divided to 8KHz by the input frequency divider circuit 1, and when there is no momentary interruption in the input reference signal on the transmission path, the input reference signal is divided by the input frequency division circuit 1.
The output from puts the selection circuit 2 in its normal position. Therefore, the frequency-divided 8 KHz reference signal passes through the selection circuit 2 as it is and is input to the phase synchronized oscillation circuit 3. This phase synchronized oscillation circuit 3 generates a reference signal within its own station that is phase synchronized with the human reference signal IN of the mask station.
伝送路における擾乱で入力基準信号が瞬断した場合には
、これを入力瞬断・復旧検出制御回路5で検出して、選
択回路2が反転回路4からの出力を選択するようにする
と同時に、リセット回路6により入力分周回路1のカウ
ンタを復旧に備えてリセットする。When the input reference signal is momentarily interrupted due to a disturbance in the transmission path, this is detected by the input momentary interruption/recovery detection control circuit 5, and the selection circuit 2 selects the output from the inverting circuit 4. The reset circuit 6 resets the counter of the input frequency divider circuit 1 in preparation for recovery.
位相同期発振回路3から取り出した信号は反転回路4で
反転され、その出力信号が選択回路2を介して位相同期
発振回路3に与えられ、−時的に、マスク局の入力基準
信号INの役割を果たす。このために、位相同期発振回
路3が自走することとなっても、反転回路4からの信号
が存在するために、位相ずれが生じるまでに比較的長い
時間を要することとなる。The signal taken out from the phase-locked oscillator circuit 3 is inverted by an inverter 4, and the output signal is given to the phase-locked oscillator circuit 3 via the selection circuit 2, and -temporally serves as the input reference signal IN of the mask station. fulfill. For this reason, even if the phase synchronized oscillation circuit 3 is allowed to run freely, it will take a relatively long time until a phase shift occurs because of the presence of the signal from the inversion circuit 4.
伝送路における擾乱が無くなり、復旧した場合には、入
力瞬断・復旧検出制御回路5がこれを検出して、選択回
路2を元の通常状態に戻す。When the disturbance in the transmission path disappears and the transmission path is restored, the instantaneous input interruption/recovery detection control circuit 5 detects this and returns the selection circuit 2 to its original normal state.
以上のように、入力基準信号が瞬断した場合、位相同期
発振回路3は、−時的に反転回路4の出力を入力基準信
号INとみなして動作することとなる。As described above, when the input reference signal is momentarily interrupted, the phase synchronized oscillation circuit 3 operates by temporarily regarding the output of the inversion circuit 4 as the input reference signal IN.
第2図は本発明における位相同期発振回路における入力
基準信号の瞬断時位相不定防止回路の一実施例を示す。FIG. 2 shows an embodiment of a circuit for preventing phase instability at the time of instantaneous interruption of an input reference signal in a phase synchronized oscillation circuit according to the present invention.
第2図において、符号11.13ないし17は第3図に
おけるものと対応するので、その説明は省略する。In FIG. 2, numerals 11, 13 to 17 correspond to those in FIG. 3, so their explanation will be omitted.
選択回路12は、伝送路において入力基準信号の瞬断が
有った場合と復旧した場合とにより回路を切り換える。The selection circuit 12 switches the circuit depending on whether there is a momentary interruption of the input reference signal in the transmission line or when the input reference signal is restored.
反転回路18は、位相同期発振回路17の閉ループ信号
を180°反転するもので、反転した出力信号は、選択
回路12に入力する。The inversion circuit 18 inverts the closed loop signal of the phase synchronized oscillation circuit 17 by 180°, and the inverted output signal is input to the selection circuit 12.
微分回路19は、反転回路18の出力信号の立ち上がり
を検出して、その立ち上がりを微分し、このパルスをA
ND回路20に出力する。入力瞬断・復旧検出制御回路
21は、伝送路における入力基準信号の瞬断あるいは復
旧を検出し、入力基準信号の瞬断時反転回路18の出力
が位相同期発振回路17に入力するように選択回路12
を選択する。その後、伝送路が復旧した場合には、これ
を検出して選択回路12を元の位置に切り換える。The differentiating circuit 19 detects the rising edge of the output signal of the inverting circuit 18, differentiates the rising edge, and converts this pulse into A.
Output to the ND circuit 20. The input instantaneous interruption/recovery detection control circuit 21 detects an instantaneous interruption or restoration of the input reference signal in the transmission path, and selects the output of the inversion circuit 18 at momentary interruption of the input reference signal to be input to the phase synchronized oscillation circuit 17. circuit 12
Select. Thereafter, when the transmission path is restored, this is detected and the selection circuit 12 is switched to its original position.
また、入力基準信号の瞬断時、これを検出してAND回
路20に入力する。前記微分回路19の出力と共に、A
ND回路20から出力が入力分周回路11に入力し、入
力分周回路11のカウンタをリセットする。Furthermore, when the input reference signal is momentarily interrupted, this is detected and input to the AND circuit 20. Along with the output of the differentiating circuit 19, A
The output from the ND circuit 20 is input to the input frequency divider circuit 11, and the counter of the input frequency divider circuit 11 is reset.
以下、動作を説明する。The operation will be explained below.
マスク局から伝送された入力基準信号は、入力分周回路
11で8KHzに分周され、選択回路12に入力する。The input reference signal transmitted from the mask station is frequency-divided to 8 KHz by the input frequency divider circuit 11 and input to the selection circuit 12.
伝送路における入力基準信号INに瞬断がない場合には
、入力瞬断・復旧検出制御回路21により選択回路12
を通常の位置に制御する。このため、人力分周回路11
で分周された8KHzの基準信号は、選択回路12をそ
のまま通って位相同期発振回路17に入力する。この位
相同期発振回路17は周知のもので、電圧制御発振器1
5で発振する信号を分周回路16で分周して、この分周
信号と前記マスク局で発生した入力基準信号とを位相比
較回路13で比較する。前記両信号の位相差は、低域フ
ィルタ14で電圧レベルに変換され、この電圧レベルに
基づいて前記電圧制御発振器15の発振周波数をマスク
局の入力基準信号の周波数に引き込むように、同期をと
って自局白基準信号を発生する。When there is no instantaneous interruption in the input reference signal IN on the transmission path, the selection circuit 12 is activated by the input instantaneous interruption/recovery detection control circuit 21.
to its normal position. For this reason, the manual frequency dividing circuit 11
The 8 KHz reference signal frequency-divided by 2 passes through the selection circuit 12 as it is and is input to the phase synchronized oscillation circuit 17. This phase-locked oscillator circuit 17 is well-known, and the voltage-controlled oscillator 1
A frequency dividing circuit 16 divides the frequency of the signal oscillated at 5, and a phase comparison circuit 13 compares this frequency-divided signal with the input reference signal generated at the mask station. The phase difference between the two signals is converted into a voltage level by a low-pass filter 14, and based on this voltage level, the oscillation frequency of the voltage controlled oscillator 15 is synchronized so as to be drawn into the frequency of the input reference signal of the mask station. to generate the own station white reference signal.
伝送路における擾乱で入力基準信号が瞬断した場合には
、これを入力瞬断・復旧検出制御回路21が検出して、
選択回路12が反転回路18の出力を選択するように制
御し、同時に、入力分周回路11からの回路は切り離さ
れる。したがって、−時的に、位相同期発振回路17の
閉ループを形成する回路の出力を反転した信号が、恰も
入力基準信号INのごとく位相比較回路13に入力され
て分周回路16の出力と比較される。また、この時、反
転回路18の出力信号の立ち上がり変化点は、微分回路
19により微分されてAND回路20に入力する。When the input reference signal is momentarily interrupted due to disturbance in the transmission path, the input momentary interruption/recovery detection control circuit 21 detects this and
The selection circuit 12 controls to select the output of the inversion circuit 18, and at the same time, the circuit from the input frequency divider circuit 11 is disconnected. Therefore, a signal obtained by inverting the output of the circuit forming the closed loop of the phase-locked oscillator circuit 17 is input to the phase comparator circuit 13 just like the input reference signal IN and is compared with the output of the frequency divider circuit 16. Ru. Further, at this time, the rising edge change point of the output signal of the inverting circuit 18 is differentiated by the differentiating circuit 19 and input to the AND circuit 20 .
一方、人力基準信号に復旧すると、入力瞬断・復旧検出
制御回路21は、これを検出してAND回路20に出力
する。AND回路20は、入力基準信号の復旧を検出し
た信号と前記微分回路19の出力信号との入力により、
入力分周回路11の図示されていないカウンタを入力基
準信号の復旧に備えてリセットする。そして、あわせて
入力瞬断・復旧検出制御回路21は選択回路12を元の
通常状態に戻す。On the other hand, when the human input reference signal is restored, the input instantaneous interruption/recovery detection control circuit 21 detects this and outputs it to the AND circuit 20. The AND circuit 20 receives the signal detecting the restoration of the input reference signal and the output signal of the differentiating circuit 19,
A counter (not shown) of the input frequency divider circuit 11 is reset in preparation for recovery of the input reference signal. At the same time, the input instantaneous interruption/recovery detection control circuit 21 returns the selection circuit 12 to its original normal state.
本発明によれば、伝送路における入力基準信号の瞬断時
に、位相同期発振回路の閉ループ回路からの信号で一時
的に入力基準信号の代わりが果たせる。According to the present invention, when the input reference signal in the transmission line is momentarily interrupted, the signal from the closed loop circuit of the phase synchronized oscillation circuit can temporarily replace the input reference signal.
したがって、伝送路における入力基準信号が断となって
自局内の基準信号の位相が早−期にずれてしまうことが
ない。Therefore, there is no possibility that the input reference signal on the transmission line is disconnected and the phase of the reference signal within the own station shifts early.
第1図は本発明における原理ブロック構成図、第2図は
本発明における一実施例説明図、第3図は従来例説明図
である。
1・・・入力分周回路
2・・・選択回路
3・・・位相同期発振回路
4・・・反転回路
5・・・入力瞬断・復旧検出制御回路
6・・・リセット回路FIG. 1 is a basic block diagram of the present invention, FIG. 2 is an explanatory diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of a conventional example. 1... Input frequency divider circuit 2... Selection circuit 3... Phase synchronized oscillation circuit 4... Inversion circuit 5... Input instantaneous interruption/recovery detection control circuit 6... Reset circuit
Claims (1)
て、入力基準信号の位相に引き込む位相同期発振回路に
おいて、 基準入力信号の周波数を所望の周波数に変換する入力分
周回路1と、 前記基準入力信号の瞬断あるいは復旧により回路を切り
換える選択回路2と、 前記入力分周回路1から出力する基準信号が前記選択回
路2を介して入力し、この基準信号周波数に同期して基
準信号を発生する位相同期発振回路3と、 当該位相同期発振回路3の出力を反転した出力信号を前
記選択回路2に入力する反転回路4と、前記基準入力信
号の瞬断あるいは復旧を検出して、前記入力分周回路1
のリセットおよび前記選択回路2の切り換えを制御する
入力瞬断・復旧検出制御回路5と、 を備えたことを特徴とする位相同期発振回路における入
力基準信号の瞬断時位相不定防止回路。[Claims] In a phase-locked oscillator circuit that compares the phases of a reference signal and an output signal of a voltage-controlled oscillator and draws them into the phase of the input reference signal, an input component that converts the frequency of the reference input signal to a desired frequency is provided. a frequency circuit 1; a selection circuit 2 that switches the circuit upon momentary interruption or recovery of the reference input signal; and a reference signal output from the input frequency divider circuit 1 is inputted via the selection circuit 2, and the frequency of the reference signal is A phase-locked oscillation circuit 3 that synchronously generates a reference signal, an inversion circuit 4 that inputs an output signal obtained by inverting the output of the phase-locked oscillation circuit 3 to the selection circuit 2, and a momentary interruption or restoration of the reference input signal. is detected, and the input frequency dividing circuit 1
A circuit for preventing phase instability of an input reference signal at momentary interruption in a phase synchronized oscillator circuit, comprising: an input instantaneous interruption/recovery detection control circuit 5 for controlling reset of the input signal and switching of the selection circuit 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1179711A JPH0344214A (en) | 1989-07-12 | 1989-07-12 | Circuit for preventing indefinite phase at momentary interrupt of input reference signal in phase synchronizing oscillation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1179711A JPH0344214A (en) | 1989-07-12 | 1989-07-12 | Circuit for preventing indefinite phase at momentary interrupt of input reference signal in phase synchronizing oscillation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0344214A true JPH0344214A (en) | 1991-02-26 |
Family
ID=16070540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1179711A Pending JPH0344214A (en) | 1989-07-12 | 1989-07-12 | Circuit for preventing indefinite phase at momentary interrupt of input reference signal in phase synchronizing oscillation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0344214A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04365223A (en) * | 1991-06-13 | 1992-12-17 | Nec Corp | Phase locked loop circuit |
| JPH0530095A (en) * | 1991-07-24 | 1993-02-05 | Nec Eng Ltd | Phase lock oscillating circuit |
-
1989
- 1989-07-12 JP JP1179711A patent/JPH0344214A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04365223A (en) * | 1991-06-13 | 1992-12-17 | Nec Corp | Phase locked loop circuit |
| JPH0530095A (en) * | 1991-07-24 | 1993-02-05 | Nec Eng Ltd | Phase lock oscillating circuit |
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