JPH0344247A - Full digital carrier recovery circuit - Google Patents

Abstract

PURPOSE:To make the circuit small, to avoid the adjustment due to the dispersion in the characteristic and the temperature characteristic of an analog element and to attain no adjustment for the circuit by constituting the carrier recovery circuit with digital circuits only. CONSTITUTION:A carrier generator 37 storing a carrier waveform is read to obtain a recovered carrier. Then a digital phase control signal in response to a phase difference between a received signal carrier and a recovered carrier is generated by a phase control signal generating circuit 31, its phase control signal is integrated by a digital integration device 32 and a digital error signal is outputted, and phase information in response to the error signal is outputted from a phase information generating circuit 33. On the other hand, a reference clock is counted by an address counter 35 and the count and the phase information are calculated by an address conversion circuit 36 and the generated phase of the readout address is revised by the result of calculation. Thus, the control circuit is made simple and no adjustment is required.

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention is applicable to digitally modulated signals, especially amplitude and phase variable signals! The present invention relates to a carrier regeneration circuit that obtains a regenerated carrier wave used for synchronously detecting an Ii (QAM) signal or a phase modulated signal.

``Prior Art'' FIG. 8 shows a duplication device using a conventional carrier wave regeneration circuit.
6QAM) received signal is supplied to a synchronous detection circuit 12.13, a regenerated carrier wave from a voltage controlled oscillator (VCO) 14 is supplied to a synchronous detection circuit 12, and this regenerated carrier wave is transmitted through a π/2 phase shifter 15. The signal is supplied to the synchronous detection circuit 13. Each synchronous detection output of the synchronous detection circuit 12.13 is supplied to an AD converter 18.19 through a low-pass filter 16.17. The estimated value al of the first path signal in the in-phase channel obtained as the most significant bit of the output of the AD converter 18 and the amplitude and phase error information t in the orthogonal channel obtained as the least significant bit of the output of the AD converter 19 b5 is multiplied by the multiplier 21, and AD
Amplitude and phase error information a5 in the in-phase channel obtained as the least significant bit of the output of the converter 18, and AD
The estimated value b1 of the first path signal in the orthogonal channel obtained as the most significant bit of the output of the converter 19 is multiplied by the multiplier 22, and both multiplication results of the multipliers 21 and 22 are subtracted from each other by the subtracter 23. The result of the subtraction is integrated by an analog integrator 24, and the integrated output has a low-pass wave integrator 25.
The high frequency components are removed and the signal is supplied to the voltage controlled oscillator 14 as an analog control signal. As a result, the recovered carrier wave from voltage controlled oscillator 14 is synchronized with the received signal carrier wave.

"Problems to be Solved by the Invention" As described above, in the past, voltage controlled oscillators were controlled using analog signals. In addition, for carrier wave regeneration of a modulation method that requires highly accurate phase control such as 256QAM, the required characteristics are a phase error of ±0.6° or less, and a voltage-controlled oscillator frequency stability of ±lXl0-" or less. For this reason, the control circuit becomes complex in order to satisfy the required characteristics while also considering external conditions, resulting in poor adjustment.Furthermore, when changing design specifications such as frequency, it is necessary to change the entire circuit. It was necessary and uneconomical.

"Means for Solving the Problem" According to the present invention, a reproduced carrier wave is obtained by reading out a carrier wave generator that stores a carrier waveform.

The phase of the reproduced carrier wave is controlled by changing the phase of the read address, that is, the generation phase of the read address is controlled in accordance with the phase difference between the received signal carrier wave and the reproduced carrier wave. This control is performed with a digital configuration, so a digital phase control signal corresponding to the phase difference between the received signal carrier wave and the reproduced carrier wave is generated by a phase control signal generation circuit.
The phase control signal is integrated by a digital integrator to output a digital error signal, and phase information corresponding to the error signal is output from the phase information generation circuit.

The reference clock is counted by an address counter, the counted value and the phase information are calculated by an address conversion circuit, and the calculation result is supplied to a carrier wave generator as a read address. Alternatively, the phase information is preset in an address counter that counts the reference clock, and the count value of the address counter is supplied to the carrier wave generator as a read address.

"Embodiment" FIG. 1 shows an embodiment of the present invention, and parts corresponding to those in FIG. 8 are given the same reference numerals. The output of the AD converter discriminator 18 and the output of the AD converter discriminator 19 are input, and the phase control signal generation circuit 31 generates a digital phase control signal according to the phase difference between the received signal carrier wave and the reproduced carrier wave. The generated 0 phase control signal generation circuit 31 is controlled by the multipliers 21 and 22 and the subtracter 23 in FIG. A digital phase control signal is obtained.

Phase system? The phase control signal from the ill signal generation circuit 31 is integrated by a digital integrator 32, and a digital error signal is output. The digital integrator 32 is, for example, an up/down counter, and counts up the phase control signal of 1, counts down the phase control signal of 0, outputs the carry pulse as the error signal, and outputs the carry pulse as the error signal. Output as -θ.

The error signal of the integrator 32 is supplied to a phase information generation circuit 33, and digital phase information corresponding to the error signal is generated. On the other hand, the reference clock at the terminal 34 is counted by the address counter 35, the counted value is output as an address, and the address of the address counter 35 is converted by the address conversion circuit 36 according to the phase information from the phase information generation circuit 33. The output of the address conversion circuit 36 is supplied as an address to the carrier wave generator 37, the stored carrier waveform is read out according to the address, and the read output is supplied as a reproduced carrier wave to the synchronous detection circuit. .

With this configuration, the generation phase of the address supplied to the carrier wave generator 37 is controlled according to the phase difference between the received signal carrier wave and the regenerated carrier wave obtained from the phase control signal generation circuit 31, and the phase of the regenerated carrier wave changes according to the phase difference. change in the direction of eliminating it.

FIG. 2 shows a specific example of FIG. 1. The m-transmission generator 37 includes waveform ROMs 38a and 38b and DA converters 39a and 39b that convert the read outputs of these ROMs into analog signals. Waveform ROM38a.

38b stores amplitude information of each point of the waveform for one cycle of the carrier wave, as shown in FIG. 3, for example. In this example, when the number of bits n of each address of the waveform ROMs 38a and 38b is 5, one cycle has 2'-32 addresses, and one cycle of the sine waveform is stored as amplitude information of 32 points. The phase of the carrier wave differs depending on which address the reading starts from, and in this case, the carrier wave can be generated with a phase accuracy of 360°/32.

An address counter 35a as the address counter 35,
35b are provided, and the address counter 35a is O.
When returning to , the value in the register 41 is preset in the address counter 35b, so that the address generated by the address counter 35b advances by 90 degrees with respect to the address generated by the address counter 35a. In other words, each address of the address counters 35a, 35b is converted according to the phase information by the address conversion circuit 36, and then the waveform R
OM38a, 38b are supplied for reading respectively. If the frequency of the reference clock at the terminal 34 is, for example, 8 times the carrier wave frequency f, the carrier wave will be generated with 1 cycle FJ]8 sample data, and the address counter 35
Octal counters are used as a and 35b, and 2 bits are added to the lower side of each 3-bit address by an address conversion circuit 36, resulting in a total of 5 bits of address to be stored in the waveform ROM 3.
8a and 38b, put 2 in the register 41, set the initial value of the address counter 35b to 2, advance the address of the address counter 35b by 2 with respect to the address of the address counter 35a, and read out the address of each of these 3-bit addresses. Since the address conversion circuit 36 adds 2 bits to the lower order of each address to make a 5-bit address, the address given to the waveform ROM 38b is
The address given to a is advanced by 8, and
The reproduced carrier wave output from the DA converter 39b has a phase lead of 90° with respect to the reproduced carrier wave output from the DA converter 39a.

The phase information generation circuit 33 is a binary counter (in this example, n
-5), the error signal θ from the integrator 32 is counted up, and the error signal -θ is counted down. The address conversion circuit 36 is an n-bit adder 36a, 36
The n-bit adders 36a and 36b each input the MSB (most significant bit) of the 5-bit phase information from the 2'=32 binary counter 33 and the 3-bit address from the address counters 35a and 35b. Align and add these addition results to 5 from the LSB (least significant bit) side.
The bits are respectively addresses for the waveform ROMs 38a and 38b.

When there is no output from the integrator 32 and the output from the 27-decimal counter 33 is -(00000), the waveform ROM addresses corresponding to the outputs from the octal address counters 35a and 35b are as follows.

Address counter ROM address 35a 35b 38a 38b (
000), (010)→(00000)-0, (0
1000) -8(001), (011)→(00
100)-4, (01100) =12(010),
(too)→(01000)=8, (10000
) -16(011), (101)→(01100
)-12, (10100) =20(too), (
110)→(10000)=16. (11000)
=24(101), (111)→(10100)=
20. (11100) =28(110) , (0
00) → (11000) -24, (00000) -0
(111), (001)→(11100)-28,
(00100)=4 carrier waves are reproduced by sequentially and repeatedly reading out the above addresses. In this state, when +θ output is obtained from the integrator 32, the 21-base counter 33 counts up and the 2''-base counter 33 outputs -
(00001), and the octal address counter 35a,
The waveform ROM address corresponding to the output from 35b is as follows.

Address counter ROM address 35a 35b 38a 38b
(000), (010)→(00001)=1,
(01001) -9(001) , (011)
→ (00101)-5, (01101)-13
(010), (100) → (01001)=
9, (10001) -17(011),
(101) → (01101)=13. (10
101) =21(100), (110) →
(10001)-17, (11001)-25(
101) , (111) → (10101)-2
1, (11101) =29(110) , (00
0) → (11001)=25. (00001
) −1(111) , (001) → (11
101)=29. (00101) =5 and 2
' If the -θ output is obtained from the integrator 32 in the state of -(00000), the output of the binary counter 33 is -(00000).
The output of the 2M base counter 33 is (
11111), and the octal address counters 35a, 3
The waveform ROM address corresponding to the output from 5b is as follows.

Address counter ROM address 35a 35b 38a 38b (
000), (010)→(11111)=31.
(00111) =7(001), (011)→
(00011)-3, (01011)-11(01
0), (100)→(00111)-7, (011
11) =15(011), (101)→(01
011) μm1. (10011) =19(100)
, (110)→(01111)=15. (101
11) =23(101), (111) → (1
0011)-19, (10111)-27(110),
(000) → (10111)-23, (1111
1)-31(111), (001) → (1101
1)-27, (00011)-3 examples) 000
001 111+11111 +111
An example of 11+11111 or more is shown in FIG. 4. However, this is an example where one period is tIed with 16 addresses. The number of addresses may be selected as appropriate depending on the required accuracy of the output phase.

Output the 1181st period of the carrier wave as 8 sample data, n=
The relationship between the output (phase information) of the 2"-32 binary counter 33 and the read address for the waveform ROM 38a in the case of 5 is shown in FIG. 5. When the output of the 2"-32 binary counter 33 is ooooo, the reproduced carrier wave obtained On the other hand, when the output of the 2a-adic counter 33 is 00001, the phase of the obtained reproduced carrier wave is delayed by 360°/32. Similarly below,
Each time the output of the 2a-adic counter 33 increases by l, the phase of the recovered carrier wave obtained is sequentially delayed by 360''/32.

In Fig. 2, the binary counter (phase information generation circuit) 3
Address counter 35a according to the output (phase information) of 3.
, 35b are shifted, and the DA converter 39a
The phase of the reproduced carrier wave obtained by this is controlled in a direction to match the phase of the received signal carrier wave.

FIG. 6 shows another embodiment of the invention, in which parts corresponding to those in FIG. 1 are given the same reference numerals. In this example, the phase information from the phase information generation circuit 33 is sent to the address counter 3.
5, and the carrier wave generator 37 is read out using the output of the address counter 35 as an address. The address counter 35 is preset every cycle of the carrier wave.

A concrete example of this is shown in FIG. In this example, 2' 1-ary counters 33a, 33b are provided as the phase information generation circuit 33, and these 211-ary counters 33a, 33b are connected to the integrator 3.
The +θ error signal of 2 is counted up, and the -0 error signal is counted down. In order to shift the phase of the regenerated carrier waves of the DA converters 39a and 39b by 90', the contents of the register 42 are preset in the 211-decimal counter 33b.

n-5, when one period of carrier wave is 8 sample data,
8 is stored in the register 42 2 N-ary counter 3
Each output (phase information) of 3a and 533b is preset to n-bit address counters 35a and 35b, respectively. When the number of sample data in one period of carrier wave is m, m
A decimal (in this example, daily decimal) counter 43 is provided, and this counter 43 counts the reference clock at the terminal 34, and the carry output of the counter 43 (output when the counted value returns to 0) causes the address counters 35a and 35b to be activated. Each is preset. Each of the address counters 35a and 35b has n bits, but the reference clock is manually entered at the 3rd bit (2''=n) from the most significant bit, in this example, the 3rd bit.Address counter 35a.

The output of each 3 bits of 35b is sent to the waveform ROM 38a.

38b as a read address.

There is no output from the integrator 32, and the 211 base counter 33a
When the output is -(00000), the initial values given to the address counters 35a and 35b are as follows.

(2) Output = (00000), Q output - (01000) The carrier wave is the reference clock and the address counter 35a.

35b is counted from this initial value, and the ROM 38a is counted.

38b by giving the following address.

Address counter output 35a 35b ↓ (00000)=O, (01000)=8↓ (0
0100)=4. (01100)-12↓ (01
000) Fable 8. (10000)=16↓ (011
00)-12, (10100)-20↓ (10000
)−16, (11000)=24↓ (10100)=
20. (11100)-28↓ (11000) Fable 24. (00000) = 0 bift bit
Bit Bit In this state, +θ from the integrator 32
When the output is obtained, the initial values given to the address counters 35a and 35b are as follows: ■Output - (00001), Q output = (01001) The carrier wave is counted from this initial value using the reference clock, and the RO
Reproduction is performed by giving the following addresses to M38a and 38b.

Address counter output 35a 35b ↓ (00001)=1. (01001)-9↓
(00101)-5, (01101)-13↓ (01
001)-9, (10001)=17↓ (01101
)=13. (10101)-21↓ (10001
)=17. (11001)-25↓ (10101
)-21, (11101)-29↓ (11001)=
25. (00001)-1↓ (11101)=2
9. (00101)-5 Also, 2a base counter 33
- from the integrator 32 when the output of a = (00000)
When the θ output is obtained, the initial values given to the address counters 35a and 35b are as follows, ! Output = (11111), Q output = (00111)
The carrier wave is counted from this initial value using the reference clock, and R
Reproduction is performed by giving the following addresses to the OMs 38a and 38b.

Address counter output 35a 35b ↓ (11111)=31. (00111)-7↓
(00011)-3, (01011)=11↓ (0
0111)=7. (01111)=15↓ (01
011)=11. (10011)=19↓ (01
111)=15. (10111)-23↓ (10
011)-19, (10111)=27↓ (1011
1)-23, (11111)=31↓ (11011)
-27, (00011)=3 In this way, also in this case, the 2'' base counter 33a.

Waveform ROM38a with a phase according to the phase information from 33b
, 38b are generated, and a reproduced carrier wave whose phase is controlled in a direction that eliminates the phase difference between the received signal carrier wave and the reproduced carrier wave is obtained.

Note that, as understood from the above explanation, the waveform ROM 38
a and 38b are data of one cycle of the stored carrier wave so that the phase change of the reproduced carrier wave that occurs when the initial value of the read address is changed by one address is equal to or smaller than the required phase accuracy of the reproduced carrier wave. Select the number.

In the above, this invention was applied to the demodulation of orthogonal modulation signals, but
It can also be applied to demodulation of digital modulation signals of other modulation methods, such as FSX and BPSK.

"Effects of the Invention" As described above, according to the present invention, the carrier regeneration circuit can be constructed entirely of digital circuits. This allows the circuit to be miniaturized, and eliminates adjustments due to variations in characteristics of analog elements such as vCO, temperature characteristics, etc., making it possible to eliminate adjustment of the circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a specific example thereof, FIG. 3 is a diagram showing an example of the relationship between amplitude information of a carrier waveform stored in a waveform ROM and addresses, and FIG. FIG. 4 is a diagram showing an example of addresses with different generation phases and output carrier waveforms. FIG. 5 is a diagram showing the relationship between the output (phase information) of the binary counter 33 and the read address of the waveform ROM 38 a. FIG. 6 is a block diagram showing another embodiment of the present invention, FIG. 7 is a block diagram showing a specific example of FIG. 6, and FIG. 8 is a block diagram showing a conventional carrier recovery circuit.

Claims (2)

[Claims] (1) In a circuit that demodulates the signal by supplying a digitally modulated received signal and a regenerated carrier wave to a synchronous detection circuit, a phase control signal that generates a digital phase control signal according to the phase difference between the received signal carrier wave and the regenerated carrier wave is used. a control signal generation circuit; a digital integrator that integrates the phase control signal and outputs a digital error signal; a phase information generation circuit that receives the error signal and outputs digital phase information in accordance with the error signal; An address counter that counts a reference clock to generate an address; an address conversion circuit that converts the address of the address counter according to the phase information; the output of the address conversion circuit is supplied as an address; An all-digital carrier wave regeneration circuit comprising: a carrier wave generator that reads out the reproduced carrier waveform and outputs the regenerated carrier wave; (2) In a circuit that demodulates the signal by supplying a digitally modulated received signal and a regenerated carrier wave to a synchronous detection circuit, a phase control signal that generates a digital phase control signal according to the phase difference between the received signal carrier wave and the regenerated carrier wave. a control generation circuit; a digital integrator that integrates the phase control signal and outputs a digital error signal; a phase information generation circuit that inputs the error signal and outputs digital phase information in accordance with the error signal; an address counter in which phase information is preset and counts the reference clock; a carrier wave generator to which the count value of the address counter is supplied as an address, reads out a stored carrier waveform according to the address, and outputs the reproduced carrier wave; An all-digital carrier wave regeneration circuit comprising: