JPH0344424B2 - - Google Patents
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- Publication number
- JPH0344424B2 JPH0344424B2 JP60072133A JP7213385A JPH0344424B2 JP H0344424 B2 JPH0344424 B2 JP H0344424B2 JP 60072133 A JP60072133 A JP 60072133A JP 7213385 A JP7213385 A JP 7213385A JP H0344424 B2 JPH0344424 B2 JP H0344424B2
- Authority
- JP
- Japan
- Prior art keywords
- misfet
- type
- source
- conductivity type
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体集積回路に関し、特に相補型
MISFETを有する半導体集積回路に関する。[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to semiconductor integrated circuits, and particularly to complementary type integrated circuits.
Related to semiconductor integrated circuits having MISFETs.
（従来の技術）
一般に、MISFETは飽和領域で作動する際に
チヤンネルのピンチオフしている部分でインパク
トイオン化を起こし、電子−正孔対を生成するこ
とが知られている。(Prior Art) Generally, it is known that when a MISFET operates in a saturation region, impact ionization occurs in the pinched-off portion of the channel to generate electron-hole pairs.
相補型MIS半導体集積回路（以下Ｃ−MIS−
ICと記す）において、その第２導電型のウエル
に形成された第１導電型のMISFETが作動する
場合にも、このインパクトイオン化が起こり、電
子−正孔対が生成される。この生成された電子−
正孔対のうち一方のキヤリアは第１導電型の
MISFETのドレインに流れ込むが、他方のキヤ
リアーは第２導電型のウエルに注入されてしま
う。キヤリアの発生量は発生源である第１導電型
のMISFETの電流能力に比例しているため、電
流能力の大きな第１導電型のMISFETが飽和領
域で作動すると多数のキヤリアが発生源である第
１導電型のMISFETを含む第２導電型のウエル
に注入され、該ウエルのコンタクト抵抗や、コン
タクト面から発生源である第一導電型の
MISFETのチヤンネルまでのウエル抵抗による
電位降下、もしくは電位上昇によつて第２導電型
のウエルの電位が変化し、ラツチアツプが発生す
る。その一例として第１導電型をＮ型、第２導電
型をＰ型とした時のＣ−MIS−ICのラツチアツ
プについて図面を用いて説明する。 Complementary MIS semiconductor integrated circuit (hereinafter referred to as C-MIS-
When a MISFET of the first conductivity type formed in the well of the second conductivity type is activated in the IC (denoted as IC), this impact ionization occurs and electron-hole pairs are generated. This generated electron-
One carrier of the hole pair is of the first conductivity type.
The carrier flows into the drain of the MISFET, but the other carrier is injected into the well of the second conductivity type. The amount of carrier generation is proportional to the current capacity of the first conductivity type MISFET, which is the generation source, so if the first conductivity type MISFET, which has a large current capacity, operates in the saturation region, a large number of carriers will be generated in the first conductivity type MISFET, which is the generation source. It is implanted into a well of the second conductivity type that contains a MISFET of the first conductivity type, and the contact resistance of the well and the source of the first conductivity type from the contact surface are
The potential of the second conductivity type well changes due to a potential drop or potential increase due to the well resistance up to the channel of the MISFET, and a latch-up occurs. As an example, a latch-up of a C-MIS-IC when the first conductivity type is N type and the second conductivity type is P type will be explained with reference to the drawings.
第２図は従来の相補型MIS半導体集積回路の一
例の模式断面図である。 FIG. 2 is a schematic cross-sectional view of an example of a conventional complementary MIS semiconductor integrated circuit.
Ｎ型半導体基板１にＰ型ウエル２を設け、その
中にＮ型のソース３とドレイン４を設ける。絶縁
膜５，ゲート絶縁膜６，ゲート電極７を設けて、
Ｎ型MISFETを構成する。ソース３は接地する。
８はチヤンネル領域である。 A P-type well 2 is provided in an N-type semiconductor substrate 1, and an N-type source 3 and drain 4 are provided therein. An insulating film 5, a gate insulating film 6, and a gate electrode 7 are provided,
Configures an N-type MISFET. Source 3 is grounded.
8 is a channel area.
一方、半導体基板１にはＰ型のMISFETを形
成する。図にはそのソース９のみを図示する。ソ
ース９は電極Vccに接続される。 On the other hand, a P-type MISFET is formed on the semiconductor substrate 1. Only the source 9 is shown in the figure. Source 9 is connected to electrode Vcc.
（発明が解決しようとする問題点）
今、上記のＮ型MISFETのドレイン４とゲー
ト７に高レベルの電圧を印加すると、電界効果に
よりＮ型チヤンネル領域８が形成され、ソース３
からドレイン４へ電子が移動する。この電子がＮ
型チヤンネル領域中のピンチオフ領域で半導体結
晶のシリコン原子と衝突し、電子−正孔対を生成
する。この電子−正孔対のうち電子はドレイン電
流としてドレインへ流れ込み、正孔はＰ型ウエル
２へ注入される。電子−正孔対の発生量は発生源
であるMISFETの電流能力に比例しているため、
電流能力の大きなMISFETを含むＰ型ウエル２
には多量の正孔が注入され、そのためＰ型ウエル
２の電位がＰ型ウエル内のコンタクト抵抗やウエ
ル抵抗による電位上昇のため接地電位より上昇す
る。(Problem to be Solved by the Invention) Now, when a high level voltage is applied to the drain 4 and gate 7 of the above N-type MISFET, an N-type channel region 8 is formed due to the electric field effect, and the source 3
Electrons move from the drain 4 to the drain 4. This electron is N
Collisions with silicon atoms of the semiconductor crystal in the pinch-off region in the type channel region generate electron-hole pairs. Of these electron-hole pairs, electrons flow into the drain as drain current, and holes are injected into the P-type well 2. Since the amount of electron-hole pairs generated is proportional to the current capacity of the MISFET that is the generation source,
P-type well 2 containing MISFET with large current capacity
A large amount of holes are injected into the P-type well 2, so that the potential of the P-type well 2 rises above the ground potential due to the potential increase due to the contact resistance and well resistance within the P-type well.
Ｎ型MISFETのソース３は、接地電位から変
化しないため、Ｐ型ウエル２の電位がソース３と
Ｐ型ウエル２で形成されるＰ−Ｎダイオードの障
壁電圧を越えると上記Ｐ−Ｎダイオードが順次方
向となり、ソース３とＰ型ウエル２とＮ型半導体
基板１で構成されるNPNバイポーラトランジス
タがオン状態となり、Ｎ型半導体基板１からソー
ス３へ電流が流れる。Ｎ型半導体基板１は電源
Vccに接続されているため、その電位は本来電源
電位であるが前記のNPNバイポーラトランジス
タがオンすることによりＮ型半導体基板１からソ
ース３へ電流が流れ、その電流が大きくなるにつ
れてＮ型半導体基板１の電位がサブコンタクト抵
抗やＮ型半導体基板中の内部抵抗による電圧降下
のため電源電位より下降する。 Since the source 3 of the N-type MISFET does not change from the ground potential, when the potential of the P-type well 2 exceeds the barrier voltage of the P-N diode formed by the source 3 and the P-type well 2, the above-mentioned P-N diode direction, the NPN bipolar transistor composed of the source 3, P-type well 2, and N-type semiconductor substrate 1 is turned on, and current flows from the N-type semiconductor substrate 1 to the source 3. N-type semiconductor substrate 1 is a power supply
Since it is connected to Vcc, its potential is originally the power supply potential, but when the NPN bipolar transistor is turned on, a current flows from the N-type semiconductor substrate 1 to the source 3, and as the current increases, the N-type semiconductor substrate The potential of 1 falls below the power supply potential due to a voltage drop due to the sub-contact resistance and internal resistance in the N-type semiconductor substrate.
Ｐ型MISFETのソース９は電源Vccに接続され
ており、その電位は電源電位である。今、前記の
ようにＮ型半導体基板１の電位が下降し、Ｐ型
MISFETのソース９とＮ型半導体基板１の電位
差がＰ型MISFETのソース９とＮ型半導基板１
で構成されるＰ−Ｎダイオードの障壁電圧を越え
ると前記Ｐ−Ｎダイオードが順方向となり、Ｐ型
MISFETのソース９Ｎ型半導体基板１とＰ型ウ
エル２と、Ｎ型MISFETのソース３で構成され
るPNPN構造のトランジスタがオン状態となり、
ラツチアツプ現象が起こる。 The source 9 of the P-type MISFET is connected to the power supply Vcc, and its potential is the power supply potential. Now, as mentioned above, the potential of the N-type semiconductor substrate 1 decreases, and the P-type
The potential difference between the source 9 of the MISFET and the N-type semiconductor substrate 1 is the source 9 of the P-type MISFET and the N-type semiconductor substrate 1.
When the barrier voltage of the P-N diode, which is composed of
The transistor with the PNPN structure consisting of the source 9 of the MISFET, the N-type semiconductor substrate 1, the P-type well 2, and the source 3 of the N-type MISFET is turned on.
A latchup phenomenon occurs.
このように、Ｐ型ウエル２の電位の変化はラツ
チングアツプ現象の要因となるため、電流能力の
大きなMISFETを用いる場合、ラツチアツプ現
象が起こりやすいと言う欠点があつた。 As described above, since changes in the potential of the P-type well 2 are a cause of the latch-up phenomenon, there is a drawback that the latch-up phenomenon is likely to occur when a MISFET with a large current capacity is used.
本発明の目的は、ラツチアツプ現象を起こすこ
となく、電流能力の大きなMISFETを回路構成
に用いることができる半導体集積回路を提供する
ことにある。 An object of the present invention is to provide a semiconductor integrated circuit in which a MISFET with a large current capacity can be used in the circuit configuration without causing a latch-up phenomenon.
（問題点を解決するための手段）
本発明の半導体集積回路は、第１導電型の半導
体基板と、該半導体基板に設けられた複数の第２
導電型のウエルと、該ウエルにそれぞれ設けられ
た第１導電型の絶縁ゲート型電界効果トランジス
タと、前記半導体基板の前記ウエル以外の領域に
設けられた第２導電型の絶縁ゲート型電界効果ト
ランジスタと、前記複数の第１導電型の絶縁ゲー
ト型電界効果トランジスタのうちの少くとも２個
の絶縁ゲート型電界効果トランジスタのソース、
ドレイン及びゲートをそれぞれ並列接続してそれ
ぞれソース端子、ドレイン端子、ゲート端子に接
続する配線とを含んで構成される。(Means for Solving the Problems) A semiconductor integrated circuit of the present invention includes a semiconductor substrate of a first conductivity type, and a plurality of second semiconductor substrates provided on the semiconductor substrate.
A conductivity type well, a first conductivity type insulated gate field effect transistor provided in each of the wells, and a second conductivity type insulated gate field effect transistor provided in a region other than the well of the semiconductor substrate. and sources of at least two insulated gate field effect transistors of the plurality of first conductivity type insulated gate field effect transistors,
The drain and the gate are connected in parallel, and the wiring is connected to the source terminal, the drain terminal, and the gate terminal, respectively.
（実施例）
次に、本発明の実施例について図面を用いて説
明する。(Example) Next, an example of the present invention will be described using the drawings.
第１図は本発明の一実施例の模式的断面図であ
る。 FIG. 1 is a schematic cross-sectional view of an embodiment of the present invention.
この実施例は、第１導電型をＮ型、第２導電型
をＰ型、ウエルの数を３個として説明する。 This embodiment will be explained assuming that the first conductivity type is N type, the second conductivity type is P type, and the number of wells is three.
この実施例は、Ｐ型の半導体基板１と、この半
導体基板１に設けられた３個のＰ型ウエル２ａ，
２ｂ，２ｃと、これらのウエルにそれぞれ設けら
れたソース３ａ，３ｂ，３ｃ，ドレイン４ａ，４
ｂ，４ｃ，ゲート７ａ，７ｂ，７ｃとから成る絶
縁ゲート型電界効果トランジスタ（これらを図に
Ａ，Ｂ，Ｃで示す）と、半導体基板１のＰ型ウエ
ル以外の領域に設けられたＮ型の絶縁ゲート型電
界効果トランジスタ（図示せず）と、３個の絶縁
ゲート型電界効果トランジスタのうちの少くとも
２個（この実施例では３個）の絶縁ゲート型電界
効果トランジスタのソース、ドレイン及びゲート
をそれぞれ並列接続してそれぞれソース端子Ｓ、
ドレイン端子Ｄ、ゲート端子Ｇに接続する配線１
１，１２，１３とを含んで構成される。 This embodiment includes a P-type semiconductor substrate 1, three P-type wells 2a provided in this semiconductor substrate 1,
2b, 2c, sources 3a, 3b, 3c, and drains 4a, 4 provided in these wells, respectively.
an insulated gate field effect transistor consisting of gates 7a, 4c, and gates 7a, 7b, and 7c (indicated by A, B, and C in the figure); an insulated gate field effect transistor (not shown), and at least two (three in this embodiment) of the three insulated gate field effect transistors. The gates are connected in parallel and the source terminals S,
Wiring 1 connected to drain terminal D and gate terminal G
1, 12, and 13.
MISFET Ａ，Ｂ，Ｃは、ソース，ドレイン，
ゲートをそれぞれ並列接続してあるので一つの
MISFETとして動作する。逆に言えば、
MISFET Ａ，Ｂ，Ｃは一つのMISFETを３分割
したものである。従つて、それぞれの電流能力
は、第２図に示すMISFETのほぼ1/3になつてい
る。 MISFET A, B, C are source, drain,
Since the gates are connected in parallel, one
Operates as MISFET. Conversely,
MISFET A, B, and C are one MISFET divided into three. Therefore, the current capacity of each is approximately 1/3 that of the MISFET shown in FIG.
今、ソース端子Ｓを接地し、ドレイン端子Ｄ，
ゲート端子Ｇにそれぞれ高レベルの電圧を印加す
ると、MISFET Ａ，Ｂ，Ｃはオン状態となり、
それぞれのMISFETのソースードレイン間に電
流ISDが流れる。MISFET Ａ，Ｂ，Ｃは同じもの
であるからその一つについて説明する。 Now, the source terminal S is grounded, the drain terminal D,
When a high level voltage is applied to each gate terminal G, MISFETs A, B, and C are turned on.
A current I SD flows between the source and drain of each MISFET. MISFETs A, B, and C are the same, so one of them will be explained.
MISFET Ａのソース３ａとドレイン４ａとの
間を流れる電流ISDによつて発生する電子−正孔
対の量Ｆは、MISFET Ａのチヤンネル内の空乏
層で電子１個が半導体結晶中のシリコン原子に衝
突してインパクト・イオン化を起こす確率をα(E)
とすると、
Ｆ＝α(E)・ISD
となる。α(E)はMISFETのゲート，ドレイン電
位とバツクゲート電位から決まる空乏層の電界に
よつて決定されるから、この場合の第１図の
MISFET Ａのα(E)と第２図のMISFETのα(E)は
等しい。また第２図のMISFETのオン状態での
ソースドレイン間電流をISD′、その時の電子−正
孔対の発生量をF′とすると第２図のMISFETで
発生する電子−正孔対の量は、
F′＝α(E)・ISD′
となる。ここで、第１図のMISFET ＡのISDは第
２図のMISFETのISDの1/3であるからMISFET
Ａの電子−正孔対の発生量ＦはF′と比べて、
F′＝α(E)・I′SD＝α(E)・3ISD
＝３・α(E)・ISD＝3F
となり、MISFET Ａでの電子−正孔対の発生量
は第２図のMISFETでの発生量の1/3となる。従
つてＰ型ウエル２ａに注入される正孔の量も１／
３となる。また、Ｐ型ウエル２ａ，２ｂ，２ｃの
個々のコンタクト抵抗及びウエル抵抗の総和は、
分割によりＡ，Ｂ，ＣのそれぞれのMISFETの
大きさが小さくなるため、第２図中のMISFET
の抵抗の総和より小さく出来る。従つて、Ｐ型ウ
エルの電位の変化は極く小さくなる。また
MISFET Ａ，Ｂ，Ｃは互いに並列接続されてい
るので、共有の端子Ｓ−Ｄ間に流れる電流ΣISDは
第２図のMISFETのソース−ドレイン間電流
ISD′に等しい。 The amount F of electron-hole pairs generated by the current ISD flowing between the source 3a and drain 4a of MISFET A is the amount F of electron-hole pairs generated by the current I SD flowing between the source 3a and drain 4a of MISFET A. α(E) is the probability of impact ionization caused by collision with
Then, F=α(E)・I SD . α(E) is determined by the electric field in the depletion layer determined by the gate, drain and back gate potentials of the MISFET, so in this case,
α(E) of MISFET A and α(E) of MISFET in FIG. 2 are equal. Also, if the source-drain current of the MISFET in Figure 2 in the on state is I SD ', and the amount of electron-hole pairs generated at that time is F', then the amount of electron-hole pairs generated in the MISFET in Figure 2 is becomes F′=α(E)・I SD ′. Here, the I SD of MISFET A in Figure 1 is 1/3 of the I SD of MISFET in Figure 2, so MISFET
Compared to F', the amount F of electron-hole pairs generated at A is F' = α(E)・I′ SD = α(E)・3I SD = 3・α(E)・I SD = 3F , the amount of electron-hole pairs generated in MISFET A is 1/3 of the amount generated in the MISFET shown in FIG. Therefore, the amount of holes injected into the P-type well 2a is also 1/
It becomes 3. Furthermore, the sum of the individual contact resistances and well resistances of the P-type wells 2a, 2b, and 2c is
Due to the division, the size of each MISFET A, B, and C becomes smaller, so the MISFET in Figure 2
can be smaller than the sum of the resistances. Therefore, changes in the potential of the P-type well become extremely small. Also
Since MISFETs A, B, and C are connected in parallel, the current ΣI SD flowing between the shared terminals SD and D is the source-drain current of the MISFETs in Figure 2.
Equal to I SD ′.
（発明の効果）
以上説明したように、本発明によれば、電流能
力の大きなMISFETのインパクトイオン化によ
るラツチアツプ現象を防ぎ、高速動作が可能な半
導体集積回路が得られる。(Effects of the Invention) As described above, according to the present invention, it is possible to prevent the latch-up phenomenon caused by impact ionization of a MISFET having a large current capacity, and to obtain a semiconductor integrated circuit capable of high-speed operation.
第１図は本発明の一実施例の断面図、第２図は
従来の相補型MIS半導体集積回路の一例の断面図
である。
１……Ｎ型半導体基板、２，２ａ，２ｂ，２ｃ
……Ｐ型ウエル、３，３ａ，３ｂ，３ｃ……ソー
ス、４，４ａ，４ｂ，４ｃ……ドレイン、５……
ゲート絶縁膜、６……絶縁膜、７，７ａ，７ｂ，
７ｃ……ゲート、８……チヤンネル領域、９……
ソース、１１，１２，１３……配線、Ｄ……ドレ
イン端子、Ｇ……ゲート端子、Ｓ……ソース端
子。
FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of an example of a conventional complementary MIS semiconductor integrated circuit. 1...N-type semiconductor substrate, 2, 2a, 2b, 2c
... P-type well, 3, 3a, 3b, 3c ... source, 4, 4a, 4b, 4c ... drain, 5 ...
Gate insulating film, 6...Insulating film, 7, 7a, 7b,
7c...Gate, 8...Channel area, 9...
Source, 11, 12, 13... Wiring, D... Drain terminal, G... Gate terminal, S... Source terminal.
Claims (1)
設けられた複数の第２導電型のウエルと、該ウエ
ルにそれぞれ設けられた第１導電型の絶縁ゲート
型電界効果トランジスタと、前記半導体基板の前
記ウエル以外の領域に設けられた第２導電型の絶
縁ゲート型電界効果トランジスタと、前記複数の
第１導電型の絶縁ゲート型電界効果トランジスタ
のうちの少くとも２個の絶縁ゲート型電界効果ト
ランジスタのソース、ドレイン及びゲートをそれ
ぞれ並列接続してそれぞれソース端子、ドレイン
端子、ゲート端子に接続する配線とを含むことを
特徴とする半導体集積回路。1 A semiconductor substrate of a first conductivity type, a plurality of wells of a second conductivity type provided in the semiconductor substrate, an insulated gate field effect transistor of a first conductivity type provided in each of the wells, and the semiconductor substrate an insulated gate field effect transistor of a second conductivity type provided in a region other than the well, and at least two of the plurality of insulated gate field effect transistors of the first conductivity type; What is claimed is: 1. A semiconductor integrated circuit comprising wiring that connects the source, drain, and gate of a transistor in parallel and connects them to the source terminal, drain terminal, and gate terminal, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60072133A JPS61230356A (en) | 1985-04-05 | 1985-04-05 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60072133A JPS61230356A (en) | 1985-04-05 | 1985-04-05 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61230356A JPS61230356A (en) | 1986-10-14 |
| JPH0344424B2 true JPH0344424B2 (en) | 1991-07-05 |
Family
ID=13480486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60072133A Granted JPS61230356A (en) | 1985-04-05 | 1985-04-05 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61230356A (en) |
-
1985
- 1985-04-05 JP JP60072133A patent/JPS61230356A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61230356A (en) | 1986-10-14 |
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