JPH0344687B2 - - Google Patents

Description

Detailed Description of the Invention (a) Field of Industrial Application The present invention relates to a bias circuit for supplying base bias to differentially connected first and second transistors, and particularly relates to a bias circuit for supplying base bias to differentially connected first and second transistors. The present invention relates to a bias circuit that can set the offset voltage between the bases of two transistors regardless of the power supply voltage.

(b) Prior Art A differential amplifier circuit as shown in FIG. 1 of Japanese Patent Publication No. 45-29246 has been known. Therefore, the differential amplifier circuit operates as an amplifier by operating the differentially connected transistors in the active region.
When operated in the saturation region, it operates as a comparator.
FIG. 2 shows an example in which the differential amplifier circuit is used as a comparator, in which an input signal source 2 is connected to the base of the first transistor 1, and a reference voltage source 4 is connected to the base of the second transistor 3. A PNP type output transistor 5 is connected to the collector of the first transistor 1. Now, if the voltage of the reference voltage source 4 is V ₀ and no bias voltage is applied to the base of the first transistor 1, when the output signal Vi of the input signal source 2 is Vi<V ₀ , the first transistor 1 off, the second transistor 3 is on, and when Vi>V ₀ , the first transistor 1 is on and the second transistor 3 is off. Furthermore, if a bias of V ₁ is applied to the base of the first transistor 1, when the output signal Vi of the input signal source 2 is Vi<V ₀ −V ₁ , the first transistor 1 is turned off, and the second transistor 3 is turned on, and when Vi>V ₀ -V ₀ , the first transistor 1 is turned on and the second transistor 3 is turned off. and,
When the first transistor 1 is turned on, the load resistor 6
A voltage drop occurs, the output transistor 5 is also turned on, and an output signal is generated at the output terminal 7. Therefore, in the comparator of FIG. 2, the reference voltage V ₀ or the difference voltage between the reference voltage and the bias voltage V ₀
An output signal will be generated when an input signal exceeding −V ₁ is applied, and the difference voltage V ₀ or V ₀ −
V ₁ becomes the offset voltage of the comparator.

(c) Problems to be solved by the invention By the way, the reference voltage V ₀ and the bias voltage
In the case of an integrated circuit comparator, V ₁ is set by its internal circuit, so it usually depends on the power supply voltage. Therefore, there is a drawback that the characteristics change when the power supply voltage fluctuates. A bias circuit including first and second bias transistors commonly connected to each other and a third bias transistor whose emitters are connected to the common base of the first and second transistors via a resistor is disposed, and a differential connection is made. The base bias voltage of the differentially connected first transistor is set according to the collector current of the first bias transistor, and the base bias voltage of the differentially connected second transistor is set according to the base voltage of the third bias transistor. That is.

(E) Effect According to the present invention, the first and second differentially connected
Since the transistor base bias voltage is provided by a single bias circuit, the offset voltage is set depending on the value of the resistor within said bias circuit.

(F) Embodiment FIG. 1 shows an embodiment of the present invention. 8
A first transistor 10 whose base is connected to the input terminal 9, and a second transistor 1 whose emitter is commonly connected to the emitter of the first transistor 10.
1, and an output transistor 12 whose base is connected to the collector of the first transistor 10; 13 , whose collector is a resistor 14;
a first bias transistor 15 connected to the base of the first transistor 10 via a second bias transistor 16 whose base and emitter are commonly connected to the first bias transistor 15; A first resistor 17 is connected between the common base of the transistors 15 and 16 and ground, and the emitter is connected to the first and second bias transistors 15 via a second resistor 18.
and a third bias transistor 19 connected to the common base of the transistors 16 and 16, and a diode 2 connected between the base of the third bias transistor 19 and the collector of the second bias transistor 16.
0, and third and fourth resistors 21 and 22 connected in series between the collector of the third bias transistor 19 and the power supply (+Vc.c.). The base of the first transistor 10 of the comparator 8 is biased according to the collector current of the first bias transistor 15, and the base of the second transistor 11 of the comparator 8 is biased according to the collector current of the first bias transistor 15.
It is biased by a voltage obtained at the connection midpoint of the third and fourth resistors 21 and 22 in accordance with the base voltage of the third bias transistor 19.

Next, the operation will be explained. When the power supply (+Vc.c.) is turned on, an operating current flows through each part of the bias circuit 13 , and the base voltage of the third bias transistor 19 increases.
V _B1 is: V _B1 = 2V _BE + R ₂ /R ₁ V _BE (1) [However, V _BE is the base-emitter voltage of the second and third bias transistors 16 and 19,
R ₁ is the resistance value of the first resistor 17, R ₂ is the second resistor 18
resistance value]. Therefore, the second transistor 1 of the comparator 8
1 base voltage V ₂₂ is V _B2 = V _B1 + R ₄ / R ₃ + R ₄ (Vc.c.-V _B1 )...(2) [However, R ₃ is the resistance value of the third resistor 21, R ₄ is the resistance value of the fourth resistor 22]. On the other hand, the first transistor 10 of the comparator 8
If _the terminal voltage of _the bias power supply 23 is _{V BE} , then _the base _voltage V _{B3 of} is the collector current of the first bias transistor 15]. By the way, since the bases and emitters of the first and second bias transistors 15 and 16 are commonly connected, the collector current of the first bias transistor 15 and the collector current of the second bias transistor 16 are equal to each other. Collector current of second bias transistor 16
I ₂ becomes I ₂ =Vc.c.−V _B1 /R ₃ +R ₄ (4). Therefore, the base voltage V _B3 of the first transistor 10 is calculated from equations (3) and (4) as follows: V _B3 = V _BE + R ₅ /R ₃ + R ₄ (Vc.c.-V _B1 )...(5 ) becomes. Therefore, the value R ₄ of the fourth resistor 22 and the resistor 1
4 and _R5 are set equal, the voltage between the bases of the first and second transistors 10 and 11 of the comparator 8 , that is, the offset voltage ΔV, is as follows: ΔV=V _B2 −V _B3 = V _BE +R ₂ /R ₁ V _BE (6), which is determined according to the resistance values of the first and second resistors 17 and 18. In the case of FIG. 1, when the voltage applied to the input terminal 9 exceeds the offset voltage ΔV, the first transistor 10 is turned on, the output transistor 12 is also turned on, and an output signal is generated at the output terminal 24. , the comparator 8 operates according to the offset voltage ΔV.

As mentioned earlier, the offset voltage ΔV of the comparator 8 is determined according to the values R ₁ and R ₂ of the first and second resistors 17 and 18, so the value R ₁ of the first resistor 17
is fixed and the value R ₂ of the second resistor 18 is varied,
An offset voltage corresponding to the resistance value _R2 of the second resistor 18 can be obtained. In that case, the second
When the value of the resistor 18 is increased, the base bias voltage of the second transistor 11 of the comparator 8 increases, and the base bias voltage of the first transistor 10 decreases. Furthermore, when the value of the second resistor 18 is made small, the base bias voltage of the second transistor 11 decreases and the base bias voltage of the first transistor 10 increases. Therefore, the second resistor 1
The offset voltage can be changed greatly by a small change of 8. Furthermore, as is clear from equation (6), the offset voltage can be set independently of the power supply voltage, so it is possible to provide a bias circuit that is resistant to fluctuations in the power supply voltage.

Incidentally, since the diode 20 is inserted and the collector voltages of the first and second bias transistors 15 and 16 are set to be equal, the Early effect can be prevented, and the collector voltages of the first and second bias transistors 15 and 16 can be prevented. The degree of matching of the collector currents is further improved.

(g) Effects of the Invention As described above, according to the present invention, it is possible to provide a bias circuit that can bias the bases of a pair of differentially connected transistors regardless of the power supply voltage. Furthermore, according to the present invention, it is possible to provide a bias circuit that can arbitrarily set the offset voltage of a pair of differentially connected transistors simply by changing the resistance value. Further, according to the present invention, it is possible to provide a bias circuit that can be integrated into a circuit with a transistor to be biased.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional differential amplifier circuit. Explanation of main figure numbers, 8 ... Comparator, 10... 1st
Transistor, 11...Second transistor, 13
...Bias circuit, 15...First bias transistor, 16...Second bias transistor, 1
7...first resistor, 18...second resistor, 19...third bias transistor.

Claims (1)

[Claims] 1 A bias circuit for biasing the bases of differentially connected first and second transistors with a predetermined offset, the first transistor having a collector connected to the base of the first transistor via a resistor. a bias transistor, a second bias transistor whose base and emitter are commonly connected to the base and emitter of the first bias transistor, and a first resistor connected between the base and emitter of the first bias transistor;
a third bias transistor whose emitter is connected to the base of the first bias transistor via a second resistor; third and fourth resistors connected in series between a power supply and the third bias transistor; and means for connecting the connection point of the third and fourth resistors to the base of the second transistor, and by setting the values of the resistor and the fourth resistor to be substantially equal, the offset voltage between the bases of the first and second transistors can be adjusted. A bias circuit characterized in that: is set according to the value of the second resistor.