JPH0344874A - Pulse noise correcting circuit - Google Patents

Abstract

PURPOSE:To always realize satisfactory correction by controlling the feedback quantity of a signal feedback path by an output from the level detector of a noise reduction decode circuit to which suitable weighing is applied so as to increase a relative level in a high area frequency. CONSTITUTION:The feedback quantity of a signal feedback path 4 is controlled by a control signal corresponding to the output from a level detector 11a of a noise reduction decode circuit 6, to which weighing is applied so as to increase the relative level in the high area frequency, and inclination at the time of hold is changed corresponding to a signal frequency and a signal level. Accordingly, since the signal feedback quantity for differential hold correction is enough enlarged in a place where the frequency and level of an audio signal are high, the inclination of a corrected waveform is enlarged and since the feedback is limited in a place where the frequency and level are reversely low, the inclination of the corrected waveform is made smooth and close to preceding-value hold correction. Thus, the correction can be executed to be matched with respective signal states.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse noise correction circuit for removing pulse noise contained in a reproduced audio signal in a video tape recorder (hereinafter referred to as rVTRJ).

BACKGROUND OF THE INVENTION In a high-fidelity VTR that records and reproduces an audio signal along with a video signal on the same track (video track), the audio signal is also alternately reproduced one track at a time by two rotating heads. Therefore, when the recording signal (FM) is returned to a predetermined audio signal, pulse noise (hereinafter also referred to as "switching noise") (24
) is added to the audio signal (S). In addition, in the figure, (a) shows the head switching pulse (25). As described above, prior value hold correction circuits and differential hold correction circuits have been known as circuits for removing switching noise (24) contained in audio signals. In the former case, as shown in FIG. 9, a switch (2) is provided on the output side of the buffer (1) to which the demodulated audio signal is applied, and a capacitor (C2) is provided behind this switch (2).
2) is the switching pulse (25) shown in FIG. 8(C).
By turning off the hold pulse (26) synchronized with the transition of the pulse (26), the level of the audio signal immediately before the switching noise (24) is held in the capacitor (C+). In addition, in FIG. 9, (3) is an amplifier.

On the other hand, as shown in FIG. 10, the differential hold correction circuit is the previous value hold circuit of FIG. A configuration is provided in which the signal returns to the capacitor (C+) side through a signal feedback path (4) consisting of This is what I did.

Figure 11 shows that switching noise (24) is AB in the previous value hold correction circuit and AB' in the @ minute hold correction circuit.
It shows that it will be corrected as follows.

However, the correction by the previous value hold correction circuit is the first
As shown in Figure 2 (a) and (b), the audio signal (S
), the hold distortion (27) remains, although it is smaller than the switching noise (24).

This hold distortion (27) is relatively small when the frequency is low because the waveform of the audio signal (S) is large and the slope angle is relatively gentle, so it is not noticeable to the audibility, but at high frequencies Since the waveform of the audio signal becomes narrow and the slope angle becomes steep, the hold distortion becomes relatively large and stands out as noise.

On the other hand, although the correction by the differential hold correction circuit is good at high frequencies, it is not good at low frequencies or when the S/N ratio of the audio signal is poor. For example, when the S/N ratio is poor, the audio signal waveform (
In the peak part of S), the peak of noise (28) (P2)
Error corrections (errors) exceeding 100% may occur. The noise that causes this can be removed to some extent with a low-pass filter (LPF), but at the same time, the pulse width expands due to the group delay, making it necessary to widen the correction width, so excessive filtering has the opposite effect. .

In this respect, in the previous value correction hold, as shown in FIG. 13(a), at most the peak value (Pl) of the noise (28) is corrected.

The present invention has been made in view of these points, and it is an object of the present invention to provide a switching noise correction circuit that can always achieve good correction regardless of the frequency or level of an audio signal.

In order to achieve the above object, the present invention provides a method for removing pulse noise based on head pulse pulses contained in an audio signal reproduced from a video track of a recording medium in a video tape recorder. In a pulse noise correction circuit that is equipped with a capacitor for value hold correction and a signal return path for differential hold correction that differentially feeds back an audio signal to the capacitor, a pulse noise correction circuit is provided at a subsequent stage to increase the relative level at high frequencies. The feedback amount of the signal feedback path is controlled by the weighted output of the level detector of the noise reduction decoding circuit.

According to this configuration, the slope of the correction waveform by the correction circuit changes between the previous value hold correction and the differential hold correction according to the output of the level detector that carries information on the frequency and level of the signal. become.

Embodiment 2 In FIG. 1 in which the present invention is implemented, the same parts as in the conventional example of FIG. 10 are given the same reference numerals. In this embodiment, the signal feedback path (4) for differentially feeding back the output of the amplifier (3) to the capacitor (C1) is constructed using a capacitor (CZ) and a variable resistor (5
), and the resistance value (R) of this variable resistor (5) is controlled by a control signal from a noise reduction decoding circuit (6).

Here, (7) and (8) are IC (semiconductor integrated circuit)
The capacitors (C8) and (C2) are externally connected via these terminals (7) and (8). Variable resistance (
5) is formed within ■C. The noise reduction decoding circuit (6) is a well-known circuit that has been conventionally provided in high-fidelity audio VTRs.
3) a de-emphasis circuit (9a) for de-emphasizing the output of 3) and a buffer (30) for receiving the audio signal given through the low-pass filter (9b) with a cut-off frequency of 20 KHz for cutting out the audio band, and the audio signal. A weighting circuit (10) that increases the gain of high-frequency components of
10) A level detector (l) detects the level of the output signal of
a), a smoothing circuit (llb), a transistor (T2) for driving the output section of the voltage/current converter (12) that converts the level-detected output voltage into a current, and a signal from the buffer (30). In addition to amplifying the transistor (
Variable current amplifier (3) whose gain changes depending on the output current of T2
1) And noise reduction emphasis times! (32
). Then, the output is sent to the amplifier (33
) to the output terminal (34). The output voltage at point (W) of the noise reduction circuit (6) (i.e., the level-detected smoothed output voltage) has a frequency characteristic as shown in Figure I4 for the human power of the de-emphasis circuit (9a) at a constant level. present. In this embodiment, in order to vary the resistance value of the variable resistor (5) using the smoothed output of the level detector (Ila), the drive transistor (T2) of the output section of the voltage/current converter (12) and the base A transistor (T,) connected in common is added to the voltage/current converter output, and the output current of this transistor (T,) is connected to a variable resistor (
5).

In this case, the voltage at the point is weighted toward the high frequency components of the audio signal as shown in FIG. 14, and relatively little occurs in the low frequency components. Moreover, an output voltage proportional to the level of the audio signal can be obtained. When the voltage at this (-) point is converted into a current, the current in the low frequency portion of the audio signal is almost small, and the current value in the high frequency portion varies depending on the level of the audio signal. By applying this current to the variable resistor (5) via the transistor (T3), the resistance value of the variable resistor (5) (
R) is increased in the low frequency range and decreased in the high frequency range according to the level of the audio signal.

Furthermore, when the resistance value R2 of the variable resistor (5) is changed within the range of R0≦R2≦ω, the cutoff frequency fc of the feedback path (4) becomes Q<fc=−−1−1≦1 2πCzRt 2 πC, R0 becomes. As mentioned earlier, the variable resistor (5) can be configured with an IC, but
An example will be explained. First, the variable amplifier circuit shown in Fig. 4 has an input voltage of V, , V, -, and a constant current source (13).
The constant current of (14) is ■, respectively. + Ir, ) If both the emitter resistances of transistor (1 (at)) are Rt, the output current i is = ±・Y”-(VI+-Vl-)...--■
! OR,I.

becomes. Here, if the input end (6) and the output @ (17) are directly connected as shown in Fig. 2, this circuit will be connected to the 5th
It can be represented as shown in Figure (A), and furthermore, as shown in Figure (B), the buffer part (18) and the variable resistance part (19)
becomes. If the resistance value of the variable resistance part (19) is R2, then R・= (V par −9・−) −・−・・−・・−■t
.

Substituting 16 of formula 0 into this, 1゜Rt==Rt ・ □ −−−・・・−・−・
−・■r. That is, R2 can be varied by changing the r,/IrO ratio. Therefore, variable resistor (5) in Figure 1
As shown in FIG. 2, Ir may be varied by the output of the noise reduction decoding circuit (6). Variation of the current 1r is performed by extracting an emitter current obtained by controlling the pace voltage of the transistor (T3) of the output section of the voltage/current conversion circuit (12) from the collector.

Next, the embodiment of FIG. 3 has a variable amplifier (2) in the feedback path (4).
3) is inserted, and the feedback amount is controlled by controlling the gain Av of this variable amplifier (23). The other configurations are the same as in FIG. The circuit shown in FIG. 4 can be used as the variable amplifier (23). That is, if a load resistor (Ro) is connected between the output @ (17) and the ground point in Fig. 4, this circuit can be expressed as shown in Fig. 6, and its gain ^ν is vO Avz --... −・・−・−・−■ v1゜−V, − Here, using the formula since vo is R810, RO
If /RE is constant, Ir/T. By varying Av, Av can be changed. In the embodiments shown in FIGS. 1 and 4, the variable resistor (5) or the variable amplifier (23
) and the collector of the transistor (T, ) to limit the current Tr to O<Ir<Irmax. Here Irmax is the amplifier (3)
When the gain of (23) is AV,, AV2, Av1
This is a current value that satisfies +Av2=1+C+/Cz. This limits the maximum value of the feedback amount and prevents the differential slope from becoming excessive. However, in the embodiment shown in FIG. 1, Av, =
It is O.

In both the variable resistance configuration of FIG. 1 and the variable gain configuration of FIG. 3 described above, the slope of the correction waveform changes as shown in FIG. 7.

For example, in the case of the variable resistance configuration shown in Fig. 1, the gain Av of the amplifier (3) and the capacitance C, C2 of the capacitor are
When the resistance value Rx of the variable resistor (5) changes from a constant value R2 to ω within a range that satisfies Av-I 2 , the cutoff frequency of the feedback path is 2. . The change from zRt to O, that is, the slope of the waveform changes as shown from AB' to AB in FIG. 7 depending on the frequency.

In addition, in the variable gain configuration shown in FIG. 3, the gain A of the amplifier (3) is
v+, gain Avz of variable resistor (23), Avz
By changing the gain of 1'-+1-Avt to O, the feedback rate changes and the cut-off frequency. □. Below zRz, the slope of the waveform is A
It changes from B' to AB.

As described above, in the variable resistance configuration, by increasing the resistance value, it is possible to sequentially change the differential hold correction state to the previous value hold correction state from the high frequency component of the signal frequency, and in the variable gain configuration, the gain By lowering , it is possible to continuously change the differential hold correction state to the previous value hold correction state simultaneously in the entire signal frequency band.

In each of the above embodiments, if a time constant circuit consisting of a resistor (R3) and a capacitor (C3) is further connected to both ends of the capacitor (C+), the feedback of the feedback path (4) is activated (when the waveform of the audio signal is The feedback rate from the feedback path (4) decreases for a portion significantly away from the center (operating point) of the waveform, which is preferable because correction similar to the audio waveform can be obtained.

Effects of the Invention As described above, according to the present invention, the amount of signal feedback for differential hold correction becomes sufficiently large where the frequency and level of the audio signal are high, so the slope of the correction waveform also becomes large, and conversely, when the frequency and level of the audio signal are high, /Or, since the feedback is limited where the level is low, the slope of the correction waveform becomes gentle, approaching the previous value hold correction, and the effect is that pulse noise correction that matches the signal condition in each case is performed. . Moreover, since the control signal for such correction is extracted using the output of the level detector of the noise reduction decoding circuit, only a small number of circuits need to be added to the existing circuit, and the design is easy.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit configuration diagram of a pulse noise correction circuit embodying the present invention, and FIG. 2 is a circuit diagram showing a specific example of a part thereof. FIG. 3 is a circuit diagram of another embodiment of the present invention. FIG. 4 is a diagram showing an example of a circuit used in the embodiments of FIGS. 1 and 3, and FIGS. 5 and 6 are simplified diagrams thereof. FIG. 7 is an explanatory diagram of the operation of the embodiment of the present invention. FIG. 8 is a diagram for explaining general switching noise processing. FIG. 9 is a diagram showing a conventional previous value hold correction circuit, and FIG. 10 is a diagram showing a conventional differential hold correction circuit. FIG. 11 is a diagram for explaining correction by the circuits of FIGS. 9 and 10. Figure 12 is the 9th
It is an explanatory view of a figure. FIG. 13 is a diagram for explaining FIGS. 9 and 10. FIG. 14 is a diagram showing the frequency characteristics at point (W) in FIG. 1. (4)--Signal return path, (5)--Variable resistor (6)
-Noise reduction decoding circuit. (lla)--Level detector, (23)--Variable amplifier. (24)-m-switching noise. (25)-m-head switching pulse. (C3)... Capacitor for previous value hold correction. (T3) --- Drive transistor.

Claims (1)

[Claims] (1) In order to remove pulse noise based on head switching pulses contained in an audio signal reproduced from a track of a recording medium in a video tape recorder, the audio signal is differentially fed back to a capacitor for previous value hold correction and the capacitor. A pulse noise correction circuit comprising a signal return path for differential hold correction, and control according to the output of a level detector of a noise reduction decoding circuit weighted so that the relative level increases at high frequencies. A pulse noise correction circuit characterized in that the feedback amount of the signal return path is controlled by a signal, and the slope at the time of hold is changed according to the signal frequency and signal level.