JPH0344939A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the yield by forming a film of a high melting point metal containing a non-metal group element on a silicon film, forming thereon a high-melting-point-metal-based film and carrying out heat treatment or electromagnetic wave irradiation treatment. CONSTITUTION:Cr metal 2 is deposited on a glass substrate 1, and etched selectively. Then, a first SiNx layer 3, an a-Si layer 4 scarcely containing an impurity, and again a second SiNx layer 5 are successively deposited thereon. Next, after the layer 5 is left only on a gate, a first MoSi2 layer 6, a second MoSi2 layer 7 are formed, and this process is repeated five times successively. Then, Al 8, 9 are deposited on the whole surface by sputtering and then selectively etched with phosphoric acid series solution, and thus formed Al pattern is used as a mask to selectively etch the MoSi2 and a-Si layers with hydrofluoric/nitric acid solution to form a drain electrode 8 and a source electrode 9. Finally, P element is diffused from the MoSi2 layer to the a-Si layer to achieve the activation of P ions.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and particularly to a method for manufacturing a semiconductor device using a non-single crystal silicon film.

Conventional Technology Thin film transistor arrays using amorphous silicon (hereinafter abbreviated as A-8I) can be made large in area at low temperatures;
Due to its excellent stability, it is being actively applied to LCD substrates and image sensors. Furthermore, thin film transistor arrays using this a-3L can have a wide variety of configurations, and there are an infinite number of manufacturing methods. Among them, those with an inverted staggered structure are described below.

Figure 3 is a cross-sectional view of the thin film transistor process.
) is a gate electrode forming step, in which, for example, Cr metal 2 is deposited to a thickness of 100 OA by sputtering, and the C
In the process of selectively etching the r metal 2 with a solution containing cerium ammonium nitrate as the main component,
) process is a three-layer deposition process, for example 4000A1500
The first silicon nitride layer (hereinafter 5
INX layer) 3, a first a-Si layer 4 containing almost no impurities and again a second 5INX layer 5 are preferably successively deposited. All of these thin films are made of silane (
The raw material gas whose main component is gas (hereinafter abbreviated as SiL layer) is
It is fabricated by plasma CVD, which synthesizes fractions using high-frequency glow discharge at a temperature of around 00°C. The process in the same figure (C) is a semiconductor layer protective film forming process, in which the second SiN layer 5 is selectively left only on the gate, and then PH is applied to 5iHa gas.
500A over the entire surface by plasma discharge with 3 gases added
A second aSiJi layer 11 containing impurities is deposited to a thickness of about 100 mL. The process shown in FIG. 2(d) is the source/drain electrode forming process. For example, MoSi2/A18.9 is deposited at 100OA/7000A on the entire surface by sputtering, and then A18.9 is deposited on the entire surface using a phosphoric acid solution.
In this step, MoSi2, the first and second a-3i layers are selectively etched using a fluoronitric acid solution as an AI parameter mask formed by selectively etching MoSi2. It was shown in Japanese Unexamined Patent Application Publication No. 57-111 that stable capacity could be achieved with this structure.
Problems to be Solved by the Invention Disclosed in Publication No. 45968 The conventional TPT array described above requires a process for forming seven films, which inevitably results in a number of photomasks of four or more, resulting in a long manufacturing process and high cost. Although the plasma CVD method is an established technology in the manufacturing process, the maintenance cycle is very short compared to other equipment, and the maintenance method is difficult.Also, it is difficult to control because there are many parameters.
It is necessary to establish a stable process by reducing the number of times as much as possible.

And n is an obstacle to improving process yield.
There is a problem of "a-3i peeling."

Conversely, unless an l'a-3i layer is interposed between the metal used for the source/drain electrode and the a-3i layer that does not contain impurities, it is difficult to form an ohmic connection, and between the metal and the a7Si layer. Must maintain its barrier layer +1TP
There is large variation in the performance of each T.

After selectively forming the a-3i layer, the ability to form a film containing a non-metal group element in a material containing a high melting point metal as the main component\ Also (1) A plate in which a non-metallic group element is subjected to either a concentration gradient in the depth direction or a concentration gradient of the element as it approaches the silicon film. A method in which nonmetal group elements are diffused into an impurity-free a-3i layer by applying one of the two methods (a method that causes peeling of the film when heat treatment or electromagnetic wave irradiation treatment such as light is applied).

SUMMARY OF THE INVENTION In view of the problems of the prior art, it is an object of the present invention to provide a method for manufacturing a semiconductor device with a simple structure, fewer steps, and a low defect rate and low wiring resistance.

Means for Solving the Problems In the present invention, after selectively forming an a-Si layer, a material mainly composed of a high melting point metal is made to contain a non-metal group element by a doping method, and then a material mainly composed of a high melting point metal is added. A film is formed by repeating the same substance at least once. Furthermore, a material containing a high-melting-point metal as a main component and a non-metal group element that has been subjected to either a concentration gradient in the depth direction or a concentration gradient of the element as it approaches the silicon film at least once. After the film is formed by repeating the above steps, at least one of heat treatment and electromagnetic wave irradiation treatment such as light is applied to diffuse non-metal group ions into the a-3i layer containing no impurities to form an ohmic connection.

Effect: By using the above means, it is not necessary to form an n''a-3i film, and the yield can be increased (de), TPT array characteristics can be improved. The ability to form a film in which a substance whose main component is a high-melting point metal is repeated at least once after containing a non-metal group element by a doping method
Tomo: A material whose main component is a high-melting-point metal is treated with a non-metal group element either with a concentration gradient in the depth direction or with a concentration gradient of the element closer to the silicon film, which is repeated at least once. A semiconductor device with a structure in which a film is formed ζ′! , the plasma CVD method can be configured only once, reducing the number of steps and improving productivity. In addition, the problem of n''a-3i peeling, which is one of the process defects that currently has a major impact on yield, is eliminated. ''Over-etching of the a-8i film is eliminated and the process becomes stable.

In addition, since the MoSi layer containing non-metal group elements (friend) is likely to peel off when subjected to heat treatment or electromagnetic wave irradiation treatment such as light, a MoSi layer containing no non-metal group elements is formed on top of it. Even if the MoSi layer is not peeled off even if heat treatment or electromagnetic wave irradiation treatment such as light is applied, Examples of the present invention will be described below with reference to the drawings.

(Example 1) The present invention relates to a connection between a wiring and a semiconductor layer in a semiconductor device using non-monocrystalline silicon, and will be explained below using TPT as an example. Even in the process cross-sectional view of LTFT, the process in Figure (a) is the gate electrode forming process, for example, Cr metal 2 is sputtered to form a 100%
This is a step in which OA deposited form 5ij, Cr is selectively etched with a solution containing cerium ammonium nitrate as a main component. The process shown in Fig. 4(b) is a three-layer debo process, for example,
The first SiN with a film thickness of 000A1500A/1000A
The x-layer 3, the substantially impurity-free a-3i layer 4 and again the second 5INX layer 5 are preferably successively deposited. All of these thin films are produced by plasma CD, in which a raw material gas containing SiH4 layer gas as a main component is synthesized by high-frequency glow discharge at a temperature of about 300°C. The step in the same figure (C) is the semiconductor layer protective film forming step, and
After selectively leaving the SiNx layer 5 of M only on the gate,
When forming oSi2 with a sputtering device, the pH is 37PH.
RF discharge was performed using a mixed gas with an I + Ar ratio of 0.01 to 0.50, and MoSi containing phosphorus was discharged.
26 to form 100A. Then, RF discharge is performed using only the elbow gas, and the MoSi27 is blown into a 100A shape. This two-layer MoSi layer is repeated five times in succession in the same vacuum.

The process shown in Figure (d) is the source/drain electrode forming process.
For example, 700 OA of A18, 9 is deposited on the entire surface by sputtering, the Al is selectively etched with a phosphoric acid solution, the formed Al pattern is used as a mask, and the MoSi2, a-3i layer is selectively etched with a fluoro-nitric acid solution. This is the process of engraving. Finally, heat treatment is performed. This allows Mo5ia to a
By diffusing P element into the -3i layer, P ions can be activated.

In this embodiment, if the metal layer 2 can be formed by using the sputtering method to form the Cr gate wiring in the process shown in FIG. a CVDa resistance heating method, etc. (1) Also, type of material (substances that do not diffuse into the semiconductor layer or insulator layer even if subjected to high temperature treatment)11 I
T O, MoSi2, MoTa, etc. are also applicable to the scope of the claims of the present invention. In addition, in this example, a MoSi2 film was formed by the RF discharge sputtering method in which PHs gas was mixed as a film containing nonmetallic elements.
Regardless of the vapor deposition method, even methods such as sputtering using a target containing a nonmetallic element, CVDa, ion shower method, etc. are acceptable.And as a film, MoSi
In addition to 2, if it is a substance whose main component is a high melting point metal (Ta, W, Cr, Ti, Co,
Any material may be used as long as it is a silicide of any one of Ni, Zr, Rh, Pd, and Pt, or a compound of high melting point metals. In addition, in this example, the MoSi2 film was deposited 5 times at a time less than 1 time, and even if the film is made of a substance whose main component is a high-melting point metal (the film may be deposited at any thickness and any number of times). In the example, the power exchange was subjected to heat treatment.
Electromagnetic wave irradiation treatment such as light may also be used; taking this example as an example, l;! : Force for diffusing P element from MoSi2 to a-3i layer＼ If P ions can be activated without diffusion, it is applicable to the claims of the present invention.

In addition, in this example, the force support using glass as the substrate may be any insulating substrate, and the insulating film may be SiN.
Force exchange using x layer Any insulating film with at least one layer or more may be used regardless of the type of material or deposition methodI,% In this example, a thin film transistor array using amorphous silicon is used. As long as there is a semiconductor device using a non-monocrystalline silicon film as described above, polycrystalline silicon or the like is also applicable to the claims of the present invention. lastly
In this example, AI is used as the conductive film. Any material may be used as long as it has at least one layer of conductor and covers the gap between the contact holes in the insulating film.
Since P element is taken as an example of a nonmetallic element, the claims of the present invention apply to any gas containing a nonmetallic element, such as It B2He (°C ( Example 2) A cross-sectional view of the process in Example 2 is shown in Figure 2.The force t, which is almost the same as the process in Example 1, and the process it PH in the same figure (C)
When performing RF discharge with a mixed gas of 3+ Ar, the ratio of PH37PH3+ Ar is set to 0.15 at the start of discharge, and the gas ratio of the mixed gas is changed over time so that it becomes 0.01 at the end of discharge. 20 MoSi2
0A Type Precept This MoSi2 layer 10 is repeated five times in a row in the same vacuum. In this example, a-3 containing no impurities
By increasing the concentration of P element at the interface between the i-layer and MoSi210, the connection resistance is lowered and at the same time Mo5ia 1
0 and A18. The interconnect resistance can be lowered by changing the P element concentration to O at the interface of 9.
Describe the gas concentration ratio as 0.15, and the force <, 0.
If the ratio is between 10 and 0.50, then in this example, a concentration gradient of non-metal group elements in the depth direction is formed in a material mainly composed of high-melting point metals.
Any semiconductor element having a structure in which an element concentration gradient is formed closer to the i-layer is applicable to the claims of the present invention.

In this way, the present invention reduces the number of times of film formation using the plasma CVD method, maintains the ohmic properties of the connection between the impurity-free a-3i layer and the metal wiring, and forms a barrier layer between the metal and the a-8i layer. This improves yield. Alternatively, the connection resistance between the jl a-3i layer and the metal wiring is lowered, the TPT array characteristics are improved, and the yield is improved.

Effects of the Invention The semiconductor devices manufactured by the manufacturing method according to the present invention (mainly, unlike the conventional TPT structure), when a TPT array using this structure is used in a liquid crystal display device, one of the causes of defects in the TPT array is This solves the problem of n″a-3i peeling and improves the yield. n′″a
Semiconductor element ζ that does not form a -3i film The CVD film forming process can be shortened while maintaining the ohmic properties of the connection between the a-3i layer, which does not contain impurities, and the metal wiring. It is possible to introduce Then, a concentration gradient of non-metal group elements is formed in the depth direction, or a concentration gradient of the element is formed as it approaches an aSi layer that does not contain impurities. A similar effect can be obtained.Finally, it can also be applied to an M○S structure that requires ohmic connection of semiconductor layers.

[Brief explanation of drawings]

Figure 1 shows the process cross section of TPT in Example 1 of the present invention.
The figure shows a process cross-section of TPT according to Example 2 of the present invention. FIG. 3 is a process cross-section of conventional TPT. 2.-Cr 3-.-first SiNx, 4...a
-8iJl? , I 5... second SiNx, 6...
・First MoSi2.7...P-doped second MoSi
2゜

Claims (4)

[Claims] (1) forming a non-single crystal silicon film on the substrate;
a step of forming a film containing a non-metal group element in a substance containing a high melting point metal as a main component on the film; a step of forming a film containing a high melting point metal as a main component on the film; A method for manufacturing a semiconductor device, comprising the steps of repeating two steps of forming a melting point metal at least once, and performing at least one of heat treatment and electromagnetic wave irradiation treatment after these steps. (2) A step of forming a film on an insulating material in which a concentration gradient of a non-metal group element is formed in a material mainly composed of a high-melting point metal, and a step of repeating the same step at least once on the film. and a step of forming a non-single crystal silicon film on the film, and at least one of heat treatment or electromagnetic wave irradiation treatment after the step, to remove non-single crystals near the substance whose main component is the high melting point metal. A method of manufacturing a semiconductor device, comprising a diffusion step of generating a concentration gradient of the non-metal group element in a crystalline silicon film. (3) Forming a film on an insulating material in which a non-metallic group element is contained in a substance containing a high melting point metal as a main component; and forming a film containing a high melting point metal as a main component on the film. a step of repeating the above two steps at least once; a step of forming a non-single crystal silicon film on the film; and a step of performing at least one of heat treatment or electromagnetic wave irradiation treatment after the step. 1. A method of manufacturing a semiconductor device, comprising a diffusion step of creating a concentration gradient of the non-metal group element in a non-single-crystal silicon film adjacent to a substance whose main component is a melting point metal. (4) Substances mainly composed of high melting point metals such as Mo, Ta, and W
, Cr, Ti, Co, Ni, Zr, Rh, Pd, Pt, or a compound of high melting point metals. A method of manufacturing the semiconductor device described above.