JPH0344964A - Protective device for cmos circuit - Google Patents

Abstract

PURPOSE:To prevent the breakdown of a circuit caused by the occurrence of latch-up by detecting an excessive earthing current with a current detecting means and intercepting a power source when the excessive earthing current flows in a CMOS circuit. CONSTITUTION:When a latch-up is generated in a system, a short-circuit state occurs between power source terminal VDD and an earthing terminal VSS of a CMOS circuit 1 and an excessive earthing current flows. Then, a current detecting means 3 operates to open a normally-close contact 3a and a power source V is intercepted, so that a breakdown of the circuit 1 is prevented and the safety is ensured. At this time in a protective means 5, the excessive earthing current brings a transistor TR1 in ON-state and subsequently on that, a transistor TR2 is brought in ON-state to energize an electromagnetic coil 3b of a means 3 and to operate it. Thus, a power source circuit 2 is disconnected from the power source V and breakdown of the circuit 1 can be prevented and safety of the circuit 1 is ensured, resulting in the improvement in reliability.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a 0MO8 (complementary metal oxide semiconductor) that detects a specific current due to the occurrence of latch-up and protects the circuit.
Related to circuit protection devices.

[Conventional technology and problems to be solved by the invention] In recent years, with the advancement of integrated circuit technology, a large proportion of ICs installed in electronic devices are of the MOS type with a high degree of integration. 0MO8-IC is NM
Due to its operating speed equal to or higher than O8-IC and its low power consumption, it has become indispensable in, for example, various control computer systems for automobiles and various small electronic devices.

However, the above-mentioned CMO8-IC has a troublesome problem in that latch-up phenomenon occurs, and when this latch-up occurs, not only does the electronic device equipped with the above-mentioned CMO8-IC malfunction, but in the worst case,
The above CMO8-IC is broken! i1! There is a risk of an accident occurring.

As is well known, the CMOS circuit is a P channel MO3-
A circuit in which a FET and an N-channel MO8-FET are connected in a complementary manner (see Figure 2). The latch-up phenomenon described above is also called the thyristor phenomenon, and is
The PI and N layers between each internal FET are combined to create a bipolar parasitic transistor circuit, and when a bias occurs that activates this parasitic transistor circuit, a current path different from that during normal operation is created. Latch-up occurs.

That is, for example, when a surge voltage v1 exceeding a certain limit is applied to the CMO8-IC and it breaks down, an excessive current flows between the power supply terminal VDD and the earth terminal V terminal, and this excessive current This continues even after the nerge voltage v1 disappears (see FIG. 3).

According to the above literature, the countermeasures against such latch-up are: 1. Connecting a series resistor to the input/output, 2. Connecting a diode to the input/output, 2. There are protection measures such as connecting a limiting resistor and 4τ.

However, all of the conventional protection measures are measures aimed at preventing the occurrence of latch-up, and cannot necessarily completely prevent the occurrence of latch-up.

Therefore, once a latch-up occurs, the excessive current caused by the latch-up continues, causing malfunction of the circuit, and if left untreated, the circuit will be destroyed.

[Object of the Invention] The present invention has been made in view of the above circumstances, and provides a CM that can prevent circuit destruction due to the occurrence of latch-up and keep the system safe from accidents caused by runaway.
The purpose is to provide a protection device for OS circuits.

[Means and effects for solving the problem] C according to the present invention
A protection device for MOS circuits prevents CM caused by latch-up.
current detection means for detecting excessive ground current in the OS circuit;
When the above current detection means detects an excessive earth current,
The device also includes protection means for cutting off power to the CMOS circuit.

That is, when latch-up occurs in the CMO-8 circuit, an excessive earth current flowing to the earth side of this CMOS circuit is detected by the current detection means, and at this time, the above-mentioned CMO
The power supply to the S circuit is immediately cut off by the protection means to protect the circuit.

“Embodiments of the invention” Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows one embodiment of the present invention, and is a block diagram of a protection device for a CMOS circuit.

(Configuration) In the figure, reference numeral 1 indicates a CMOS circuit consisting of 0MO8-IC, and the power input terminal VDD of this CMOS circuit 1 is connected to a power supply circuit 2, which is connected to the normally closed contact 3a of the relay 3. It is connected to the power supply (2) via the power supply (2), and supplies power to the CMOS circuit 1.

Further, the ground terminal VSS of the CMOS circuit 1 includes, for example, a resistor R1, a capacitor C1, and a transistor TR.
1, etc., is connected to the current detecting means 4, and a driving means 5a is connected to the current detecting means 4.

The drive means 5a and the relay 3 constitute a protection means 5, and when the current detection means 4 detects an excessive earth current due to latch-up, the protection means 5 immediately cuts off the power supply V'a. .

Further, the current detecting means 4 has a resistor R1 and a capacitor C connected in parallel between the ground terminal SS of the CMOS circuit 1 and the ground G, and further includes a resistor R1 and a capacitor C connected in parallel to the ground terminal V
The base of an NPN transistor TR1 is connected to SS.

Further, the driving means 5a is configured such that the collector of the transistor TR1 of the current detecting means 4 is connected to the base of a PNP transistor TR2 via a resistor R2, and the emitter of the transistor TR2 is connected to the power supply V. Furthermore, the collector of the transistor 11t2 is connected to the E41 coil 3b of the relay 3.

The CMOS circuit 1 is supplied with power by the power supply circuit 2, and when a predetermined signal is applied to its input terminal IN, it outputs a predetermined signal from its output terminal OUT.

(Function) Next, the function of the embodiment of the present invention having the above configuration will be explained.

(During normal operation) Under normal conditions, the relay 3 is OFF, and the power supply ■ is stabilized at a constant voltage in the power supply circuit 2 via the normally closed contact 3a, and is applied to the power supply terminal VDD of the CMOS circuit 1. rated voltage is applied.

When a signal is input to the input terminal IN of the CMOS circuit 1 and a dynamic operation is performed in which a predetermined signal is output from the output terminal OUT, a current flows from the ground terminal SS to the ground G via the resistor R1.

At this time, the current consumption of the CMOS circuit 1 is extremely small, and the current flowing from the ground terminal VSS generates a voltage sufficient to bias between the base and emitter of the NPN transistor TR1 connected to the ground terminal VSS. Does not occur.

That is, the transistors RH and 0FFI are connected to each other, and the current that accompanies the dynamic operation of the CMOS circuit 1 is absorbed by the capacitor C, thereby preventing malfunction of the transistor TR1.

Therefore, the resistor R2 is connected to the collector of the transistor TR1.
The PNP type transistor TR2 connected through the relay 3 is also kept in an OFF state, and the relay 3 is turned OFF and its normally closed contact 3a is always kept in a closed state.

(When latch-up occurs) For example, if a surge voltage occurs in the system,
When latch-up occurs in the CMOS circuit 1, the power terminal VD[l-ground terminal vSS of the CMOS circuit 1]
A short circuit occurs between them, and an excessive abnormal current flows from the ground terminal vSS to the ground G via the resistor R1.

Then, the base and emitter of the transistor TR1 are biased due to this excessive ground current, and the transistor TRI is turned on. Accordingly, the transistor TR2 is ONL, and the electromagnetic coil 3 of the relay 3
b is energized and operates, and the normally closed contact 3a is opened.

In other words, latch-up occurs and the CMOS circuit 1
When an excessive abnormal current flows from the earth terminal SS, the relay 3 is activated immediately, the normally closed contact 3a is opened, and the power supply V is cut off.

Thereby, even if latch-up should occur in the CMOS circuit 1, destruction of the circuit is prevented and safety is ensured.

Then, due to the power cutoff, the power supply terminal V of the CMOS circuit 1 is
When the short circuit between DD and ground terminal 988 is restored,
The transistor TR1 turns off, the transistor TR2 and the relay 3 turn off, the normally closed contact 3a returns to the closed state, and power is again supplied from the power supply via the power supply circuit 2 to the CMOS circuit 1. returns to normal operation.

[Effect between lights] As explained above, according to the present invention, there is provided a current detection means for detecting an excessive earth current of a CMOS circuit due to latch-up intervention, and when an excessive earth current is detected by the current detection means, Since the above-mentioned CMOS circuit is equipped with a protection means to cut off the power supply, latch-up occurs and the above-mentioned CMOS circuit is
If an excessive ground current flows through the S circuit, the power is immediately cut off to prevent the CMOS circuit from being destroyed.

Therefore, safety can be maintained by preventing the system from running out of control due to destruction of the CMOS circuit, and excellent effects such as improving the reliability of the product can be achieved.

[Brief explanation of drawings]

Fig. 1 shows an embodiment of the present invention, and Fig. 2 is an explanatory diagram of the CMOS circuit. Fig. 3 shows the correlation between voltage and current when latch-up occurs. It is a correlation diagram. 1...CMOS circuit 4...Current detection means 5...Protective means VDD...Power input terminal ■SS...Earth terminal U plan

Claims (1)

[Claims] Current detection means for detecting an excessive earth current in a CMOS circuit due to latch-up occurrence; when the current detection means detects an excessive earth current,
A protection device for a CMOS circuit, comprising a protection means for cutting off power to the CMOS circuit.