JPH0345187A - Motor rotation synchronization detecting circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a motor rotation synchronization detection circuit, for example,
The present invention relates to technology that is effective for use in semiconductor integrated circuits for motor drivers of hard disk memories and optical disk memories.

[Conventional technology]

The synchronization state is determined by inputting the integral value of the motor rotation speed error into the window comparator. In this manner, when the motor is at a desired rotational speed, read/write access to the hard disk memory or optical disk memory is enabled.

An example of a motor drive circuit equipped with a motor rotation synchronization detection circuit as described above is disclosed in Japanese Patent Laid-Open No. 61-218393.

[Problem to be solved by the invention]

In the above motor rotation synchronization detection circuit, if there are variations in the reference voltage of the window comparator due to element variations or power supply fluctuations, the detected synchronization range will vary, so there is a problem with detection accuracy. It cannot be used as is for devices that require highly accurate rotation synchronization detection, such as memory, and the synchronization judgment will differ depending on how the motor rotation speed error is integrated. A capacitor is required, and an external terminal is also required accordingly.

An object of the present invention is to provide a motor rotation synchronization detection circuit that reduces the number of external parts and achieves high accuracy.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a pair of pulse signals having a constant pulse width corresponding to the target rotation speed are formed in synchronization with the rise and fall of the motor rotation speed detection pulse, respectively, and input to the match/mismatch detection circuit, and the match is detected. A reference pulse having a constant pulse width is formed in synchronization with the front edge of the coincidence detection pulse formed by the /mismatch detection circuit, and the back edge of this reference pulse causes the -fi/non(() to be changed from the output pulse of the detection circuit. Form a synchronization detection signal according to the level.

[For production]

According to the above means, since synchronous detection is performed by digital signal processing, it is possible to eliminate external capacitors and external terminals for integration, and to obtain highly accurate detection outputs that are not affected by element variations or power supply fluctuations. .

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a motor rotation synchronization detection circuit according to the present invention.

Each circuit block in the figure is formed on a single semiconductor substrate together with a motor drive circuit and its rotation control circuit (not shown) using known semiconductor integrated circuit manufacturing techniques, although not particularly limited thereto.

In this embodiment, in order to detect motor rotation synchronization, an output signal of a speed discriminator circuit used for motor rotation control is used. That is, the speed discriminator circuit is composed of the following circuit. A pulse signal from an FC (frequency generation circuit) that changes depending on the rotational speed (number of rotations) of the motor is input to a T-shaped flip-flop circuit FFI. This flip-flop circuit FFI
The outputs Q and Q of are output from pulse generation circuits CPG1 and C, respectively.
Input to PG2. These pulse generation circuits CPCI
and CPG2 each generate a pulse signal synchronized with the rising edge of the input pulse.

The pulse signal P1 generated by the pulse generating circuit CPGI is supplied to the sent terminal S of the R3 type flip-flop circuit FF2. This flip-flop circuit F
The reset output Q of F2 is connected to the reset terminal RC of the counter circuit C0UNTI that counts the reference clock pulse CP.
is supplied to

This reference clock pulse CP is formed by a crystal oscillation circuit that uses a crystal resonator and has a highly accurate and stable frequency, although it is not particularly limited.

When the flip-flop circuit FF2 is clocked by the pulse signal P1, the counter circuit C0UNT1 is released from the reset state, so that the reference clock pulse CP
starts counting operation. This counter circuit C0UNTI
performs an N-bit counting operation, that is, the pulse width (half cycle) of the input pulse FG in a state where the motor reaches the target rotational speed is made equal to N times the number of reference clock pulses. Counter circuit C0UNTI, /l (When N reference clock pulses CP are formed, 1. The output Q is supplied to the reset R of the flip-flop circuit FF2, so the flip-flop circuit FF2 is reset. This flip-flop circuit FF2 The counter circuit C0UNTI is also reset by the reset output Q of the flip-flop circuit FF2, so that the reset output Q of the flip-flop circuit FF2 has a constant pulse width as described above.

Similarly to the above, the pulse signal P2 generated by the pulse generating circuit CPG2 is supplied to the set terminal S of the R3 type flip-flop circuit FF3. A reset output Q of this flip-flop circuit FF3 is supplied to a reset terminal RC of a counter circuit C0UNT2 that counts the reference clock pulse CP. The above counter circuit C0U
NT2 performs an N-bit counting operation in the same manner as described above, and its output signal Q resets the flip-flop circuit FF3. Thereby, the reset output Q of the flip-flop circuit FF3 is also made to have a constant pulse width as described above.

The above-mentioned pair of pulse signals are supplied to a phase comparison circuit PD (not shown), and the phase comparison output thereof is supplied to a loop filter to form a motor rotation control voltage.

In this embodiment, a pair of output pulses formed by the speed discriminator circuit described above is utilized to obtain a motor rotation synchronization detection signal.

The pair of pulses output from the reset outputs Q of the flip-flop circuits FF2 and FF3 is the negative number circuit ENOH.
is input. This minus number circuit ENOR operates as a match/mismatch detection circuit, and forms a high level output signal if both pulses are the same high level or low level, and forms a low level output pulse P3 if they do not match.

This output pulse P3 is generated by the pulse generating circuit C on the one hand.
Input to PG3. This pulse generation circuit CPG3 is
A pulse signal P4 is generated in synchronization with the rising edge of the input pulse P3. From this pulse signal P4, a reference pulse is formed by a circuit similar to the above. That is, the pulse signal P4 generated by the pulse generating circuit CPG3 is transmitted to the R3 type flip-flop circuit FF.
It is supplied to the set terminal S of No. 4. A reset output Q of this flip-flop circuit FF4 is supplied to a reset terminal RC of a counter circuit C0UNT3 that counts reference clock pulses CP. Therefore, the flip-flop circuit F
When F4 is set, the counter circuit C0UNT3 is released from the reset state, so the reference clock pulse C
Start counting P. This counter circuit C0UNT
3 performs an N-bit counting operation, that is, the constant time during which the motor is considered to have reached the target rotational speed is made equal to M times the number of reference clock pulses. The counter circuit C0UNT3 generates M reference clock pulses CP.
When the output Q is formed, the output Q is supplied to the reset R of the flip-flop circuit FF4, so that the flip-flop circuit FF4 is reset. Since the counter circuit C0UNT3 is also reset by the reset output Q of the flip-flop circuit FF4, the pulse outputted from the reset output Q of the flip-flop circuit FF4 is used as a reference pulse having a certain period of time as described above.

The reference pulse output from the reset output Q of the flip-flop circuit FF4 is the D-type flip-flop circuit F.
It is supplied to the input terminal T of F5.

The input terminal of this flip-flop circuit FF5 is supplied with the pulse signal P3 which is the above-mentioned -defeat/mismatch output. That is, the flip-flop circuit FF5 outputs a coincidence signal from its output Q in synchronization with the bank edge of the reference pulse.
A rotation synchronization detection output OUT corresponding to the level of the pulse signal P3, which is the mismatch output, is formed.

FIG. 2 shows a timing diagram for explaining an example of the operation of the motor rotation synchronization detection circuit.

By inputting the input pulse FC to the flip-flop circuit FFI, 1/2 of the phase opposite to each other is obtained from the outputs Q and Q.
A divided output can be obtained.

Pulse generating circuits CPCI and CPG2 form pulse signals P1 and P2 synchronized with the rising edges of their respective input pulses. Therefore, pulse signals Pl and P2 are generated alternately in synchronization with the rising edge of input pulse FC.

From these pulse signals P1 and P2, the flip-flop circuit FF2 and the counter circuit C0UNTI, the flip-flop circuit FF3 and the counter circuit C0UNT2,
Pulse Q (FF2) with constant pulse width as above
and Q(FF3) are formed.

Output pulse P3 of coincidence circuit ENOR that receives both the above signals
When the rotational speed of the motor is slower than the target rotational speed, the pulse width of the input pulse FC also increases, and the matching period corresponding to the reset state (high level) increases in proportion.

Furthermore, when the rotational speed of the motor is faster than the target rotational speed, the pulse width of the input pulse FC of the output pulse P3 becomes smaller, and the matching period corresponding to the cent state (low level) becomes longer in proportion. That is, when the rotational speed of the motor reaches the target rotational speed, the output pulse P3 does not generate the coincidence detection signal because the outputs Q of the flip-flop circuits FF2 and FF3 alternately become high and low levels. In reality, even when the target rotational speed is reached, whisker-like pulses P3 are formed.

With this timing, a reference pulse is formed from the reset output Q of the flip-flop circuit FF4 as described above.
The flip-flop circuit FF5 sets a time corresponding to the pulse width of the reference pulse as an allowable time, and the flip-flop circuit FF5 outputs a high-level asynchronous BC ready when the pulse signal P3, which is the match/mismatch detection signal, is at a high level. The signal OUT is formed, and if it is low level, the output signal OUT is in the low level synchronized state (long).
is formed.

The effects obtained from the above examples are as follows. That is, (1) Form a pair of pulse signals having a constant pulse width corresponding to the target rotation speed in synchronization with the rise and fall of the motor rotation speed detection pulse, respectively, and input them to the coincidence/mismatch detection circuit. , a reference pulse having a constant pulse width is formed in synchronization with the front edge of the coincidence detection pulse formed by this coincidence/mismatch detection circuit, and the output of the coincidence/mismatch detection circuit is generated by the bank edge of this reference pulse. A synchronization detection signal corresponding to the pulse level is formed. In this configuration, since synchronous detection is performed using digital signal processing, it is possible to eliminate external capacitors and external terminals for integration, and it is also possible to obtain highly accurate detection outputs that are not affected by element variations or power supply fluctuations. is obtained.

(2) By forming the above-mentioned pulse signal with a constant pulse width and reference pulse by counting highly accurate and highly stable reference clock pulses using a crystal oscillation circuit, it is possible to detect the rotation amount M with high accuracy and with high stability. You can get the effect of

(3) From (2) above, it is possible to achieve the effect of enabling highly accurate rotational synchronization detection that is also applicable to optical disk memories.

(4) By using FC waves as a signal corresponding to the rotational speed of the motor, the conventional index detection element (Hall element or optical element) is no longer necessary, and together with the reduction of external capacitors mentioned above, the circuit This has the effect of making it possible to simplify the process.

(5) By utilizing the output signal of the speed discriminator circuit used to control the rotational speed of the motor, it is possible to significantly simplify the circuit.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist thereof. For example, a circuit that forms a pair of pulse signals with a constant pulse width corresponding to a target rotation speed in synchronization with the rise and fall of a motor rotation speed detection pulse, or a circuit that forms a reference pulse. As for the specific configuration, various embodiments can be adopted, such as replacing the pulse generation circuit and the flip-flop circuit with an edge-trigger type flip-flop circuit. The circuit for forming the rotation synchronization detection signal from the reference pulse and the output pulse of the coincidence/mismatch detection circuit can be modified in various ways, such as by combining a gate circuit with a flip-flop circuit.

The motor rotation synchronization detection circuit of this embodiment is not only configured in the same semiconductor integrated circuit as the motor drive circuit and rotation speed control circuit, but also built in a control circuit such as an optical disk control circuit or a hard disk control W circuit. It may be something that

The present invention can be widely used as a motor rotation synchronization detection circuit in addition to optical disk memories, hard disk memories, etc.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a pair of pulse signals having a constant pulse width corresponding to the target rotation speed are formed in synchronization with the rise and fall of the motor rotation speed detection pulse, respectively, and input to the match/mismatch detection circuit, and the match is detected. A reference pulse having a constant pulse width is formed in synchronization with the front edge of the coincidence detection pulse formed by the coincidence detection circuit, and the level of the output pulse of the coincidence/mismatch detection circuit is changed by the front edge of the coincidence detection pulse. A synchronization detection signal corresponding to the synchronization detection signal is formed.

In this configuration, since synchronization detection is performed by digital signal processing, it is possible to eliminate an external capacitor for integration and an external terminal, and to obtain a highly accurate detection output that is not affected by element variations or electric B fluctuations.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a motor rotation synchronization detection circuit according to the present invention, and FIG. 2 is a timing chart for explaining an example of its operation. CPCI-CPG3...Pulse generation circuit, FFl...T
Type frimb flop circuit, FF2~FF4...R5 type 7
9717071 circuit, FF5...D type flip-flop circuit, Co(JNTI~C○UNT3...counter circuit, ENOR...matching circuit

Claims (1)

[Claims] 1. A first pulse signal that forms a pair of pulse signals having a constant pulse width corresponding to a target rotation speed in synchronization with the rise and fall of the motor rotation speed detection pulse, respectively.
a match/mismatch detection circuit that receives the pair of pulse signals, and forms a reference pulse having a constant pulse width in synchronization with the front edge of the match detection pulse formed by the match/mismatch detection circuit. , and a second circuit that forms a synchronization detection output signal according to the level of the output pulse of the coincidence/mismatch detection circuit according to the back edge of the reference pulse. 2. The output pulses from the pair of first circuits are input to a phase detection circuit, and the rotational speed of the motor is controlled based on the output signal thereof. The motor rotation synchronization detection circuit described in item 1. 3. The above-mentioned pair of pulse signals having a constant pulse width and the reference pulse are each constituted by a counter circuit that counts reference clock pulses, as set forth in claim 1 or 2. Motor rotation synchronization detection circuit.