JPH034541A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH034541A JPH034541A JP1140477A JP14047789A JPH034541A JP H034541 A JPH034541 A JP H034541A JP 1140477 A JP1140477 A JP 1140477A JP 14047789 A JP14047789 A JP 14047789A JP H034541 A JPH034541 A JP H034541A
- Authority
- JP
- Japan
- Prior art keywords
- elements
- wiring
- resin
- semiconductor element
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electronic Switches (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、各種電子機器に利用される半導体装置の製造
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing semiconductor devices used in various electronic devices.
従来の技術 従来の技術を第2図(a)〜(c)とともに説明する。Conventional technology The conventional technique will be explained with reference to FIGS. 2(a) to 2(c).
まず第2図(2L)に示すように、七うピンク、ガラス
。First, as shown in Figure 2 (2L), seven pink, glass.
ガラスエポキシ等によりなる配線基板1の導体配線2を
有する面に絶縁性樹脂5を塗布する。導体配線2はCr
−人U、ムl、Cu、i切等であり、絶縁性樹脂5は熱
硬化型又は紫外線硬化型のエポキシ。An insulating resin 5 is applied to a surface of a wiring board 1 made of glass epoxy or the like having conductor wiring 2. Conductor wiring 2 is Cr
- Insulating resin 5 is thermosetting or ultraviolet curing epoxy.
シリコーン、アクリル等である。次に第2図(b)に示
すように半導体素子3の突起電極4と導体配線2とを一
致させ、半導体素子3を加圧体6で加圧し、配線基板1
に押し当てる。突起電極4はムE。Silicone, acrylic, etc. Next, as shown in FIG. 2(b), the protruding electrodes 4 of the semiconductor element 3 and the conductor wiring 2 are aligned, the semiconductor element 3 is pressurized with the pressurizing body 6, and the wiring board 1 is
press against. The protruding electrode 4 is MuE.
ムu、Cu 等である。この時、導体配線2上の絶縁性
樹脂6は周囲に押し出され、半導体素子3の突起電極4
と導体配線2は電気的に接触する。次に半導体素子3を
加圧した状態で上部より紫外線7を照射することにより
、半導体素子3周縁の絶縁性樹脂6を硬化させ仮固定す
る。上記の方法で複数個の半導体素子3が仮固定された
配線基板1を第2図(C)に示すように、ナイロン、ポ
リプロピレン等からなる真空袋8内に入れ、真空包装し
、複数個の半導体素子3全てに大気圧による均等な圧力
を加える。この状態のまま加熱することによって絶縁性
樹脂5全体を硬化させ、その接着力により半導体素子3
の突起電極4と導体配線2との電気的接続と、半導体素
子3の機械的保持とが完了される。なお、真空包装後に
圧力容器等に入れ、大気圧以上もしくは以下の圧力を加
えることも可能である。Mu, Cu, etc. At this time, the insulating resin 6 on the conductor wiring 2 is pushed out to the periphery, and the protruding electrode 4 of the semiconductor element 3
and the conductor wiring 2 are in electrical contact with each other. Next, by irradiating ultraviolet rays 7 from above while the semiconductor element 3 is pressurized, the insulating resin 6 around the semiconductor element 3 is cured and temporarily fixed. As shown in FIG. 2(C), the wiring board 1 on which a plurality of semiconductor elements 3 are temporarily fixed by the above method is placed in a vacuum bag 8 made of nylon, polypropylene, etc., vacuum-packed, and a plurality of semiconductor elements 3 are temporarily fixed. Uniform atmospheric pressure is applied to all semiconductor elements 3. By heating the insulating resin 5 in this state, the entire insulating resin 5 is cured, and the semiconductor element 3 is
The electrical connection between the protruding electrode 4 and the conductor wiring 2 and the mechanical holding of the semiconductor element 3 are completed. Note that it is also possible to place the product in a pressure container or the like after vacuum packaging and apply pressure above or below atmospheric pressure.
発明が解決しようとする課題
以上のように従来の技術では、半導体素子3と真空袋8
が直接接触している為、前記半導体素子3を、前記真空
袋8から取り外す際に発生する静電気により、前記半導
体素子3が静電破壊することがあった。Problems to be Solved by the Invention As described above, in the conventional technology, the semiconductor element 3 and the vacuum bag 8
Since they are in direct contact with each other, the semiconductor element 3 may be damaged by static electricity generated when the semiconductor element 3 is removed from the vacuum bag 8.
課題を解決するだめの手段
本発明は、真空袋の内面に帯電防止体を設けたものであ
る。Means for Solving the Problems According to the present invention, an antistatic body is provided on the inner surface of a vacuum bag.
作用
上記方法により、真空袋から半導体素子を取り外す際に
発生する静電気を防止し、半導体素子の静電破壊を未然
に防ぐことが出来るものである。Effect: The above method prevents static electricity generated when a semiconductor element is removed from a vacuum bag, thereby preventing electrostatic damage to the semiconductor element.
実施例 本発明の一実施例を第1図とともに説明する。Example An embodiment of the present invention will be described with reference to FIG.
まず第1図(2L)に示す様に、セラミック、ガラス。First, as shown in Figure 1 (2L), ceramic and glass.
エポキシ等よシなる配線基板11の半導体素子13を固
着する部分に導体配線12上をも含んでエポキシ、シリ
コーン、アクリル等よりなる絶縁性樹脂15を塗布すZ
・、1導体配線12はCr A u 、Aa l1t
o等よりなる。An insulating resin 15 made of epoxy, silicone, acrylic, etc. is applied to the portion of the wiring board 11 made of epoxy or the like to which the semiconductor element 13 is fixed, including on the conductor wiring 12.
・, 1 conductor wiring 12 is Cr A u , Aa l1t
It consists of o, etc.
次に第1図(′b)に示すように、半導体素子13の突
起電極14と、導体配線12を一致させ半導体素子13
を配線基板11に加圧圧16により加圧する。突起電極
14はJJ、Au、Cu等である。この時、導体配線プ
2上の絶縁性樹脂15は周囲に押し出され、上部より紫
外線17を照射することによって半導体素子13の周縁
部の絶縁性樹脂15を硬化させ、仮固定する。上記の方
法で複数個の半導体素子13が仮固定きれた配線基板1
1を、第1図(C)に示すように、内側に帯電防止機能
を備えた帯電防止層19を塗った真空袋18内に入れ、
真空包装する。この状態のまま加熱することによって、
絶縁性樹脂15全体を硬化させ、その接着力により、半
導体素子13の突起電極14と、導体配線12との電気
的接続と、半導体素子13の機械的保持が完了さt、且
つ前記半導体素子13を真空袋18から取シ出す際に、
静電気の発生がなく、前記半導体素子13を静電破壊す
ることがなくなる。Next, as shown in FIG. 1('b), the protruding electrode 14 of the semiconductor element 13 and the conductor wiring 12 are aligned, and the semiconductor element 13 is
is applied to the wiring board 11 by a pressure 16. The protruding electrode 14 is made of JJ, Au, Cu, or the like. At this time, the insulating resin 15 on the conductor wiring board 2 is pushed out to the periphery, and by irradiating ultraviolet rays 17 from above, the insulating resin 15 at the peripheral edge of the semiconductor element 13 is hardened and temporarily fixed. Wiring board 1 on which a plurality of semiconductor elements 13 have been temporarily fixed by the above method
1 into a vacuum bag 18 coated with an antistatic layer 19 having an antistatic function on the inside, as shown in FIG. 1(C).
Vacuum package. By heating in this state,
The entire insulating resin 15 is cured, and its adhesive strength completes the electrical connection between the protruding electrodes 14 of the semiconductor element 13 and the conductor wiring 12, and the mechanical holding of the semiconductor element 13. When taking out from the vacuum bag 18,
There is no generation of static electricity, and the semiconductor element 13 is prevented from being damaged by static electricity.
発明の効果 本発明の効果を以下に示す。Effect of the invention The effects of the present invention are shown below.
すなわち本発明によれば、真空袋から半導体素子を取り
外す際に、静電気が発生することがなくなるので、半導
体素子の静電破壊を防ぐことが出来る。That is, according to the present invention, static electricity is not generated when a semiconductor element is removed from a vacuum bag, so that electrostatic damage to the semiconductor element can be prevented.
第1図(a)〜(C)は、本発明の半導体装置の製造方
法の一実施例を示す各工程の断面図、第2図(2L)〜
(C)は従来の技術を示す各工程の断面図である。
11・・・・・・配線基板、12・・・・・・導体配線
、13・・・・・・半導体素子、14・・・・・・突起
電極、15・・・・・・絶縁性樹脂、16・・・・・・
加圧体、17・・・・・・紫外線、18・・・・・・真
空袋、19・・・・・・帯電防止層。FIGS. 1(a) to (C) are cross-sectional views of each process showing an embodiment of the method for manufacturing a semiconductor device of the present invention, and FIGS. 2(2L) to
(C) is a cross-sectional view of each process showing a conventional technique. 11... Wiring board, 12... Conductor wiring, 13... Semiconductor element, 14... Projection electrode, 15... Insulating resin , 16...
Pressure body, 17... Ultraviolet rays, 18... Vacuum bag, 19... Antistatic layer.
Claims (1)
体素子を接着したものを、内面に帯電防止体を設けた真
空袋内に収納させ、気圧を用い前記半導体素子と配線基
板を加圧した状態で前記絶縁性樹脂の硬化させる半導体
装置の製造方法。A semiconductor element was bonded with an insulating resin onto a wiring board having conductor wiring, and the semiconductor element and wiring board were placed in a vacuum bag with an antistatic material on the inside, and the semiconductor element and wiring board were pressurized using air pressure. A method for manufacturing a semiconductor device, comprising curing the insulating resin in a state in which the insulating resin is cured.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1140477A JPH034541A (en) | 1989-06-01 | 1989-06-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1140477A JPH034541A (en) | 1989-06-01 | 1989-06-01 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH034541A true JPH034541A (en) | 1991-01-10 |
Family
ID=15269518
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1140477A Pending JPH034541A (en) | 1989-06-01 | 1989-06-01 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH034541A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5578518A (en) * | 1993-12-20 | 1996-11-26 | Kabushiki Kaisha Toshiba | Method of manufacturing a trench isolation having round corners |
-
1989
- 1989-06-01 JP JP1140477A patent/JPH034541A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5578518A (en) * | 1993-12-20 | 1996-11-26 | Kabushiki Kaisha Toshiba | Method of manufacturing a trench isolation having round corners |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6048420A (en) | Method for surface mounting electrical components to a substrate | |
| MY123366A (en) | Semiconductor device and its manufacturing method | |
| KR100417553B1 (en) | Curing method and apparatus for flip chip device with epoxy resin | |
| CA2122278A1 (en) | Adhesive sheet for wafer and process for preparing semiconductor apparatus using the same | |
| US20040171192A1 (en) | Semiconductor integrated circuit card manufacturing method, and semiconductor integrated circuit card | |
| JPH10125825A (en) | Seal structure of chip device and method of sealing the same | |
| JPH034541A (en) | Manufacture of semiconductor device | |
| JPH01199440A (en) | Manufacture of semiconductor device | |
| JPH02122531A (en) | Device for mounting electronic component | |
| JPH0558660B2 (en) | ||
| JPS5737839A (en) | Manufacture of hybrid integrated circuit | |
| EP0736225A1 (en) | Method of attaching integrated circuit dies by rolling adhesives onto semiconductor wafers | |
| JPH0244742A (en) | Manufacture of semiconductor device | |
| EP1387398A3 (en) | Method and adhesive for a Flip Chip assembly | |
| JPS62252946A (en) | Manufacture of semiconductor device | |
| JPS6059105B2 (en) | Manufacturing method of electrostatic adsorption device | |
| JPH04254343A (en) | Packaging method of semiconductor device | |
| JP2841846B2 (en) | IC semiconductor element bonding method | |
| JPH0718566Y2 (en) | Taping device | |
| JPS5471980A (en) | Adhesion method of semiconductor wafer to lapping surface plate | |
| JPS5669846A (en) | Sealing method of package | |
| JPH03145792A (en) | leadless parts | |
| JPH03174743A (en) | Semiconductor device | |
| KR920000610B1 (en) | A preparing method for the material sticker of which indurance is developed | |
| JPH10256285A (en) | Method and apparatus for manufacturing substrate with sealing frame for semiconductor package |