JPH0345554B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a MOS transistor, and an object of the present invention is to protect a gate insulating film from hydrogen plasma bombardment and obtain a MOS transistor with a high figure of merit.

Amorphous silicon, which contains a few percent of hydrogen in its composition to compensate for imperfections in atomic bonding pairs, has attracted attention as a solar cell because it can be formed at low temperatures and can be easily made into a large area. ing. However, compared to single-crystal silicon, the free electron mobility is 0.1 to 1 cm ² /V.sec, which is more than three orders of magnitude smaller, so a transistor with excellent performance cannot be obtained as when single-crystal silicon is used. Even so, image display devices can be constructed by combining them with liquid crystal cells that do not require high-speed operation or large currents, for example.
It is possible to obtain switching arrays of MOS type transistors.

FIGS. 1 and 2 are cross-sectional views of conventional amorphous silicon MOS transistors developed for such uses. First, in FIG. 1, 1 is an insulating substrate, for example a glass plate, and 2 is a first metal layer that becomes a gate electrode. 3 is the gate insulating film made of SiO ₂
Alternatively, materials such as Si ₃ N ₄ are deposited by thermal decomposition using plasma deposition or CVD (chemical vapor deposition). 4 is an amorphous silicon layer whose thickness is selected to be 2000 to 5000 Å;
No addition of impurities is necessary. Reference numerals 5 and 6 denote second metal layers serving as source/drain electrodes, which are deposited so as to partially overlap gate 2 to avoid an offset gate structure.

The second metal layer 5, 6 must form an ohmic contact with the amorphous silicon layer 4, and its material is
Limited to Al, Ni-Cr alloys, etc. The first metal layer 2 is an amorphous silicon MOS due to the difference in work function.
Although there is a change in the threshold value V _T of the type transistor, the restrictions are loose, and of course the same material as the second metal layers 5 and 6 can be used. It is sufficient that the first and second metal layers have a thickness of 2000 Å or more.

The conventional MOS type transistor having the above structure has the following drawbacks, and the hydrogenated amorphous silicon layer 4 is generally deposited by glow discharge or arc discharge of a silane-based gas such as silane or disilane. It is true. In some cases, it is also possible to deposit silicon by sputtering silicon by mixing hydrogen gas with argon gas, but in all of these deposition methods, a large amount of hydrogen plasma exists in the reaction chamber, and the gate It is unavoidable that the insulating film 3 is exposed to hydrogen plasma bombardment. Hydrogen plasma has a strong reducing effect, and the composition ratio of the gate insulating film fluctuates, vacancies are formed, and fixed charges are generated.
It becomes difficult to control the threshold voltage V _T of the MOS transistor. When the hydrogen plasma bombardment is severe, it is not uncommon for pinholes to be formed in the gate insulating film 3, significantly lowering the yield. In order to suppress the generation of pinholes, the thickness of the gate insulating film 3 may be increased, for example, 5000 Å. This will reduce the mutual conductance of the MOS transistor, which is a fatal constraint for amorphous silicon, which has low mobility.

As is clear from the structure of the conventional MOS transistor shown in FIG. 2, since the gate insulating film 3 is deposited after the island-shaped amorphous silicon layer 4 is formed, it is susceptible to hydrogen plasma bombardment. There isn't. However, in order to avoid a phenomenon in which hydrogen is released from the amorphous silicon layer 4 during the deposition of the gate insulating film 3 and the film quality of the amorphous silicon layer 4 deteriorates, the temperature during deposition must be kept at 300° C. or lower. A gate insulating film formed at such a low temperature has an unstable reaction and cannot escape fluctuations in composition ratio. In addition, in the structure of the MOS type transistor shown in Fig. 1, it is possible to heat the insulating substrate 1 to the softening point of the insulating substrate 1, for example, 600°C in the case of a glass plate, during the deposition or post-deposition heat treatment, so there is clearly little variation in the composition ratio. However, as mentioned above, the composition ratio changes due to the impact of hydrogen plasma.

In this way, in the conventional manufacturing method of MOS type transistors, it is extremely difficult to control the threshold voltage V _T of amorphous silicon MOS type transistors because it includes a factor that changes the composition ratio of the gate insulating film. It was hot.

The present invention was made to eliminate such conventional drawbacks, and the key point thereof is the introduction of a protective film to avoid hydrogen plasma bombardment. The manufacturing method will be explained.

Incidentally, in FIG. 3, the same parts as those showing the conventional example are given the same numbers.

As shown in FIG. 3, after selectively depositing a first metal layer 2 that will become a gate electrode on an insulating substrate 1, a gate insulating film 3 is deposited over the entire surface. The deposition method is as described above, and the film thickness may be about 1000 Å. Preferably, the amorphous silicon layer 4 is formed after the quality of the gate insulating film is improved by heating the insulating substrate 1 to its softening point.
A and 4b are deposited. The amorphous silicon layer is deposited by glow discharge decomposition or arc discharge decomposition of silane gas using hydrogen gas plasma. Silicon may be sputter-deposited using a sputter gas made by adding hydrogen gas to argon or the like. For glow discharges, e.g. He-based 20
Using % _SiH4 gas, pressure 1Torr, flow rate 300SCCM
When the high frequency power density is 40 mw/ ^cm2, the deposition rate is 1~
2 Å/sec is obtained. From the start of deposition until the amorphous silicon layer grows to about 100 to 500 Å, the discharge power is reduced to about 1/10 to form the first amorphous silicon layer 4a, and then the deposition is performed under the above conditions. The deposition is continued to obtain a second amorphous silicon layer 4b having a thickness of 2000 to 5000 Å. Thereafter, the first and second amorphous silicon layers are left in the form of islands 4, and source/drain electrodes 5 and 6 made of the second metal layer are selectively covered on the island-like amorphous silicon layers 4. The amorphous silicon MOS transistor is completed.

Now, if we consider the difference between the conventional method of manufacturing a MOS transistor shown in FIG. 1 and the method of manufacturing a MOS transistor according to the present invention shown in FIG. The method is characterized in that when depositing the amorphous silicon layer 4a, the discharge power is lowered to reduce the density and acceleration energy of the hydrogen plasma. The first amorphous silicon layer 4a, which contains almost no hydrogen, serves as a protective film to protect the gate insulating film 3 from hydrogen gas plasma bombardment during the deposition of the second amorphous silicon layer 4b, which contains a large amount of hydrogen plasma in the reaction atmosphere. It is protected and partially hydrogenated. Therefore, it became possible to form a homogeneous amorphous silicon layer 4 without deteriorating the gate insulating film 3. This has a particularly remarkable effect when a large amount of hydrogen gas is added to microcrystallize the amorphous silicon layer in order to increase the mobility of the amorphous silicon layer. This is because in this case, the discharge power is also increased to perform deposition, so the density and activation power of the hydrogen gas plasma become extremely strong.

In addition, in the manufacturing method of the MOS transistor shown in FIG. 1, there is also a method in which the amorphous silicon layer 4 is deposited by CVD or vacuum evaporation and then hydrogenated by hydrogen plasma treatment to improve the film quality. Are known. However, in this method, hydrogen is formed by decreasing exponentially from the surface.
The bottom part, which constitutes the channel of the MOS transistor,
In other words, it is not possible to reduce the local level density near the interface with the gate insulating film, resulting in hysteresis in the transistor characteristics, so even if a high-quality gate insulating film 3 can be obtained, it is still impractical. There are drawbacks.

As described above, in the method for manufacturing a MOS transistor of the present invention, fluctuations in the composition ratio and destruction of the gate insulating film are suppressed, thereby improving mutual conductance, uniformity of threshold voltage V _T , and improving yield. Excellent effects can be obtained.

[Brief explanation of drawings]

1 and 2 are cross-sectional views for explaining a conventional method of manufacturing a MOS transistor, and FIG. 3 is a cross-sectional view for explaining a method of manufacturing a MOS transistor according to an embodiment of the present invention. . 1... Insulating substrate, 2... Gate electrode, 3...
Gate insulating film, 4...Amorphous silicon layer, 5, 6
...Source/drain electrode.

Claims (1)

[Claims] 1. A step of selectively forming a first metal layer as a gate electrode on an insulating substrate, a step of forming an insulating film on the first metal layer, and glow discharge decomposition or arc discharge of silane-based gas. In selectively forming an amorphous silicon layer on the insulating film by decomposition or sputtering silicon using gas added with hydrogen gas, the discharge power of the glow discharge, arc discharge or sputtering a process of forming a film by step-like discharge in which the initial stage of the discharge is small and the subsequent discharge period is large; and a source/drain layer is formed on the amorphous silicon layer so as to overlap with the first metal layer. 1. A method for manufacturing a MOS transistor, comprising the step of selectively forming a second metal layer as an electrode.