JPH0346201A - Semiconductor porcelain possessing positive resistance-temperature characteristic - Google Patents

Semiconductor porcelain possessing positive resistance-temperature characteristic

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Publication number
JPH0346201A
JPH0346201A JP18133789A JP18133789A JPH0346201A JP H0346201 A JPH0346201 A JP H0346201A JP 18133789 A JP18133789 A JP 18133789A JP 18133789 A JP18133789 A JP 18133789A JP H0346201 A JPH0346201 A JP H0346201A
Authority
JP
Japan
Prior art keywords
resistance
curie point
inner layer
ceramic
semiconductor porcelain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18133789A
Other languages
Japanese (ja)
Inventor
Yutaka Shimabara
豊 島原
Yasunobu Yoneda
康信 米田
Yukio Sakabe
行雄 坂部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP18133789A priority Critical patent/JPH0346201A/en
Publication of JPH0346201A publication Critical patent/JPH0346201A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To avoid the destruction of an element when voltage is applied suddenly by a method wherein the Curie point, to be transferred to a high resistance element from a low resistance element, is set in such a manner that it becomes higher as going into the inner part and it becomes lower as going to the outer part. CONSTITUTION:The inner layer 2 of high Curie point is laminated by pinching it with the outer layers 3 and 3 having low Curie point in such a manner that the Curie point becomes higher as going into the inner part from outside part of a semiconductor porcelain. Accordingly, even when heat is generated when a current is limited, the resistance of the inner layer 2 can be made equal to or lower than the resistance of the outer layers 3. To be more precise, the resistance of the inner layer is liable to abnormal increase of resistance due to the fact that heat is hardly generated there, and its temperature rises easily, but the increase of resistance can be suppressed by constituting the inner layer with a high Curie point material. As a result, the thermal stress breakdown due to the difference in temperature distribution of a ceramic element and especially the destruction of the element due to sudden application of voltage can be avoided.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、例えばモーター起動に用いられる正の抵抗温
度特性ををする半導体磁器電子部品に関し、特に急激な
電圧を印加したときの熱応力破壊を回避できるようにし
た素子の構造に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor ceramic electronic component having a positive resistance-temperature characteristic used, for example, for starting a motor, and particularly relates to a semiconductor ceramic electronic component that is used for starting a motor and has a thermal stress fracture when a sudden voltage is applied. The present invention relates to an element structure that avoids this.

〔従来の技術〕[Conventional technology]

一般に、BaTloiに微量の不純物と添加物とを混合
することにより正の抵抗温度特性を示す半導体磁器が知
られており、従来、例えば第4図に示すような構造のも
のがある。この半導体磁器10は、円板状のセラミクス
素子11の両主面に電極12を形威し、該電極12にリ
ード線13を接続して構成されている。この半導体磁器
10は、例えば温度検知、温度制御、温度補償、定温度
発熱体、過電流保護、雰囲気検知、モーター起動。
Generally, semiconductor porcelain is known which exhibits positive resistance-temperature characteristics by mixing small amounts of impurities and additives with BaTloi, and conventionally there is a structure as shown in FIG. 4, for example. This semiconductor ceramic 10 is constructed by forming electrodes 12 on both main surfaces of a disk-shaped ceramic element 11, and connecting lead wires 13 to the electrodes 12. This semiconductor porcelain 10 is capable of, for example, temperature detection, temperature control, temperature compensation, constant temperature heating element, overcurrent protection, atmosphere detection, and motor starting.

あるいは自動消磁回路等に使用されている6例えばモー
ター起動回路においてはモーターの起動を行うために、
まず大きな交流電流を印加し、モーターが動きだした後
は電流を徐々に減衰させる機能を持たせる必要があり、
このモーター起動回路に上記半導体磁器lOが採用され
る。即ち、上記半導体磁器10は、電流印加開始時には
大きな電流を流し、時間の経過とともにセラミクス素子
11の発熱により抵抗値が増加することにより電流を制
限し減衰させるという機能を有しており、これにより単
一素子でモーター起動回路を形成できる。このような用
途に採用されるため、上記率。
Or, for example, in a motor starting circuit used in an automatic degaussing circuit, etc., in order to start the motor,
It is necessary to have a function that first applies a large alternating current and then gradually attenuates the current after the motor starts moving.
The above semiconductor ceramic lO is employed in this motor starting circuit. That is, the semiconductor ceramic 10 has the function of passing a large current at the start of current application, and limiting and attenuating the current by increasing the resistance value over time due to heat generation of the ceramic element 11. A motor starting circuit can be formed with a single element. The above rate is adopted because it is used for such purposes.

体磁器10には低抵抗かつ耐電圧が要求され、特に急激
な電圧印加に対する耐電圧が要求される。
The body ceramic 10 is required to have low resistance and withstand voltage, and in particular, is required to withstand voltage against sudden voltage application.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、上記従来の半導体磁器10は、急激な電
圧印加によりセラミクス素子11が破壊し易いという問
題点がある。これは、上記セラミクス素子11が単一材
料で構成されていることから、1!流制限の際の発熱時
に素子11の内部11a (楕円状に示した部分)と外
部11bとで温度分布に差ができる。つまり外部11b
は大気と接触しているため熱拡散が速く温度は比較的低
く抵抗も小さくなるが、内部11aは放熱が遅いことか
ら外部11bに比べて高抵抗となり、その結果内部11
aの方が外部に比べて速く熱応力破壊が起こるからであ
る。特に急激な電圧印加時には内部11aと外部11b
との熱平衡の速度差が大きいため破壊が起こり易い。
However, the conventional semiconductor ceramic 10 described above has a problem in that the ceramic element 11 is easily destroyed by sudden voltage application. This is because the ceramic element 11 is made of a single material, so 1! When heat is generated during flow restriction, there is a difference in temperature distribution between the inside 11a (the elliptical portion) and the outside 11b of the element 11. In other words, external 11b
Since the inside 11a is in contact with the atmosphere, heat diffusion is fast, the temperature is relatively low, and the resistance is small. However, since heat dissipation is slow in the inside 11a, the resistance is higher than that of the outside 11b, and as a result, the inside 11a
This is because thermal stress fracture occurs faster in a than in the outside. Especially when a sudden voltage is applied, the internal 11a and external 11b
Destruction is likely to occur because there is a large difference in the rate of thermal equilibrium between the two.

本発明は上記従来の状況に鑑みてなされたもので、セラ
ミクス素子の温度分布の差による熱応力破壊、特に急激
な電圧印加時の破壊を回避できる半導体磁器電子部品を
提供することを目的としている。
The present invention has been made in view of the above-mentioned conventional situation, and an object of the present invention is to provide a semiconductor ceramic electronic component that can avoid thermal stress destruction due to differences in temperature distribution of ceramic elements, particularly destruction when a sudden voltage is applied. .

c問題点を解決するための手段〕 本件発明者らは、セラミクス素子の発熱時における内部
の抵抗値を、放熱しに<<温度上昇し易いにもかかわら
ず、外部の抵抗値と同じかあるいはそれより低くできれ
ば熱応力破壊を回避できることに想到し、本発明を成し
たものである。
Means for Solving Problem c] The present inventors have determined that the internal resistance value of the ceramic element when it generates heat is equal to or equal to the external resistance value, even though the temperature tends to rise due to heat dissipation. The present invention was developed based on the idea that thermal stress fracture could be avoided if the temperature could be lowered.

そこで本願第1項の発明は、正の抵抗温度特性を有する
半導体磁器において、外部に対して内部ほど高キュリー
点を有する材料で、即ち、より高温で高抵抗になる材料
で構成したことを特徴としている。また第2項の発明は
、高キュリー点のセラミクス材料からなる内層の両面に
、低キュリー点のセラミクス材料からなる外層を積層し
、これを一体焼結してなることを特徴としている。
Therefore, the invention of item 1 of the present application is characterized in that semiconductor porcelain having positive resistance-temperature characteristics is made of a material whose Curie point is higher on the inside than on the outside, that is, with a material that becomes higher in resistance at higher temperatures. It is said that The second aspect of the invention is characterized in that an outer layer made of a ceramic material having a low Curie point is laminated on both sides of an inner layer made of a ceramic material having a high Curie point, and these are integrally sintered.

ここで、本発明の半導体磁器は、低抵抗体から高抵抗体
に転移するキュリー点を内部ほど高く、外部ほど低く設
定する点を特徴としているが、具体的には第2項の発明
のように、キュリー点の異なる内層1両外層からなる少
なくとも3層構造を採用することにより実現できる。こ
の場合、本発明は勿論この3層構造に限られるものでは
なく、3層以上の多層構造とした場合も含まれ、この多
層構造にした場合でも、各層のキュリー点を外層ほど低
くなるように設定すればよい。
Here, the semiconductor porcelain of the present invention is characterized in that the Curie point, which transitions from a low-resistance element to a high-resistance element, is set higher on the inside and lower on the outside. This can be realized by adopting at least a three-layer structure consisting of an inner layer and an outer layer having different Curie points. In this case, the present invention is of course not limited to this three-layer structure, but also includes a multi-layer structure of three or more layers. Just set it.

〔作用〕[Effect]

本発明に係る半導体磁器によれば、半導体磁器の外部か
ら内部に行くほど高キュリー点になるようにしたので、
即ち、具体的には高キュリー点の内層を低キュリー点の
外層で挟んで積層化したので、電流制限の際の発熱が生
じても内層の抵抗を外層の抵抗と同じか、又は低くする
ことができる。
According to the semiconductor porcelain according to the present invention, since the Curie point increases from the outside to the inside of the semiconductor porcelain,
Specifically, since the inner layer with a high Curie point is sandwiched between the outer layers with a low Curie point and is laminated, the resistance of the inner layer can be made equal to or lower than the resistance of the outer layer even if heat is generated during current limitation. I can do it.

即ち、内層は放熱しにくく温度上昇し易いことから、そ
の抵抗が異常に上昇し易いが、高キュリー点材料で構成
したことにより、抵抗の上昇を抑制でき、その結果急激
な電圧印加による素子の破壊を回避できる。
In other words, since the inner layer is difficult to dissipate heat and easily rises in temperature, its resistance tends to rise abnormally. However, by being made of a material with a high Curie point, the rise in resistance can be suppressed, and as a result, the resistance of the element due to sudden voltage application can be suppressed. Destruction can be avoided.

〔実施例〕〔Example〕

以下本発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図ないし第3図は本発明の一実施例による半導体磁
器を説明するための図である。
FIGS. 1 to 3 are diagrams for explaining semiconductor ceramics according to an embodiment of the present invention.

図において、1は正の抵抗温度特性を有する半導体磁器
であり、これは矩形板状の内層2と該内層2を挟んで対
向する同じく矩形板状の一対の外層3.3とを積層し、
これを一体焼結してなるセラミクス素子4の両主面の中
央部分に電極5.5を形成するとともに、該各電極5に
リード線6を接続してtitcされている。
In the figure, 1 is a semiconductor ceramic having positive resistance-temperature characteristics, which is made by laminating a rectangular plate-shaped inner layer 2 and a pair of rectangular plate-shaped outer layers 3.3 facing each other with the inner layer 2 in between.
Electrodes 5.5 are formed at the center of both main surfaces of the ceramic element 4 which is integrally sintered, and lead wires 6 are connected to each electrode 5 for titc.

上記内層2は、キュリー温度が、例えば65℃のセラミ
クス材料からなり、また上記外層3はキュリー温度が、
例えば115℃のセラ【クス材料により構成されている
The inner layer 2 is made of a ceramic material having a Curie temperature of, for example, 65°C, and the outer layer 3 has a Curie temperature of, for example, 65°C.
For example, it is made of ceramic material at a temperature of 115°C.

次に本実施例の半導体磁器lの製造方法について説明す
る。
Next, a method for manufacturing the semiconductor ceramic l of this example will be explained.

1、まず、チタン酸バリウム74mo 1%、チタン酸
ストロンチウム24゜95mo1%に対して、半導体化
剤として酸化イツトリウム0.05−01%を混合し、
これに鉱化剤としてS i Ot O,5wt%を添加
し、さらに特性改善剤としてMn0xO,2wt%を添
加して混合粉砕し、1000℃×2時間で仮焼成する。
1. First, 0.05-01% of yttrium oxide was mixed as a semiconducting agent with 1% of barium titanate 74mo1% and strontium titanate 24°95mo1%,
To this, 5 wt% of SiOtO is added as a mineralizing agent, and 2 wt% of Mn0xO is added as a property improving agent, mixed and pulverized, and calcined at 1000° C. for 2 hours.

次に、この仮焼成した材料を再び粉砕し、これに酢酸ビ
ニル系バインダー、及び分散剤を混合して厚さ1.5 
snのグリーンシートを形成する。これによりキュリー
点115℃の外層3が形成される。
Next, this pre-fired material is crushed again, and a vinyl acetate binder and a dispersant are mixed therein to give a thickness of 1.5 mm.
A green sheet of sn is formed. As a result, an outer layer 3 having a Curie point of 115° C. is formed.

ii、一方、チタン酸バリウム91mo 1%、チタン
酸ストロンチウム2.95moj!%対して、半導体化
剤として酸化イツトリウム0.05−01%、これに鉱
化剤としてS i O! 0.3 wL%、Af!○s
 O,2wt%。
ii, while barium titanate 91 mo 1%, strontium titanate 2.95 moj! %, 0.05-01% yttrium oxide as a semiconducting agent, and S i O! as a mineralizing agent. 0.3 wL%, Af! ○s
O, 2wt%.

特性改善剤としてM n Ot O,2wt%を添加し
て混合粉砕し、1000℃×2時間で仮焼成する0次に
、この仮焼成した材料を再び粉砕し、これに酢酸ビニル
系バインダー、及び分散剤を混合して厚さ2゜0fiの
グリーンシートを形成する。これによりキュリー点65
℃の内層2が形威される。
2 wt% of MnOtO is added as a property improving agent, mixed and pulverized, and calcined at 1000°C for 2 hours.Next, the calcined material is crushed again, and a vinyl acetate binder and a vinyl acetate binder are added to it. A green sheet with a thickness of 2°0fi is formed by mixing the dispersant. This results in a Curie point of 65
The inner layer 2 of ℃ takes shape.

iii 、次に上記2枚の外層3,3で内層2をサンド
イッチ状に挟んで積み重ねて熱圧着し、厚さ5nのセラ
ミクス素子4を形成する。そして、該素子4を1350
℃×2時間で一体焼成し、焼結体を得る。しかる後、上
記セラミクス素子4の両主面に、例えばAgペーストを
印刷して焼き付は電極55を形成し、さらに該各電極5
にリード線6を半田付けする。これにより本実施例の半
導体磁器1が製造される。
iii.Next, the inner layer 2 is sandwiched between the two outer layers 3, 3, stacked and thermocompressed to form a ceramic element 4 having a thickness of 5n. Then, the element 4 is
It is integrally fired at ℃ for 2 hours to obtain a sintered body. Thereafter, for example, Ag paste is printed and baked on both main surfaces of the ceramic element 4 to form electrodes 55, and each of the electrodes 5 is
Solder the lead wire 6 to. In this way, the semiconductor ceramic 1 of this example is manufactured.

表は、本実施例の効果をfl認するために行った特性試
験の結果を示す。
The table shows the results of characteristic tests conducted to confirm the effects of this example.

この試験では、本実施例の製造方法により作成した半導
体磁器を採用し、これの抵抗値、温度係数、静耐圧、及
び動耐圧を測定した。また、上記半導体磁器は、各外層
1.5m、内層2.0flで直径10關の円板状に形威
したものを採用した。なお、比較するために2fl[の
従来試料A、13を作成し、同様の測定を行った。上記
従来試料Aは上記外層に使用したセラミクス材料(キュ
リー点115℃)を使用し、直径10嶋、厚さ5゜Of
lの単板状ユニットに形威し、また上記従来試料Bは内
層に使用したセラミクス材料(キュリー点65℃)を使
用し、同様の形状とした。
In this test, semiconductor porcelain produced by the manufacturing method of this example was used, and its resistance value, temperature coefficient, static withstand voltage, and dynamic withstand voltage were measured. The semiconductor ceramic was shaped like a disk with a diameter of 10 mm and each outer layer was 1.5 m thick and the inner layer was 2.0 fl thick. For comparison, 2 fl [conventional samples A and 13] were prepared and the same measurements were performed. The above-mentioned conventional sample A uses the ceramic material (Curie point: 115°C) used for the above-mentioned outer layer, and has a diameter of 10 cm and a thickness of 5°.
The conventional sample B used the same ceramic material (Curie point: 65° C.) for the inner layer and had the same shape.

同表からも明らかなように、従来試料A、 Hの場合は
、温度係数25%/L28 %/L静耐圧100V、 
120v1動耐圧85V、95Vであった。これに対し
て本実施例試料の場合は、温度係数20%/に、静耐圧
130v、勤耐圧115vといずれも向上しており、こ
の試験結果からも明らかなように、半導体磁器lの内層
2を高キュリー点とし外層3を低キュリー点としたこと
により、セラミクス素子4の発熱時の熱平衡の速度差を
抑制でき、熱応力破壊を回避でき、耐圧、特に動耐圧に
優れた電子部品が得られる。
As is clear from the same table, in the case of conventional samples A and H, the temperature coefficient is 25%/L28%/L, the static withstand voltage is 100V,
120v1 dynamic withstand voltage was 85V and 95V. On the other hand, in the case of the sample of this example, the temperature coefficient was 20%/, the static withstand voltage was 130 V, and the withstand voltage was 115 V, which were all improved, and as is clear from the test results, the inner layer 2 of the semiconductor ceramic By setting the outer layer 3 to a high Curie point and the outer layer 3 to a low Curie point, it is possible to suppress the difference in speed of thermal equilibrium during heat generation of the ceramic element 4, avoid thermal stress fracture, and obtain an electronic component with excellent withstand voltage, especially dynamic voltage resistance. It will be done.

また、本実施例では、キュリー点の異なる外層内層を積
層することにより熱応力破壊を回避できるから、従来の
セラミクス素子の大型化による対策を不要にでき、それ
だけ小型化でき、ひいては電気機器の小型化に貢献でき
る。
In addition, in this example, thermal stress fracture can be avoided by laminating outer and inner layers with different Curie points, so it is not necessary to take measures to increase the size of conventional ceramic elements, which allows for miniaturization of electrical equipment. can contribute to the development of

なお、上記実施例では、内層2と2枚の外層3゜3とに
よる3層構造にした場合を例にとって説明したが、本発
明はこの構造に限られるものではなく、3層以上の多層
構造にしてもよい、この場合においても外部ほどキュリ
ー温度が低くなるように各層のセラミクス材料を選定す
ればよく、この多層の場合はより熱応力破壊を回避でき
る効果が得られる。
In addition, in the above embodiment, the case where a three-layer structure consisting of an inner layer 2 and two outer layers 3°3 was used was explained as an example, but the present invention is not limited to this structure, and can be applied to a multilayer structure having three or more layers. In this case as well, the ceramic material of each layer may be selected so that the Curie temperature is lower toward the outside, and in the case of this multilayer structure, thermal stress fracture can be more effectively avoided.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明に係る半導体磁器によれば、半導体
磁器の外部に対して内部ほど高キュリー点になるように
し、具体的には高キュリー点の内層を低キュリー点の外
層で挟んで積層化したので、セラミクス素子の熱応力破
壊、特に急激な電圧を印加したときの破壊を回避できる
効果がある。
As described above, according to the semiconductor porcelain according to the present invention, the Curie point is higher on the inside than on the outside of the semiconductor porcelain, and specifically, the inner layer with a high Curie point is sandwiched between the outer layers with a low Curie point and laminated. This has the effect of avoiding thermal stress breakdown of the ceramic element, particularly breakdown when a sudden voltage is applied.

【図面の簡単な説明】[Brief explanation of drawings]

第1図ないし第3図は本発明の一実施例による半導体磁
器を説明するための図であり、第1図はその断面図、第
2図はその製造工程を示す分解斜視図、第3図はその積
層化した状態を示す斜視図、第4図は従来の半導体磁器
を示す断面図である。 図において、1は半導体磁器、2は内層、3は外層、4
はセラ逅りス素子である。
1 to 3 are diagrams for explaining semiconductor porcelain according to an embodiment of the present invention, in which FIG. 1 is a sectional view thereof, FIG. 2 is an exploded perspective view showing its manufacturing process, and FIG. 4 is a perspective view showing the laminated state, and FIG. 4 is a sectional view showing the conventional semiconductor ceramic. In the figure, 1 is semiconductor porcelain, 2 is inner layer, 3 is outer layer, 4
is a ceramic element.

Claims (2)

【特許請求の範囲】[Claims] (1)所定のキュリー点で低抵抗体から高抵抗体に転移
する正の抵抗温度特性を有する半導体磁器において、外
部に対して内部ほど高キュリー点のセラミクス材料で構
成したことを特徴とする正の抵抗温度特性を有する半導
体磁器。
(1) In a semiconductor porcelain having a positive resistance-temperature characteristic that transitions from a low resistance to a high resistance at a predetermined Curie point, the inside is made of a ceramic material with a higher Curie point than the outside. Semiconductor porcelain with resistance temperature characteristics.
(2)上記半導体磁器が、高キュリー点のセラミクス材
料からなる内層の両面に、該内層より低キュリー点のセ
ラミクス材料からなる外層を積層し、これを一体焼成し
てなることを特徴とする特許請求の範囲第1項記載の正
の抵抗温度特性を有する半導体磁器。
(2) A patent characterized in that the semiconductor porcelain is formed by laminating an outer layer made of a ceramic material with a lower Curie point than the inner layer on both sides of an inner layer made of a ceramic material with a lower Curie point, and firing these together. A semiconductor ceramic having a positive resistance temperature characteristic according to claim 1.
JP18133789A 1989-07-13 1989-07-13 Semiconductor porcelain possessing positive resistance-temperature characteristic Pending JPH0346201A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18133789A JPH0346201A (en) 1989-07-13 1989-07-13 Semiconductor porcelain possessing positive resistance-temperature characteristic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18133789A JPH0346201A (en) 1989-07-13 1989-07-13 Semiconductor porcelain possessing positive resistance-temperature characteristic

Publications (1)

Publication Number Publication Date
JPH0346201A true JPH0346201A (en) 1991-02-27

Family

ID=16098935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18133789A Pending JPH0346201A (en) 1989-07-13 1989-07-13 Semiconductor porcelain possessing positive resistance-temperature characteristic

Country Status (1)

Country Link
JP (1) JPH0346201A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6095901A (en) * 1983-10-31 1985-05-29 松下電器産業株式会社 Positive temperature coefficient semiconductor porcelain
JPH0196901A (en) * 1987-10-08 1989-04-14 Murata Mfg Co Ltd Semiconductor porcelain having positive resistance temperature characteristic
JPH01110701A (en) * 1987-10-23 1989-04-27 Murata Mfg Co Ltd Semiconductor porcelain with positive resistance temperature characteristic

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6095901A (en) * 1983-10-31 1985-05-29 松下電器産業株式会社 Positive temperature coefficient semiconductor porcelain
JPH0196901A (en) * 1987-10-08 1989-04-14 Murata Mfg Co Ltd Semiconductor porcelain having positive resistance temperature characteristic
JPH01110701A (en) * 1987-10-23 1989-04-27 Murata Mfg Co Ltd Semiconductor porcelain with positive resistance temperature characteristic

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