JPH0346372A - Mos type transistor - Google Patents

Abstract

PURPOSE:To suppress hot carriers by forming a partial well region by partly implanting impurity without forming a well region on a whole surface. CONSTITUTION:A P-type well region 2 is formed on a P-type silicon substrate 1 except a region formed with a channel. The surface of the substrate 1 is oxidized, a gate oxide film 3 is formed, and a gate electrode 4 is then formed. With the electrode 4 as a mask an N-type low concentration impurity diffused layer 5 is formed, and sidewalls are formed on the sidewalls of the electrode 4 and the film 3. In this case, since the low concentration impurity diffused layer under the sidewall is formed in the lower impurity concentration substrate than that of the well region, a depletion layer is extended larger to reduce an electric field smaller. Thus, generation of hot carriers can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an LDD (LDD) used in a miniaturized semiconductor device.
The present invention relates to an MO8 type transistor with an extremely doped drain structure.

2. Description of the Related Art Performance requirements for conventional semiconductor integrated circuits include miniaturization and reduction in current consumption. In order to achieve the former, individual transistors are being downsized. For the latter, complementary MO8) transistors are used. When a transistor is downsized, the electric field near the drain is strengthened, making it easier to generate hot carriers that cause characteristic fluctuations. Therefore, MOS type transistors having an LDD structure have become common. or,
When a complementary MOS transistor is formed, a transistor with a parasitic NPN structure or a transistor with a parasitic PNP structure is formed between an impurity diffusion layer serving as the source or drain of one conductivity type transistor and an adjacent well region of the other conductivity type transistor. will be done. Therefore, when the noise spreads to the impurity diffusion layer or the well region, a current flows between the impurity diffusion layer of one conductivity type transistor and the well region of the other conductivity type transistor, just like a bipolar transistor.

As a result, the well region potential fluctuates due to the resistance of the well region, further increasing the bipolar current, and eventually causing a latch-up phenomenon that leads to destruction of the transistor. Therefore, in order to suppress the latch-up phenomenon, it is necessary to lower the resistance of the well region as much as possible and suppress fluctuations in the well region potential.

From the above, the conventional technique is an MO8 type transistor having a structure as shown in FIG.

In this structure, a p-type well region 12 is formed by implanting impurities into a p-type silicon substrate 11 so that the resistance is as low as possible in consideration of the subsequent process.
A gate oxide film 13 and a gate electrode 14 made of polysilicon are stacked on the surface of the gate oxide film 1113, and an n-type low concentration impurity diffusion layer 15 is formed in the well region 12 near the gate oxide film 11113.
is formed, a sidewall 16 as an implantation mask is formed on the sidewall of the gate oxide M13 and the gate electrode 14,
An n-type, high concentration impurity diffusion layer 17 is formed in the well region 12 in contact with the low concentration impurity diffusion layer 15 .

Problems to be Solved by the Invention In order to suppress hot carriers, that is, to suppress the electric field near the drain, it is necessary to widen the width of the depletion layer in the junction layer between the low concentration impurity diffusion layer 15 and the well region 12. be. To achieve this, the impurity concentration of the low concentration impurity diffusion layer 15 and the well region 12 must be lowered. However, there is a problem of latch-up, and in order to lower the resistance of the well region 12, the impurity concentration of the well region 12 must be made as high as possible. This is not possible with the current structure.

Means for Solving the Problems Unlike conventional methods, a well region is not formed over the entire surface, but by implanting impurities into a portion, a partial well region is formed.

That is, the structure is such that a well region is not formed in a region in contact with a low concentration impurity diffusion layer that is involved in the generation of hot carriers near the drain.

According to the MOS transistor of the present invention, the low concentration impurity diffusion layer under the sidewall is formed in the semiconductor substrate with a lower impurity concentration than the well region, so the depletion layer expands more and the electric field becomes smaller. , generation of hot carriers can be suppressed. In addition, the bipolar current due to the parasitic bipolar transistor has a high impurity concentration,
Since it flows through the low-resistance well region, it is possible to suppress potential fluctuations and suppress the occurrence of latch-up.

Therefore, the effect of suppressing hot carriers and latch-up can be obtained.

Embodiment As an example of an embodiment of the present invention, an n-channel (hereinafter n-
A step surface of an MO8 type transistor (denoted as ch) is shown in FIG. 1, and will be described with reference to this.

In this structure, the p-type silicon substrate 1 is doped with poron at a dose of I x 10 l, except for the region where the channel is formed.
3 cta-2 and an energy of 50 keV, and through annealing and drive-in heat treatment, a P-type well region 2 is formed. Next, the surface of the silicon substrate 1 is oxidized, and a gate oxide film 3 to 200 is formed. After forming, polysilicon as an electrode is grown to a thickness of 4000A,
Gate electrode 4 is formed by buttering and etching processes.
was formed, and using this gate electrode 4 as an implantation mask, phosphorus was implanted at a dose of 2 x 1013 cm-2.
A low-concentration impurity diffusion layer 5 is formed, and an oxide film is grown by vapor phase growth, and sidewalls 6' are formed on the side walls of the gate electrode 4 and gate oxide film 3 by anisotropic etching. After this, arsenic is added 5×1
This can be obtained by performing a process of forming an n-type high concentration impurity diffusion layer 7 by implanting at a dose of 0I5 cm 2 .

This L D D (Lightly Doped
According to the MO8 type transistor having the drain) structure, the p-type well region is in contact with the high concentration impurity diffusion layer 7 but not with the low concentration impurity diffusion layer 5. In addition, in the embodiment, an n-ch transistor on a p-type silicon substrate was explained, but a p-ch transistor on an n-type silicon substrate was explained.
It goes without saying that the present invention is also applicable to transistors.

Effects of the Invention According to the MOS transistor of the present invention, the low concentration impurity diffusion layer under the sidewall is formed in the semiconductor substrate with a lower impurity concentration than the well region, so the depletion layer expands more and the electric field becomes stronger. This makes it possible to suppress the generation of hot carriers.

Furthermore, since the bipolar current generated by the parasitic bipolar transistor flows through the well region with high impurity concentration and low resistance, it is possible to suppress fluctuations in potential and suppress the occurrence of latch-up. As a result, the reliability of the device can be improved.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of the MO8 type transistor of the present invention, and FIG. 2 is a sectional view of a conventional MOS type transistor. 1.11...Silicon substrate, 2,12...
...well region, 3,13... gate oxide film,
4, 14... Gate electrode, 5, 15...
-Low concentration impurity diffusion layer, 6, 16... side wall, 7, 17... high concentration impurity diffusion layer.

Claims (1)

[Claims] A gate insulating film and a gate electrode are sequentially formed on the surface of a semiconductor substrate of one conductivity type, a sidewall of an insulating film is formed on the sidewalls of the gate insulating film and the gate electrode, and a semiconductor is formed in the semiconductor substrate below the sidewall. A first impurity diffusion layer having a conductivity type opposite to that of the substrate is formed, and a second impurity diffusion layer having the same conductivity type as the first impurity diffusion layer and having a higher concentration than the first impurity diffusion layer is formed in the first impurity diffusion layer. A MOS type transistor, characterized in that a well region is formed in contact with the semiconductor substrate and has the same conductivity type as the semiconductor substrate under the second impurity diffusion layer.