JPH0346590Y2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field] This invention relates to a trapezoidal wave generation circuit used, for example, in a PLL phase comparison circuit, and in particular relates to a configuration that generates a trapezoidal wave using MOS transistors. be.

[Conventional technology]

In the conventional technology, a trapezoidal wave generation circuit is used as a phase comparison circuit of a PLL. PLL is
The input pulse is made into a trapezoidal wave by a trapezoidal wave generation circuit, the slope part of this trapezoidal wave is sampled by a sampling pulse, and an error voltage proportional to the phase difference is generated.
It controls the oscillation frequency of the VCO by supplying it to the VCO, divides its output, and supplies it again to the sampling gate as a sampling pulse to generate an output that is an integral multiple of the input pulse. .

[Problem that the invention attempts to solve]

However, if the trapezoidal wave formed by the trapezoidal wave generating circuit has the same slope in its rise and fall as shown in Figure 3, when such a trapezoidal wave is used in the PLL, the PLL The phase at which the signal is locked is present in both the rising slope section and the falling slope section. For this reason, the VCO may not oscillate at an integer multiple of the input pulse, but may oscillate at several times the input pulse.
There is a possibility that the PLL lock phase may not be normal.

Therefore, the purpose of this invention is to form a trapezoidal wave in which the VCO oscillates at an integral multiple of the input pulse when used in a PLL phase comparison circuit, and to generate a trapezoidal wave with a simple circuit configuration. The purpose is to provide circuits.

[Means for solving problems]

This device has first, second, and third MOS transistors 1, 2, and 3 of a first conductivity type, and a fourth MOS transistor 4 of a second conductivity type, and has a first reference potential. point and the second reference potential point.
and the second MOS transistors 1 and 2 are connected in series, and the third and fourth MOS transistors 3 and 4 are connected in series between the first reference potential point and the second reference potential point. The gates of the four MOS transistors 1 and 4 are connected to an input terminal 7 to which a square wave is supplied, the gates of the second and third MOS transistors 2 and 3 are commonly connected, and this common connection point is connected to the first and third MOS transistors. A capacitor 5 is connected between the connection point of the fourth and third MOS transistors 3 and 4 and the first or second reference potential point. This trapezoidal wave generating circuit is characterized in that the conductance of the transistor 4 is made larger than the conductance of the third MOS transistor 3.

[Effect]

The input pulse alternately turns on the N-channel MOS transistors 1, 2, and 3 and the P-channel MOS transistor 4, and the capacitor 5 connected to the MOS transistors 3 and 4.
Charge is performed by MOS transistor 4 whose conductance is larger than that of MOS transistor 3,
Also, the capacitor 5 is connected by the MOS transistor 3.
As a result, a trapezoidal wave with a steep rise and a sloped fall is output from the output terminal.

〔Example〕

An embodiment of this invention will be described below with reference to the drawings. In FIG. 1, 1, 2, and 3 are N-channel MOS transistors, and 4 is a P-channel MOS transistor.

The drain of MOS transistor 1 is the power supply terminal 6
The source is connected to the drain of the MOS transistor 2. The source of MOS transistor 2 is grounded, and the gate is connected to MOS transistor 3.
This connection point is connected to the connection point between the source of MOS transistor 1 and the drain of MOS transistor 2. The source of MOS transistor 3 is grounded. The source of the MOS transistor 4 is connected to the power supply terminal 6, the gate is connected to the input terminal 7, and the drain is connected to the drain of the MOS transistor 3. This MOS
One end of a capacitor 5 is connected to a connection point between the drain of the transistor 4 and the drain of the MOS transistor 3, and the other end is grounded, and an output terminal 8 is led out from this connection point.

The conductance of MOS transistor 4 is
It is said to be larger than the conductance of MOS transistor 3. The conductance of a MOS transistor is determined by its gate width W and gate length L, and the conductance is proportional to W/L. That is, compared to the gate of MOS transistor 3, the gate of MOS transistor 4 is
The gate width W is large or the gate length L is small.

A voltage V _DD is supplied to the power supply terminal 6 from a DC power supply, and the ground level is set to V _SS .
The input terminal 7 has a voltage V DD at its high level and a voltage V _DD at its low level, as shown in Figure 2A.
An input pulse is provided that is at V _SS .

MOS transistors 1 and 4 are activated by the input pulse.
When the gate of is set to a low level, MOS transistor 1 is not conductive because it is an N-channel type MOS transistor, and MOS transistor 4 is conductive because it is a P-channel type MOS transistor.
Turns on. At this time, MOS transistor 2
and 3 are both off because the MOS transistor 1 is non-conductive.

At the same time as the MOS transistor 4 turns on, the current flowing through the MOS transistor 4 causes
Capacitor 5 is charged. Therefore, output terminal 8
At the same time as the MOS transistor 4 turns on, the voltage generated rises as shown in FIG.
It increases until it becomes equal to the power supply voltage V _DD .

MOS transistors 1 and 4 are activated by the input pulse.
When the gate of MOS transistor 4 is set to a high level, it does not conduct because it is a P channel type.
Since the MOS transistor 1 is an N-channel type, it becomes conductive and turns on. At the same time that MOS transistor 1 turns on, the diode-connected MOS
Transistor 2 makes MOS transistor 3 conductive.

At the same time as the MOS transistor 3 turns on, the charge accumulated in the capacitor 5 is transferred to the MOS transistor 3.
It is discharged as a current through the transistor 3.
Therefore, the voltage generated at the output terminal 8 is MOS
At the same time as transistor 3 turns on, the voltage falls as shown in FIG. 2B until it becomes equal to the ground level V _SS .

A continuous input pulse as shown in FIG. 2A is supplied to the input terminal 7, and the above-mentioned operation is repeated alternately, so that a continuous trapezoidal wave as shown in FIG. 2B is generated at the output terminal 8. Output. Furthermore, as mentioned above, the conductance of the MOS transistor 4 is larger than that of the MOS transistor 3, so the rise of the output from the output terminal 8 (Fig. 2B) is steep, and the fall is gradual. be taken as a thing.

In one embodiment of this invention, the capacitor 5 is connected between the connection point between the drain of the MOS transistor 3 and the drain of the MOS transistor 4, and the power supply terminal 6.
It may also be configured such that it is connected between.

Furthermore, each of the MOS transistors 1, 2, and 3 may be of a P channel type, and the MOS transistor 4 may be of an N channel type.

Furthermore, the conductance of the MOS transistor 1 may be made smaller than the conductance of the MOS transistor 2, so that the output has a slope at the rise time and a steep fall time.

[Effect of idea]

According to this invention, a square wave input can be converted into a trapezoidal wave output with a simple circuit configuration of three N-channel transistors, one P-channel transistor, and one capacitor. Also, since either the rise or fall of this trapezoidal wave is steep depending on the conductance value of the MOS transistor, when used in a PLL, the VCO may oscillate at a pulse other than an integral multiple of the predetermined input pulse, or the PLL may It is possible to prevent the lock phase from becoming incorrect.

[Brief explanation of drawings]

FIG. 1 is a connection diagram of an embodiment of this invention, FIG. 2 is a waveform diagram used to explain an embodiment of this invention, and FIG. 3 is a waveform diagram used to explain a conventional trapezoidal wave generating circuit. 1, 2, 3: N-channel transistor,
4: P-channel transistor, 5: capacitor, 7: input terminal, 8: output terminal.

Claims (1)

[Claims for Utility Model Registration] It has first, second, and third MOS transistors of a first conductivity type, and a fourth MOS transistor of a second conductivity type; The first and second MOS transistors are connected in series between the second reference potential point, and the third and fourth MOS transistors are connected between the first reference potential point and the second reference potential point. are connected in series, the first and fourth
The gate of the MOS transistor is connected to an input terminal to which a square wave is supplied, and the gate of the second and third
The gates of the MOS transistors are commonly connected, this common connection point is connected to the connection point of the first and second MOS transistors, and the connection point of the fourth and third MOS transistors is connected to the connection point of the first and second MOS transistors.
Alternatively, a trapezoidal wave generating circuit characterized in that a capacitor is connected between the second reference potential points, and the conductance of the fourth MOS transistor is made larger than the conductance of the third MOS transistor.