JPH0347588B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a one-transistor/one-capacitor type MOS dynamic memory element that can be highly integrated.

(Prior art) Conventionally, one-transistor, one-capacitor type dynamic memory has been widely used as a dynamic memory because it can be highly integrated, but the following problems arise when trying to achieve even higher integration. The point was hot.

With higher integration, the cell area and capacitor area also decrease, so in order to obtain a sufficient noise margin, it is necessary to make the capacitor oxide film thinner so as not to reduce the capacitor capacity, but making it thinner will reduce the manufacturing yield. do.

Since the capacitor is formed of a MOS capacitor consisting of a conductive electrode, a dielectric material, and a semiconductor substrate, a so-called soft error occurs in which the contents of the memory cell change due to the charge generated by the alpha rays incident on the substrate. There is a problem with the reliability of the device.

(Object of the Invention) The present invention has been made in view of the above points, and its object is to develop a dynamic memory element which can increase the capacitor capacity per unit area and obtain a dynamic memory element with high α-ray resistance. An object of the present invention is to provide a method for manufacturing a memory device.

(Summary of the Invention) The gist of the present invention is to form a groove in the element isolation region of a semiconductor substrate, bury an element isolation insulator in the groove, and form a groove in the element isolation insulator. The purpose is to form a capacitor composed of a conductor electrode, a dielectric material, and a conductor electrode by using the side and bottom surfaces of the trench.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of an element formed according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line -- in FIG. In these figures, reference numeral 1 denotes a P-type silicon substrate as a semiconductor substrate, on the surface side of which a groove 2 is dug and an oxide film 3 as an insulator for isolation between elements is embedded. Further, a P-type channel stop layer 4 for preventing reversal is formed on the substrate portion under this oxide film 3. A groove 5 is formed in the oxide film 3. A first electrode 6 made of polysilicon is formed inside the groove 5 on the bottom and side surfaces of the groove 5, and then a dielectric 7 made of a silicon nitride film is formed on the first electrode 6. However, by further forming a second electrode 8 made of polysilicon on this dielectric 7, a capacitor is embedded. Said first electrode 6 of this capacitor extends onto the substrate surface adjacent to the oxide film 3. Then, the first electrode 6 is connected to the N ⁺ diffusion layer 9 formed in the adjacent substrate portion.
In addition to the N ⁺ diffusion layer 9, the P-type silicon substrate 1 includes:
An N ⁺ diffusion layer 10 is formed at a predetermined distance from this diffusion layer 9 in a direction opposite to the oxide film 3 . Furthermore, a gate oxide film 11 and a gate electrode 12 are laminated on the substrate surface between the pair of N ⁺ diffusion layers 9 and 10. That is, a transfer gate transistor having the gate oxide film 11 and the gate electrode 12 and having the N ⁺ diffusion layers 9 and 10 as the source and drain is formed on the silicon substrate 1. Further, on the silicon substrate 1, in the capacitor section, an oxide film 13 and an address line 14 are laminated to be located on the second electrode 8 of the capacitor. This address line 14 is formed of polysilicon together with the gate electrode 12 of the transfer gate transistor. Then, an address line 14 is connected to the gate electrode 12. An insulating film 15 is formed on the entire surface of the silicon substrate 1 so as to cover the address lines 14, gate electrodes 12, and the like. Then, a bit line 16 made of aluminum is formed on this insulating film 15, and a protective film 17 is further formed. Note that the bit line 16 is connected to the contact hole 18 formed in the insulating film 15.
It is connected to the N ⁺ diffusion layer 10 via. Further, the second electrode 8 of the capacitor is connected to ground potential.

FIG. 3 is an electrical equivalent circuit for one dynamic memory element as described above, where _C1 is a capacitor and _T1 is a transfer gate transistor.

Next, a method for manufacturing the above-mentioned dynamic memory element (an embodiment of the present invention) will be explained with reference to FIG.

First, for example, an impurity concentration of 1×10 ¹⁵ to 1×10 ¹⁶ cm
A resist pattern is formed on a P-type silicon substrate 1 of ^-3 having openings at locations that are to become inter-element isolation regions of the substrate. Next, using the resist as a mask, the silicon substrate 1 is etched using a reactive ion etching device using CBrF ₃ gas, for example, to form a groove 2 with a depth of 2 μm in the element isolation region of the silicon substrate 1. do.
Furthermore, by implanting boron (B) ions at a dose of 5×10 ¹² to 5×10 ¹³ ions/cm ² using the resist as a mask, P is implanted into the substrate portion at the bottom of the groove 2.
A mold channel stop layer 4 is formed. (See Figure 4A) Next, after removing the resist, an oxide film (SiO ₂ ) 3 is deposited on the entire surface by sputtering, and the grooves 2 are
fill in. On top of that, apply 2 polyimide resin 21.
Apply ~10 μm. At this time, due to the viscosity of the resin,
The surface becomes almost flat. (See Figure 4B) After that, the resin 21 is etched using a reactive ion etching device using Freon gas mixed with oxygen.
Then, by etching the oxide film 3, the oxide film 3 is left only in the groove 2 as an insulator for isolation between elements, and the substrate surface is planarized (see FIG. 4C).

Next, in order to form a groove in the remaining oxide film 3 in which a capacitor is to be buried, a resist pattern having an opening in the groove formation portion is formed on the substrate 1 and the oxide film 3. Then, using the resist as a mask, etching is performed using a reactive ion etching device using fluorocarbon gas.
A trench 5 with a depth of 1.5 μm is dug in the oxide film 3. (Figure 4D
(See) Thereafter, an oxide film 22 with a thickness of 100 to 500 Å is formed on the exposed surface of the silicon substrate 1 by thermal oxidation. This oxide film 22 masks the diffusion of impurities from the first layer polysilicon to the substrate 1, which will be formed in a later step. (See FIG. 4E) Next, a part of the oxide film 22, that is, the oxide film 2
2, a portion adjacent to the oxide film 3 serving as an insulator for isolation between elements is removed. (See Figure 4 F) Next, apply phosphorus (P), arsenic (As), etc. to the entire surface.
A first layer of polysilicon containing a high concentration of impurities such as remove. As a result, the first electrode 6 of the capacitor made of the first layer polysilicon is formed extending over the side and bottom surfaces of the trench 5 as well as the surface of the substrate adjacent to the oxide film 3. Also, of course,
Oxide film 22 is removed. (FIG. 4G) Thereafter, a silicon nitride film that will become the dielectric of the capacitor is deposited to a thickness of 200 to 300 Å by low pressure CVD. Then, in order to reduce the leakage current of the nitride film, an oxide film with a thickness of 20 to 40 Å is formed on the surface of the nitride film in a wet oxygen atmosphere at 850 to 950°C. Subsequently, a second layer of polysilicon containing, for example, phosphorus (P) or arsenic (As) at a high concentration is deposited over the entire surface by low pressure CVD. At this time, a flat surface can be obtained by setting the film thickness so that the grooves 5 are completely filled. Thereafter, the second layer polysilicon is patterned by photolithography, and the silicon nitride film is etched using the remaining polysilicon as a mask. As a result, a dielectric 7 of the capacitor made of a silicon nitride film is formed on the first electrode 6 of the capacitor, and a second electrode of the capacitor made of a second layer of polysilicon is further formed on this dielectric 7. 8 is formed. (See FIG. 4H) Thereafter, oxidation is performed in an oxygen atmosphere at 950° C. to form an oxide film on the entire surface. This oxide film has a thickness of 300 to 500 Å on the single crystal silicon substrate 1.
Make it thick. Subsequently, molybdenum silicide is deposited to a thickness of 3000 Å over the entire surface by sputtering. Then, by patterning the molybdenum silicide using photolithography, the gate electrode 12 and address line 1 of the transfer gate transistor made of the molybdenum silicide are patterned.
4 are respectively formed at predetermined positions. Furthermore, by patterning the oxide film using the gate electrode 12 and address line 14 as a mask, the gate oxide film 11 of the transfer gate transistor made of the oxide film and the insulating oxide film 13 under the address line 14 are formed. . Note that the address line 14 is patterned so as to be connected to the gate electrode 12. (See Figure 4 I.) Thereafter, arsenic (As) is ion-implanted into the substrate 1 in a self-aligned manner using the gate electrode 12 as a mask, thereby adding N ⁺ to the substrate 1 as the source and drain of the transfer gate transistor.
Diffusion layers 9 and 10 are formed. Here, one side located on the oxide film 3 side as an insulator for element isolation
The N ⁺ diffusion layer 9 is connected to the first electrode 6 of the capacitor.
connected to. (See Figure 4 I) Next, for example, PSG (phosphorus silica glass) is deposited by CVD.
An insulating film 15 is formed on the entire surface by a method of deposition, and a contact hole 18 is formed in this insulating film 15 on the N ⁺ diffusion layer 10 by photolithography. Thereafter, by sputtering and patterning aluminum containing 1 to 2% silicon, the bit line 1 is connected to the N ⁺ diffusion layer 10 through the contact hole 18.
6 is formed on the insulating film 15 using the aluminum. (See FIG. 4J) Finally, a protective film is formed over the entire surface. Through the above steps, the dynamic memory device shown in FIGS. 1 and 2 is completed.

Note that the above is an N
Although it is a channel process, it is also possible to form a memory element in a P-well provided in an N-type substrate or an insulating substrate.Furthermore, by reversing all the polarities of impurities and the polarity of the power supply, it is possible to form the memory element in a P-well provided in an N-type substrate or an insulating substrate. It can also be constructed using a P channel process.

Furthermore, although molybdenum silicide is used as the address line 14, it may be made of other high melting point metal silicides, or it may be of a so-called polycide structure in which polysilicon is laid under the silicide, or polysilicon may be used as long as it is devised to lower the resistance of the address line. .

Furthermore, as the dielectric material 7, silicon dioxide or a high dielectric material with a small leakage current may be used instead of silicon nitride.

(Effects of the Invention) As explained above, in the method for manufacturing a dynamic memory element of the present invention, a groove is formed in the element isolation region of a semiconductor substrate, and an insulator for element isolation is buried in the groove. Then, a groove is dug in the insulator for isolation between elements, and a capacitor is formed using the side and bottom surfaces of the groove. Therefore, the capacitance per unit area of the capacitor can be increased compared to a planar structure, and the area of the capacitor can be reduced. In addition, since the capacitor uses a conductor electrode-dielectric-conductor electrode structure rather than a MOS type structure,
There is no need to consider interface states, which is a problem with MOS type devices, and high dielectric materials such as silicon nitride can be used. Therefore, the capacitance per unit area of the capacitor is further increased, and the area of the capacitor can be further reduced. Furthermore, since the capacitor is formed in the thick insulator for isolation between elements, carriers generated by α rays will not flow into the capacitor from the substrate, and the strength against α rays will be improved.

[Brief explanation of drawings]

1 and 2 show a dynamic memory device obtained according to an embodiment of the present invention.
The figure is a plan view, FIG. 2 is a sectional view taken along the - line in FIG. 1, and FIG. 3 is a top view of the dynamic memory element 1
FIG. 4 is a sectional view showing an embodiment of the method for manufacturing a dynamic memory element of the present invention. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Groove, 3... Oxide film, 5... Groove, 6... First electrode, 7... Dielectric, 8... Second electrode, 9, 10... …N ⁺ diffusion layer,
11... Gate oxide film, 12... Gate electrode,
C ₁ ... Capacitor, T ₁ ... Transfer gate transistor.

Claims (1)

[Claims] 1. A step of forming a groove in the element isolation region of a semiconductor substrate, a step of burying the groove with an element isolation insulator, and forming a groove for capacitor embedding in the element isolation insulator. A first electrode of a capacitor is formed on the side and bottom surfaces of the groove, a dielectric film is formed on the inner surface of the first electrode, and a second electrode of the capacitor is further formed inside the first electrode of the capacitor, thereby forming a capacitor in the groove. A process of embedding and forming, and then,
In a substrate region adjacent to the element isolation insulator,
forming a transfer gate transistor connected to the first electrode.