JPH0347621B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a drive circuit for a solid-state imaging device, and particularly to a small and simple drive circuit that can be disposed on a substrate on which a solid-state imaging device is mounted close to the device. The present invention relates to the configuration of a drive circuit.

(b) Prior Art and Problems A drive circuit for driving a solid-state imaging device, such as a charge injection device (CID), has conventionally been constructed using individual semiconductor devices or ready-made ICs on a printed circuit board. When using a CID, it is necessary to use a cooler, but the drive circuit described above is large in circuit size and consumes a large amount of power.
It is impossible to house it in the same cooler as CID. Therefore, the drive circuit is placed outside the cooler and connected to the CID attached to the cooler via a lead wire. In such a configuration, the number of lead wires increases as the CID becomes larger, but leading out a large number of lead wires from the cooler causes various problems.

Therefore, various studies have been made to mount the drive circuit and the CID element on the same substrate. In this case, the drive circuit is a dedicated IC, and this IC element is
It is arranged together with the CID element on, for example, a ceramic substrate, and connects bonding pads such as input terminals for row selection and output terminals for data output on the surface of the pixel element and circuit wiring formed on the surface of the ceramic substrate. , electrical connection is made by bonding thin metal wires.

Such a structure requires a complicated configuration of the row selection IC, and manufacturing the IC is not necessarily easy.

(c) Object of the Invention An object of the present invention is to provide a drive circuit that can solve the above-mentioned problems and simplify the configuration of an IC for driving a solid-state imaging device such as a CID.

(d) Structure of the Invention The feature of the present invention is that a solid-state image sensor having a plurality of pixels arranged two-dimensionally and mounted on a predetermined substrate is sandwiched between the shift register and the shift register. A drive IC element is provided which includes a predetermined logic circuit provided corresponding to each stage and whose element arrangement is a mirror image of each other, and is built into the two drive IC elements. The outputs obtained by inputting the same drive signal to each of the shift registers and the shaping pulses having a mutually complementary relationship are subjected to a logical operation in a logic circuit built in the two drive ICs. The present invention is configured such that the output obtained by this is used as a drive pulse for row selection of the solid-state image sensor.

(e) Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing the configuration of an embodiment of a driving circuit for a solid-state imaging device according to the present invention. In the figure, reference numeral 1 denotes a CID element in which a plurality of pixels in n rows and m columns are two-dimensionally arranged, and input terminals IN ₁ for each n/2 row selection drive pulse are provided on both left and right sides of the CID element.
IN ₃ , ...... INn and IN ₂ , IN ₄ , ...... INn, that is, in the figure, odd numbered input terminals are provided on the left side, even numbered input terminals are provided on the right side, and each n/
It has two signal output ends (not shown).
Reference numerals 2 and 2' indicated by dashed lines are CI elements (hereinafter simply abbreviated as IC) for driving the CID element 1, which have an element array formed in a mirror image-reversal relationship with each other,
It incorporates n/2 stage shift registers 3, 3' and NAND gates 4', 4'. The shift register 3 in the IC 2 receives the drive signal 5 from the outside as a serial input, transmits it to the shift register 3 in the direction shown by the arrow 6 in synchronization with the clock, and inputs it in synchronization with the clock as well. input into the NAD gate 4 together with the shaped shaping pulse (PS _A ), and its output is sent from each output terminal O ₁ , O ₃ , ......On
Corresponding input terminals IN ₂ , IN ₄ , ...... of CID element 1
Drive pulses 7 are sequentially sent to INn. On the other hand, the drive signal 4 is also supplied to the IC 2' at the same time, and is transmitted within the shift register 3' in the IC 2' in the direction indicated by the arrow 6' in synchronization with the clock. Furthermore, this is inputted to the NAD gate 4' together with the shaping pulse (PS _B ) inputted in synchronization with the clock, and the corresponding CID element 1 is output from each output terminal O ₂ , O ₄ , ......On.
The drive pulse 7 is sequentially output to the input terminals IN ₂ , IN ₄ , ... INn of the input terminals IN 2 , IN 4 , ... INn.

Since the above two shaping pulses PS _A and PS _B have complementarity as described later, the output timings of the drive pulses 7 and 7' sent out from IC1 and IC2 are also complementary, and it is impossible for both to be output at the same time. do not have.

Next, the operation of this embodiment will be explained with reference to FIGS. 2 and 3.

FIG. 2 is a circuit configuration diagram showing the configuration of the above IC2,
Although it is not shown, the circuit configuration of IC2' is exactly the same as this, but it is changed to PS _A as a shaping pulse.
The only difference is that PS _B is connected.

In the figure, 8 is a NAND gate, 9 is an inverter, φ is a clock, and φ is inverted. One NAND gate 8 is provided corresponding to each stage of the shift register 3,
A shaping pulse PS _A is input together with the parallel output of the shift register 3. The output of this is inverted by an inverter 9 provided for each NAND gate 8, and is used as a driving pulse 7.
It is input to each odd-numbered input terminal IN ₁ to INn of the CID element. Similarly, in the IC 2', the drive signal 5 input to the shift register 3' is a shaping pulse having a complementary relationship with the shaping pulse PS _A.
The drive pulse 7' which is subjected to NAND operation with PS _B and further inverted is applied to each even numbered input terminal IN ₂
~Sent to INn. In the figure, the symbol in parentheses indicates the IC2' side.

FIG. 3 is a timing diagram for explaining the operation of this embodiment, and the horizontal axis indicates time. The figure shows, from the top, the drive signal 5, the state of each row at each time, the selected row number, the shaping pulses PS _A , PS _B , the clock φ,
shows.

When a drive signal 5 is sent from an external circuit (not shown), the drive signal 5 is synchronized with the clock φ.
The signal is taken into the first stage of shift registers 3 and 3' in IC1 and IC2, that is, the stage corresponding to the first row in shift register 3 and the second row in shift register 3'. Then, in synchronization with the clock, this drive signal 5 is applied to the corresponding NAND gate 8,
8', and a shaping pulse is output in each.
PS _A and PS _B are subjected to NAND operation, and then inverted by inverters 9 and 9', respectively, to drive pulse 7.
and 7' are input to the input terminals IN ₁ and IN ₂ of the CID element 1.

In this example, the above shaping pulse PS _A and
PS _B is approximately 1/1/1 of the period of the drive signal 5 as shown in the figure.
2 and are configured to be substantially complementary, that is, when one is 1, the other is 0, so that the same drive signal 5 and the above two shaping pulses PS _A and
Drive pulses 7 and 7', which are the NAND operation results with PS _B , are also substantially complementary, and when one is 1, the other is 0. In this embodiment, first _, the rear half of the drive signal 5 is removed and the drive pulse 7 corresponding to only the front half is input to the input terminal IN 1 of row number 1, and then the drive pulse 7 corresponding to only the front half is input to the input terminal IN 2 of row number _2.
A drive pulse 7' corresponding to the last half of the drive signal 5 is input to the drive signal 5.

Then, in synchronization with the next clock φ, the drive signal 5 is transferred to the next stage of the shift register 3, and sent to the NAND gate by the clock. Next, as in the previous stage, the NAND operation results with the shaping pulses PS _A and PS _B are inverted, and the input terminal
Drive pulses are input in the order of IN ₃ and IN ₄ .

Similarly, the drive signal 5 is transmitted to the shift register 3,
3' to the next stage in synchronization with clock φ,
Drive pulses are sent to the odd numbered and then even numbered input terminals in synchronization with the clock.

As described above, in this embodiment, the single drive signal 5 is
2 and IC2', and while simultaneously transmitting it through the shift registers 3 and 3', NAND is performed between this signal and two shaping pulses PS _A and PS _B , which have a mutually complementary relationship. By using this as a drive pulse, each row of the CID element 1 can be selected in order from the smaller number to the larger number.

In this example, two types of ICs, IC1 and IC2, are used.
However, since the element arrangement of both is in a mirror-image inversion relationship, by preparing one mask pattern and inverting the left and right sides of this, the other mask pattern can be obtained. Therefore these 2
It is easy to manufacture different types of ICs.

The present invention is not limited to the above-mentioned embodiment, but can be implemented with various modifications.

For example, in the above embodiment, the shaping pulse
Although it is necessary that PS _A and PS _B have a complementary relationship, this does not mean that complete complementarity is required; in the circuit configuration of the above embodiment,
It is fine as long as PS _A and PS _B do not become “1” at the same time.
There may be a moment when both are "0" at the same time.
However, this relationship depends on whether the logic used in the configuration of the drive circuit is positive logic or negative logic.
It also varies depending on the configuration of the logic circuit. 2
In short, the relationship required between the two shaping pulses can be established by performing a certain logical operation on the drive signal.
Any drive pulse may be used as long as it can obtain two drive pulses in which when one is "1", the other is always "0".

This also means that the logic circuits that can be used in the present invention can have various configurations.
For example, even if the NAND circuit in the above-mentioned embodiment is replaced with an OR circuit and an inverted version of the drive signal and shaping pulse is inputted thereto, the same drive pulse as in this embodiment can be obtained. Furthermore, an AND circuit may be used instead of the NAND circuit and inverter connected in series, and the same drive pulse can also be obtained. In addition, the inverter in the above 1 was removed, and the shaping pulse
Even by exchanging PS _A and PS _B , the same drive pulse as in the above embodiment can be obtained. However, in this case, it is required that the two shaping pulses do not become "0" at the same time.

As described above, in implementing the present invention, logic circuits having various configurations can be used. Although the above embodiment and modification examples have all been explained using positive logic, it is of course possible to use negative logic, and in that case, the configuration of the logic circuit, the driving signal, and the method of applying the shaping pulse It goes without saying that these can be modified in various ways, and there is no need to specifically explain them.

Further, in the above embodiment, an example of selecting a row of a CID element was described, but the present invention can be used when selecting a row of a solid-state image sensor in which a plurality of pixels are arranged two-dimensionally. It is not particularly limited to CID elements.

(f) Effects of the Invention As explained above, according to the present invention, the configuration of the drive circuit used for row selection of the solid-state image sensor can be simplified. Therefore, the present invention makes it easy to integrate the row selection drive circuit into an IC, and by using this IC, the solid-state imaging device in which the solid-state imaging device and the drive circuit are both mounted on the same substrate can be made smaller and simpler. and its manufacture becomes easy.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a circuit configuration diagram showing main parts of the drive circuit used in the above embodiment, and Fig. 3 explains the operation of the above embodiment. FIG. In the figure, 1 is a solid-state image sensor, 2 and 2' are drive circuit IC elements, both of which have an element arrangement that is a mirror image of each other, and 3 and 3' are shift registers built into the ICs 2 and 2'. 4 and 4' are also IC
2 and 2' are built-in NAND gates, 5 is a drive signal, 6 and 6' are the transmission directions of the drive signal 5, 7 and 7' are drive pulses, and PS _A and PS _B are shaping pulses.

Claims (1)

[Claims] 1 A solid-state image sensor having a plurality of pixels arranged in a two-dimensional array and mounted on a predetermined substrate is provided on both sides of the solid-state image sensor, corresponding to a shift register and each stage of the shift register. A driving IC element is provided which incorporates a predetermined logic circuit and whose element arrangement is a mirror image of each other, and the same driving signal is sent to each of the shift registers built into the two driving IC elements. The output obtained by performing a logical operation on the output obtained by inputting the input and the shaping pulse having a substantially complementary relationship to each other in the logic circuit built in the two driving ICs is outputted from the solid-state image sensor. A drive circuit for a solid-state imaging device, characterized in that the drive circuit is configured to use a drive pulse for selecting a row of elements.