JPH0348435A - Mounting structure of flip chip element - Google Patents
Mounting structure of flip chip elementInfo
- Publication number
- JPH0348435A JPH0348435A JP1182613A JP18261389A JPH0348435A JP H0348435 A JPH0348435 A JP H0348435A JP 1182613 A JP1182613 A JP 1182613A JP 18261389 A JP18261389 A JP 18261389A JP H0348435 A JPH0348435 A JP H0348435A
- Authority
- JP
- Japan
- Prior art keywords
- circuit pattern
- bump
- flip chip
- chip element
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/303—Assembling printed circuits with electric components, e.g. with resistors with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、絶縁性基板に形成した回路パターン上にフリ
ップチップ素子をフェイスダウンボンディングにより実
装するための構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure for mounting a flip chip element on a circuit pattern formed on an insulating substrate by face-down bonding.
〔従来の技術］
絶縁性基板に形成した導体による回路パターンに対する
ＩＣチップ等のチップ素子の実装方式として、チップ素
子の電極部を１電極毎に微細なワイヤにより回路パター
ンに接続するワイヤボンディングと、チップ素子の電極
部を同時に回路パターン上に接続するワイヤレスボンデ
ィングの２種がある。[Prior Art] As a method for mounting chip elements such as IC chips on a circuit pattern made of a conductor formed on an insulating substrate, wire bonding is used to connect the electrode portion of the chip element to the circuit pattern with fine wires for each electrode. There are two types of wireless bonding in which the electrode portions of chip elements are simultaneously connected to the circuit pattern.
このうちワイヤレスボンディングは、ワイヤボンディン
グと比較して、絶縁性基板上におけるチップ素子の実装
面積を小さく抑えることができると共に、接続の作業性
が良く、また接続強度も大きい等の長所を有している。Among these, wireless bonding has the advantages of being able to reduce the mounting area of chip elements on an insulating substrate, as well as being easier to work with and having greater connection strength than wire bonding. There is.
フリップチップボンディングは、このワイヤレスポンデ
ィングの代表的な方法で、フリップチップ素子をフエイ
スダウンボンディングによって回路パターンに接続する
ものであり、その実装構造の公知例としては、特開昭６
２−１６０２４８号公報，実開昭６２−１４２８４９号
公報，及び実開昭６２−７４３３３号等に開示されるも
のがある。Flip chip bonding is a typical method of wireless bonding, in which a flip chip element is connected to a circuit pattern by face down bonding.
Some of them are disclosed in Japanese Utility Model Application Publication No. 2-160248, Japanese Utility Model Application Publication No. 62-142849, and Japanese Utility Model Application Publication No. 62-74333.
第６図は従来のこの種のフリップチップ素子の実装構造
を示す側断面図で、図において１はセラミックまたはガ
ラスから成る絶縁性基板、２は該絶縁性基板１上に形成
した導体による回路パターン、３は該回路パターン２の
端部に設けた端子部である。FIG. 6 is a side cross-sectional view showing the mounting structure of a conventional flip-chip device of this type. In the figure, 1 is an insulating substrate made of ceramic or glass, and 2 is a circuit pattern formed by a conductor on the insulating substrate 1. , 3 are terminal portions provided at the ends of the circuit pattern 2.
前記回路パターン２は一層もしくは複数層の金属層ある
いは金属層と樹脂コーティング層等から成るが、ここで
は２ａ，２ｂの二層の金属層とすることで端子部３との
境に段差を設け、この段差により後述するバンプ溶着時
の溶融バンプの流出を防止するようにしている。The circuit pattern 2 is composed of one or more metal layers, or a metal layer and a resin coating layer, etc., but here, it is made of two metal layers 2a and 2b, so that a step is provided at the border with the terminal part 3, This level difference prevents the molten bump from flowing out during bump welding, which will be described later.
尚、前記金属層２ａ，２ｂは単一種類または複数種類の
金属膜により構威される。Note that the metal layers 2a and 2b are composed of a single type of metal film or a plurality of types of metal films.
４は例えばガラス膜やＳ ｉ ｓ Ｎ ４膜で保護され
たフリップチップ素子で、このフリップチップ素子４の
片面には図示しない電極部が設けられ、各電極部に例え
ば５０〜１００μの高さの半田や金等の組成によるバン
プ５が形成されている。Reference numeral 4 denotes a flip-chip element protected by, for example, a glass film or a SiS N 4 film, and an electrode part (not shown) is provided on one side of the flip-chip element 4. Bumps 5 made of solder, gold, or the like are formed.
以上の構或においてフリップチップ素子４を絶縁性基板
ｌの回路パターン２上に実装する場合、まず回路パター
ン２の端子部３に予備半田を施しておく。When mounting the flip chip element 4 on the circuit pattern 2 of the insulating substrate 1 in the above structure, preliminary soldering is first applied to the terminal portion 3 of the circuit pattern 2.
そして、フリップチップ素子４の電極面つまりバンプ５
を形或した面を下にして、このバンプ５を前記予備半田
された端子部３に載せて位置合わせし、端子部３にバン
プ５を押しつけたまま熱を加えてバンプ５を溶着するこ
とにより、フリップチップ素子４を回路パターン２に電
気的に接続する。Then, the electrode surface of the flip chip element 4, that is, the bump 5
With the shaped surface facing down, place this bump 5 on the pre-soldered terminal part 3, align it, and apply heat while pressing the bump 5 to the terminal part 3 to weld the bump 5. , the flip chip device 4 is electrically connected to the circuit pattern 2.
しかしながら、上述した従来の実装構造では、バンプを
溶着するときにその溶融バンプの流出を防止するための
段差を回路パターンに形或するため、回路パターンを多
層に形成したり樹脂でコーティングする等の製造工程を
必要とし、その分製造コストがかかるという問題があっ
た。However, in the conventional mounting structure described above, in order to form steps in the circuit pattern to prevent the melted bumps from flowing out when welding the bumps, it is necessary to form the circuit pattern in multiple layers or coat it with resin. There is a problem in that a manufacturing process is required and the manufacturing cost increases accordingly.
また、端子部に形成された段差は回路パターンの延在方
向への溶融バンプの流出は阻止できるものの、隣接して
いる回路パターン方向への流出は阻止できないため、微
細なピッチで形成されている回路パターンの濡れ性によ
り溶融バンプが広がり、その結果フリップチップ素子が
傾いて実装される等の現象が生じて信頼性の低下を招く
だけでなく、回路パターンのショートを発生するという
問題もあった。In addition, although the steps formed in the terminal part can prevent the molten bump from flowing in the direction in which the circuit pattern extends, they cannot prevent the molten bump from flowing in the direction of the adjacent circuit pattern, so they are formed at a fine pitch. The wettability of the circuit pattern causes the melted bumps to spread, resulting in phenomena such as the flip-chip device being mounted at an angle, which not only causes a decrease in reliability, but also causes short circuits in the circuit pattern. .
更に、上述した従来技術では、回路パターンに対するフ
リップチップ素子の位置決めを各回路パターン上に直接
ハンブを載せることで行っているため、バンプ間のピッ
チが狭くなると回路パターン上にバンブが正確に載って
いるかどうかの判断が難しく、そのため位置決めに時間
がかかるという問題もあった。Furthermore, in the above-mentioned conventional technology, the flip-chip element is positioned with respect to the circuit pattern by placing bumps directly on each circuit pattern, so if the pitch between the bumps becomes narrower, the bumps cannot be accurately placed on the circuit pattern. There was also the problem that it was difficult to judge whether or not there was a vehicle, and it took a long time to determine the position.
本発明はこれらの問題を解決するためになされたもので
、製造コストの低減，フリップチップ素子実装の信頼性
の向上．及びショートの発生防止を図ることができると
共に、回路パターンに対するフリップチップ素子の位置
決めを短時間で正確に行うことが可能なフリップチップ
素子の実装構造を実現することを目的とするものである
。The present invention was devised to solve these problems, and it aims to reduce manufacturing costs and improve the reliability of flip-chip device mounting. It is an object of the present invention to realize a mounting structure for a flip chip element that can prevent the occurrence of short circuits and can accurately position the flip chip element with respect to a circuit pattern in a short time.
この目的を達或するため、本発明はフリップチップ素子
に設けたバンプを絶縁性基板上に形成した回路パターン
に溶着して電気的接続を得るフリップチップ素子の実装
構造において、耐熱性と電気的絶縁性を有するシート状
の熱応力緩和部材を絶縁性基板の回路パターン上に配置
すると共に、この熱応力緩和部材にバンプ規制孔を設け
たものである。In order to achieve this object, the present invention provides a mounting structure for a flip chip device in which electrical connection is achieved by welding bumps provided on the flip chip device to a circuit pattern formed on an insulating substrate. A sheet-shaped thermal stress relieving member having insulating properties is placed on a circuit pattern of an insulating substrate, and bump regulating holes are provided in the thermal stress relieving member.
（作用〕
上述した構成を有する本発明は、フリップチップ素子に
設けたパンプの位置をバンプ規制孔でガイドして絶縁性
基板の回路パターンに対するフリップチップ素子の位置
決めを行うと共に、このバンプを回路パターンに溶着す
る際、溶融したバンプの流出を熱応力緩和部材のバンプ
規制孔により防止し、各バンブを対応する回路パターン
に溶着してフリップチップ素子を実装する。(Function) The present invention having the above-described configuration positions the flip chip element with respect to the circuit pattern of the insulating substrate by guiding the position of the bump provided on the flip chip element with the bump regulation hole, and also positions the bump provided on the flip chip element with respect to the circuit pattern of the insulating substrate. When welding the bumps to the substrate, the bump regulation holes of the thermal stress relaxation member prevent the melted bumps from flowing out, and each bump is welded to the corresponding circuit pattern to mount the flip chip device.
従ってこれによれば、従来のように絶縁性基板の回路パ
ターンに段差を形或する必要がなくなるので、回路バタ
・−ンを多層に形成したり樹脂でコーティングする等の
製造工程が不要になり、そして熱応力緩和部材は回路パ
ターンを多層に形成したり樹脂でコーティングする等の
場合に較べて容易かつ安価に形成できるので、製造コス
トの低減が可能となる．
また、前記熱応力緩和部材のバンプ規制孔は回路パター
ンの延在方向のみでなく隣接している回路パターン方向
への溶融バンプの流出を確実に阻止できるため、フリッ
プチップ素子が傾いて実装されることがなくなり、実装
の信頼性を向上できると共に、回路パターンのショート
の発生も防止することができる。Accordingly, this eliminates the need to form steps in the circuit pattern of the insulating substrate as in the past, and eliminates the need for manufacturing processes such as forming the circuit pattern in multiple layers or coating it with resin. Thermal stress relaxation members can be formed more easily and inexpensively than in the case of forming circuit patterns in multiple layers or coating with resin, so manufacturing costs can be reduced. In addition, the bump regulating holes of the thermal stress relaxation member can reliably prevent the melted bumps from flowing out not only in the extending direction of the circuit pattern but also in the direction of the adjacent circuit pattern, so that the flip chip element is mounted at an angle. As a result, the reliability of mounting can be improved, and the occurrence of short circuits in the circuit pattern can also be prevented.
更に、フリップチップ素子のバンブを熱応力緩和部材の
バンブ規制孔にガイドすることができるため、回路パタ
ーンに対するフリップチップ素子の位置決めを容易かつ
短時間で正確に行うことも可能になる。Furthermore, since the bumps of the flip chip element can be guided to the bump regulating holes of the thermal stress relaxation member, it is possible to easily and accurately position the flip chip element with respect to the circuit pattern.
以下図面を参照して実施例を説明する。 Examples will be described below with reference to the drawings.
第ｌ図は本発明によるフリップチップ素子の実装構造の
第１の実施例を示す斜視図、第２図は第１図のＡ−Ａ線
断面図、第３図（ａ）〜（Ｃ）は各構威要素の詳細を示
す斜視図である。FIG. 1 is a perspective view showing a first embodiment of a mounting structure for a flip-chip device according to the present invention, FIG. 2 is a sectional view taken along the line A-A in FIG. 1, and FIGS. FIG. 3 is a perspective view showing details of each structural element.
第１図及び第２図において６はセラミックまたはガラス
から或る絶縁性基板、７は例えばガラス膜やＳ ｉ ３
Ｎ ４膜で保護されたフリップチップ素子、８は少な
くともバンプの溶融温度に耐えられるだけの耐熱性を有
すると共に電気的絶縁性を有する薄いテープあるいはフ
ィルム等から或るシート状の熱応力緩和部材である。In FIGS. 1 and 2, 6 is an insulating substrate made of ceramic or glass, and 7 is, for example, a glass film or Si 3
The flip-chip element 8 is protected by an N4 film, and 8 is a sheet-shaped thermal stress relaxation member made of a thin tape or film that has heat resistance sufficient to withstand at least the melting temperature of the bumps and has electrical insulation properties. be.
前記絶縁性基板６上には第３図（Ｃ）に明示したように
単一の金属層により所定形状の回路パターン９が形成さ
れており、各々の回路パターン９の端部（破線で囲んだ
部分）はフリップチップ素子７を実装するための端子部
９ａとなっている。As clearly shown in FIG. 3(C), a circuit pattern 9 of a predetermined shape is formed on the insulating substrate 6 by a single metal layer. portion) serves as a terminal portion 9a for mounting the flip chip element 7.
また、第３図（ａ）に示したようにフリップチップ素子
７の片面にはその電極上に略半球形のバンプｌＯが前記
端子部９ａに対応するように形成されており、更に熱応
力緩和部材８には第３図（ｂ）に示したように前記バン
プ９と対応する位置にテーパ状のバンブ規制孔ｌ１が設
けられ、かつ四隅には位置決めマーク１２が設けてあっ
て、この位置決めマーク１２上にフリップチップ素子７
の各角部を一致させることにより回路パターン９に対す
る位置決めが行えるようになっている．
尚、前記バンブ規制孔１１はレーザ加工，放電加工，錐
状のドリルによる孔あけ加工，またはモールド威形加工
等により設けられ、その回路パターン９側となる部分の
径は、回路パターン９の端子部９ａの幅以下となるよう
に設定されている。Further, as shown in FIG. 3(a), a substantially hemispherical bump 1O is formed on one side of the flip chip element 7 on its electrode so as to correspond to the terminal portion 9a, and furthermore, the bump lO is formed on one side of the flip chip element 7 so as to correspond to the terminal portion 9a. As shown in FIG. 3(b), the member 8 is provided with a tapered bump regulating hole l1 at a position corresponding to the bump 9, and positioning marks 12 are provided at the four corners. Flip chip device 7 on 12
By matching each corner of the circuit pattern 9, positioning with respect to the circuit pattern 9 can be performed. The bump regulating hole 11 is provided by laser machining, electric discharge machining, drilling with a conical drill, mold shaping, etc., and the diameter of the portion facing the circuit pattern 9 is equal to the terminal of the circuit pattern 9. The width is set to be less than or equal to the width of the portion 9a.
以上の構或においてフリップチップ素子７を絶縁性基板
６の回路パターン９上に実装する場合、まず回路パター
ン９の端子部９ａに予備半田を施しておき、そして熱応
力緩和部材８を第３図（Ｃ）の破線で囲んだ部分に載せ
て、各バンプ規制孔１１が回路パターン９の端子部９ａ
の直上に載るように目視により位置決めする。When mounting the flip chip element 7 on the circuit pattern 9 of the insulating substrate 6 in the above structure, preliminary soldering is first applied to the terminal portion 9a of the circuit pattern 9, and then the thermal stress relaxation member 8 is attached as shown in FIG. Place it on the part surrounded by the broken line in (C) so that each bump regulation hole 11 is connected to the terminal part 9a of the circuit pattern 9.
Visually position it so that it is placed directly above it.
次に、フリップチップ素子７の電極面つまりバンプ１０
を形成した面を下にして熱応力緩和部材８上に載せ、こ
のときフリップチップ素子７の各角部を位置決めマーク
１２上に一致させるようにする。Next, the electrode surface of the flip chip element 7, that is, the bump 10
The flip chip element 7 is placed on the thermal stress relieving member 8 with the surface thereof facing down, and at this time each corner of the flip chip element 7 is aligned with the positioning mark 12.
これにより各バンプ規制孔ｌ１にそれぞれ対応するバン
ブ１０が位置決めされ、しかもバンプ規制孔１１は前記
の如くテーバ状に形成されているため、バンプ１０の下
部はこのテーパによりガイドされてパンプ規制孔１１に
スムーズに入り込み、これによりフリップチップ素子７
の位置決めが容易かつ正確に行われる。As a result, the bumps 10 corresponding to each bump regulation hole l1 are positioned, and since the bump regulation hole 11 is formed in a tapered shape as described above, the lower part of the bump 10 is guided by this taper, and the bump regulation hole 11 is guided by the taper. The flip chip element 7 smoothly enters the
positioning is performed easily and accurately.
この状態で熱を加えてバンプ１０を溶融すると、溶融バ
ンプがバンプ規制孔ｌｌ内を満たし、端子部９ａに溶着
してフリップチップ素子７が回路パターン９に電気的に
接続される。When the bumps 10 are melted by applying heat in this state, the molten bumps fill the inside of the bump regulation holes ll and are welded to the terminal portions 9a, thereby electrically connecting the flip chip element 7 to the circuit pattern 9.
尚、このフリップチップ素子７の実装の際、放熱性の面
から熱応力緩和部材８とフリップチップ素子７との間に
第２図に示すギャップΔ・Ｘが得られるようにすること
が望ましく、そのため予めバンプｌＯの高さをこのギャ
ップΔＸが得られるように考慮して設定する。Incidentally, when mounting this flip-chip element 7, it is desirable to obtain a gap Δ·X shown in FIG. 2 between the thermal stress relaxation member 8 and the flip-chip element 7 in terms of heat dissipation. Therefore, the height of the bump lO is set in advance with consideration given to obtaining this gap ΔX.
第４図は本発明の第２の実施例を示す側断面図で、この
実施例は同図（ａ）に示すように熱応力緩和部材８に設
けられるバンプ規制孔ｌ１の形状を鼓形するこにより、
同図（ｂ）に示したようにバンプｌＯを溶融してフリッ
プチップ素子７を回路パターン９の端子部９ａに電気的
に接続した後にバンプの剥離等が発生しにくい構造とな
るようにしたものである．
また、この実施例ではフリップチップ素子７の電極部９
ａに予め所定の厚みを持たせ、これにより熱応力緩和部
材８とフリップチップ素子７との間に常に安定した前記
ギャップΔＸを得られるようにしている。FIG. 4 is a side sectional view showing a second embodiment of the present invention, and in this embodiment, the shape of the bump regulation hole l1 provided in the thermal stress relaxation member 8 is hourglass-shaped, as shown in FIG. Due to this,
As shown in Figure (b), the bump lO is melted to create a structure in which the bumps are less likely to peel off after the flip chip element 7 is electrically connected to the terminal portion 9a of the circuit pattern 9. It is. Further, in this embodiment, the electrode portion 9 of the flip chip element 7
a has a predetermined thickness in advance, so that a stable gap ΔX can always be obtained between the thermal stress relaxation member 8 and the flip chip element 7.
第５図は本発明の第３の実施例を示す側断面図で、この
実施例はフリップチップ素子７の電極部９ａに予め所定
の厚みを持たせると共に、熱応力緩和部材８のバンプ規
制孔１１の形状を円柱形としたもので、第２の実施例と
同様の結果が得られるものである。FIG. 5 is a side sectional view showing a third embodiment of the present invention. In this embodiment, the electrode portion 9a of the flip chip element 7 has a predetermined thickness, and the bump regulation hole of the thermal stress relaxation member 8 11 is cylindrical in shape, and the same results as in the second embodiment can be obtained.
尚、上述した実施例において、熱応力緩和部材８の位置
決めマークは必ずしも必要なものではなく、バンプ規制
孔１ｌによりバンプｌＯをガイドするだけで回路パター
ン９に対するフリップチップ素子７の位置決めを行うこ
とも可能である。In the above-described embodiment, the positioning mark of the thermal stress relaxation member 8 is not necessarily necessary, and the flip chip element 7 may be positioned with respect to the circuit pattern 9 by simply guiding the bump IO through the bump regulation hole 1l. It is possible.
以上説明したように本発明は、フリップチップ素子に設
けたバンプを絶縁性基板上に形成した回路パターンに溶
着して電気的接続を得るフリップチップ素子の実装構造
において、耐熱性と電気的絶縁性を有するシート状の熱
応力緩和部材を絶縁性基板の回路パターン上に配置する
と共に、この熱応力緩和部材にバンブ規制孔を設けて、
このパンプ規制孔によりバンプの位置をガイドすること
で絶縁性基板の回路パターンに対するフリップチップ素
子の位置決めを行うと共に、このバンプを回路パターン
に溶着する際、溶融したバンプの流出を熱応力緩和部材
のバンプ規制孔により防止するようにしている．
従ってこれによれば、従来のように絶縁性基板の回路パ
ターンに段差を形成する必要がなくなるので、回路パタ
ーンを多層に形成したり樹脂でコーティングする等の製
造工程が不要になり、そして熱応力緩和部材は回路パタ
ーンを多層に形成したり樹脂でコーティングする等の場
合に較べて容易且つ安価に形或できるので、製造コスト
の低減を計れるという効果が得られる。As explained above, the present invention provides a mounting structure for a flip chip element in which electrical connection is achieved by welding bumps provided on the flip chip element to a circuit pattern formed on an insulating substrate. A sheet-like thermal stress relieving member having the following properties is placed on the circuit pattern of the insulating substrate, and a bump regulating hole is provided in the thermal stress relieving member.
By guiding the position of the bump with this pump regulation hole, the flip chip element is positioned with respect to the circuit pattern of the insulating substrate, and when the bump is welded to the circuit pattern, the melted bump is prevented from flowing out by the thermal stress relaxation member. Bump regulation holes are used to prevent this. Therefore, according to this, there is no need to form steps in the circuit pattern of an insulating substrate as in the past, so manufacturing processes such as forming the circuit pattern in multiple layers or coating it with resin are no longer necessary, and thermal stress Since the relaxation member can be formed more easily and at a lower cost than in the case of forming a circuit pattern in multiple layers or coating with resin, the effect of reducing manufacturing costs can be obtained.
また、前記熱応力緩和部材のバンブ規制孔は回路パター
ンの延在方向のみでなく隣接している回路パターン方向
への溶融バンプの流出も確実に阻止できるため、フリッ
プチップ素子が傾いて実装されることがなくなり、実装
の信頼性を向上できると共に、回路パターンのショート
を発生も防止することができるという効果も得られる．
更に、フリップチップ素子のバンプを熱応力緩和部材の
バンプ規制孔によりガイドすることができるため、回路
パターンに対するフリンプチップ素子の位置決めを容易
かつ短時間で正確に行うことも可能になるという効果も
得られる．In addition, the bump regulating holes of the thermal stress relaxation member can reliably prevent melted bumps from flowing out not only in the extending direction of the circuit pattern but also in the direction of adjacent circuit patterns, so that the flip chip device can be mounted at an angle. This eliminates the problem, which improves the reliability of mounting and also prevents short circuit patterns from occurring.
Furthermore, since the bumps of the flip chip element can be guided by the bump regulation holes of the thermal stress relaxation member, the flip chip element can be easily and accurately positioned with respect to the circuit pattern. ．．
第１図は本発明によるフリップチップ素子の実装構造の
第ｌの実施例を示す斜視図、第２図は第１図のＡ−Ａ線
断面図、第３図は第１の実施例における各構成要素の詳
細を示す斜視図、第４図は第２の実施例を示す側断面図
、第５図は第３の実施例を示す側断面図、第６図は従来
例を示す側断面図である。
６：絶縁性基板
７：フリップチップ素子
８：熱応力緩和部材
９：回路パターン
９ａ：端子部
１０：バンプ
１１：バンプ規制孔
１２：位置決めマークFIG. 1 is a perspective view showing a first embodiment of a flip-chip device mounting structure according to the present invention, FIG. 2 is a sectional view taken along line A-A in FIG. 1, and FIG. FIG. 4 is a side sectional view showing the second embodiment; FIG. 5 is a side sectional view showing the third embodiment; FIG. 6 is a side sectional view showing the conventional example. It is. 6: Insulating substrate 7: Flip chip element 8: Thermal stress relaxation member 9: Circuit pattern 9a: Terminal portion 10: Bump 11: Bump regulation hole 12: Positioning mark
Claims (1)
上に形成した回路パターンに溶着して電気的接続を得る
フリップチップ素子の実装構造において、 耐熱性と電気的絶縁性を有するシート状の熱応力緩和部
材を絶縁性基板の回路パターン上に配置すると共に、こ
の熱応力緩和部材に前記バンプのガイドと溶融したバン
プの流出を防止するためのバンプ規制孔を設けたことを
特徴とするフリップチップ素子の実装構造。(1) In the mounting structure of a flip-chip device in which electrical connection is achieved by welding the bumps provided on the flip-chip device to a circuit pattern formed on an insulating substrate, a heat-resistant sheet with heat resistance and electrical insulation properties is used. A flip chip characterized in that a stress relaxation member is disposed on the circuit pattern of an insulating substrate, and the thermal stress relaxation member is provided with bump guides and bump regulation holes for preventing melted bumps from flowing out. Mounting structure of the element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1182613A JPH0348435A (en) | 1989-07-17 | 1989-07-17 | Mounting structure of flip chip element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1182613A JPH0348435A (en) | 1989-07-17 | 1989-07-17 | Mounting structure of flip chip element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0348435A true JPH0348435A (en) | 1991-03-01 |
Family
ID=16121352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1182613A Pending JPH0348435A (en) | 1989-07-17 | 1989-07-17 | Mounting structure of flip chip element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0348435A (en) |
Cited By (8)
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|---|---|---|---|---|
| JPH08250835A (en) * | 1995-03-10 | 1996-09-27 | Nec Corp | Method for mounting lsi package having metallic bump |
| US5683942A (en) * | 1994-05-25 | 1997-11-04 | Nec Corporation | Method for manufacturing bump leaded film carrier type semiconductor device |
| US5883438A (en) * | 1995-09-22 | 1999-03-16 | Lg Semicon Co., Ltd. | Interconnection structure for attaching a semiconductor to substrate |
| EP0827191A3 (en) * | 1996-08-20 | 1999-12-29 | Nec Corporation | Semiconductor device mounting structure |
| EP0917195A4 (en) * | 1997-01-17 | 2000-03-22 | Seiko Epson Corp | ELECTRONIC COMPONENT, SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, PRINTED BOARD, AND ELECTRONIC EQUIPMENT |
| US6124634A (en) * | 1996-03-07 | 2000-09-26 | Micron Technology, Inc. | Micromachined chip scale package |
| JP2002313840A (en) * | 2001-04-17 | 2002-10-25 | Matsushita Electric Ind Co Ltd | Semiconductor element mounting board and method of manufacturing the same |
| JP2009016399A (en) * | 2007-06-29 | 2009-01-22 | Toshiba Corp | Printed circuit board, electronic component mounting method, and electronic apparatus |
-
1989
- 1989-07-17 JP JP1182613A patent/JPH0348435A/en active Pending
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5683942A (en) * | 1994-05-25 | 1997-11-04 | Nec Corporation | Method for manufacturing bump leaded film carrier type semiconductor device |
| US5905303A (en) * | 1994-05-25 | 1999-05-18 | Nec Corporation | Method for manufacturing bump leaded film carrier type semiconductor device |
| JPH08250835A (en) * | 1995-03-10 | 1996-09-27 | Nec Corp | Method for mounting lsi package having metallic bump |
| US5883438A (en) * | 1995-09-22 | 1999-03-16 | Lg Semicon Co., Ltd. | Interconnection structure for attaching a semiconductor to substrate |
| US6358833B1 (en) | 1996-03-07 | 2002-03-19 | Micron Technology, Inc. | Method of fabricating a micromachined chip scale package |
| US6124634A (en) * | 1996-03-07 | 2000-09-26 | Micron Technology, Inc. | Micromachined chip scale package |
| US6207548B1 (en) * | 1996-03-07 | 2001-03-27 | Micron Technology, Inc. | Method for fabricating a micromachined chip scale package |
| US6407451B2 (en) | 1996-03-07 | 2002-06-18 | Micron Technology, Inc. | Micromachined chip scale package |
| EP0827191A3 (en) * | 1996-08-20 | 1999-12-29 | Nec Corporation | Semiconductor device mounting structure |
| EP0917195A4 (en) * | 1997-01-17 | 2000-03-22 | Seiko Epson Corp | ELECTRONIC COMPONENT, SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, PRINTED BOARD, AND ELECTRONIC EQUIPMENT |
| US6323542B1 (en) | 1997-01-17 | 2001-11-27 | Seiko Epson Corporation | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
| US6518651B2 (en) | 1997-01-17 | 2003-02-11 | Seiko Epson Corporation | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
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| US7307351B2 (en) | 1997-01-17 | 2007-12-11 | Seiko Epson Corporation | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
| US7485973B2 (en) | 1997-01-17 | 2009-02-03 | Seiko Epson Corporation | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
| US7755205B2 (en) | 1997-01-17 | 2010-07-13 | Seiko Epson Corporation | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
| US7888177B2 (en) | 1997-01-17 | 2011-02-15 | Seiko Epson Corporation | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
| US8399999B2 (en) | 1997-01-17 | 2013-03-19 | Seiko Epson Corporation | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
| JP2002313840A (en) * | 2001-04-17 | 2002-10-25 | Matsushita Electric Ind Co Ltd | Semiconductor element mounting board and method of manufacturing the same |
| JP2009016399A (en) * | 2007-06-29 | 2009-01-22 | Toshiba Corp | Printed circuit board, electronic component mounting method, and electronic apparatus |
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