JPH0348521B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a control circuit for a system that controls a predetermined system A as shown in FIG.

More specifically, when the automatic control circuit section C that controls a predetermined system A malfunctions, if this malfunction does not recover immediately, this malfunction is promptly detected, and when this malfunction is not repaired, this malfunction is detected immediately. This invention relates to a system control circuit that automatically switches the system A so that it can be operated manually.

[Background technology]

Conventionally, in order to control large systems, various measures have been taken to prevent malfunctions due to noise and the like. For example, as shown in FIG. 1, a central processing unit (central processing unit) that operates a program counter in accordance with a signal E from a clock pulse generator of an automatic control circuit section and retrieves command signals from a predetermined memory. (hereinafter referred to as CPU) shows a system in which the CPU outputs a signal F to reset the program counter after a predetermined period of time has elapsed, but if the CPU is broken, it cannot be reset.

[Purpose of the invention]

The present invention has been made in view of such conventional drawbacks, and it is possible to reset the system after a predetermined period of time even if the control circuit becomes uncontrollable for a short period of time due to noise, or to completely reset the CPU. The purpose is to avoid a complete loss of control of the system by automatically switching to manual operation in the event of a breakdown.

[Disclosure of the invention]

The present invention will be described in detail below based on one embodiment thereof.

In the figure, A is a controlled system. B is an input signal. C is an automatic control circuit section. D
is the manual operation circuit section. X is automatic control circuit section C
and manual operation circuit section D. The automatic control circuit section C consists of a CPU section 1 and a detection section 2, as shown in FIG. The CPU section 1 is the CPU 11
This CPU 11 outputs an instruction cycle end signal 12 every time one instruction cycle ends according to a predetermined program, and this instruction cycle end signal 12
A high level signal H and a low level signal L are outputted at equal intervals by a conversion circuit 13 such as a flip-flop.
and output from CPU section 1. 2 is a detection section. This detection section 2 includes a first counter section 21, a second counter section 22, and the first and second counter sections 21, 2 to detect the arrival of the instruction cycle end signal outputted from the CPU section 1.
OR gate 23 for outputting a reset signal no matter which side of the second output
and an oscillation circuit 24 for use as a reference for the detection time interval of the second counter sections 21 and 22, and a third counter section 2 for switching between automatic control and manual operation.
5 and a conversion circuit 26 for converting the signal from the OR gate 23 into a one-shot signal. The configuration of the first and second counter sections 21 and 22 includes a first AND gate 211 and a first counter 212, and the AND gate 21 of the body 1
The input of 1 is a signal 2111 from the oscillation circuit 24 for use as a reference for the detection time interval and a signal 131 obtained by converting the instruction cycle end signal by the conversion circuit 13.
Enter . The second counter section 22
It is composed of an AND gate 221, a second counter 222, and a NOT gate 223 for converting the input signal to the second AND gate 221.
The second counter unit 22 detects the CPU unit 1 when the instruction cycle end signal converted by the conversion circuit 13 is at a signal level opposite to that of the first AND gate 211 of the first counter unit 21. A NOT gate 223 is provided in order to be able to detect even when a failure occurs.

The CPU unit 1 controls the system according to a predetermined program based on input signals not shown, and when one instruction cycle is completed, it outputs an instruction cycle end signal 12, indicating the end of this instruction cycle. The signal 12 is converted into a high-level and low-level signal at equal intervals by a conversion circuit 13 (see FIG. 3B) and outputted from the CPU section 1. When the instruction cycle end signal arrives within a predetermined time interval, that is, when the CPU unit is operating normally, the first or second counter unit counter 212,
Since the counter 222 is configured to be reset by the input signal from the conversion circuit of the counter section on the opposite side, the first and second counter sections 2
No output signal is output from 1 and 22.

However, if there is some kind of failure in the CPU section 1 and the instruction cycle end signal is not output from the CPU 11, the output of the conversion circuit 13 remains stopped at both high and low levels. When the output from the conversion circuit is at a low level in this state, the second counter section 22 outputs an output signal (see FIG. 3D). This is because the signal inverted by the NOT gate 223 is continuously outputted to the second AND gate 221 and exceeds the time interval reference of the counter 222, so the signal from the second counter section 22 [see FIG. 3 D] is output. Get out. This signal is OR
The signal is converted into a one-shot signal by a one-shot signal conversion circuit 26 via a gate 23 (see FIG. 3-E), and outputted as a reset signal (see FIG. 3-A and α) for resetting the CPU 1. When the CPU unit 1 returns to a normal state by this reset signal, an instruction cycle end signal is output again [see FIG. In addition, the CPU section 1 is reset by the reset signal.
If the output signal does not return to the normal state, the output signal of the conversion circuit continues to maintain the same signal output level, so the third counter section 23 outputs an output signal (see FIG. 3). Note that 251 is a switching element, 252 is an AND gate, and 523 is a counter.

〔Effect of the invention〕

The present invention includes an automatic control circuit unit that operates according to a predetermined program based on input signals to control a predetermined system, and a system that manually controls the predetermined system when the automatic control circuit unit malfunctions. In the system control circuit device, the automatic control circuit unit sequentially outputs control signals according to a predetermined program based on at least input signals, and executes one command cycle according to the predetermined program. An instruction cycle end signal is now output to indicate completion.
A central processing unit 1 consisting of a CPU 11 and a conversion circuit 13 that converts an instruction cycle end signal from the CPU 11 into ON and OFF signals at equal intervals and outputs the signals.
The command cycle end signal outputted from the central processing unit 1 is inputted to the first counter 212 as the product of the signal from the separately provided transmitting circuit 24, and the signal obtained by inverting the command cycle end signal and the The signal is input to the second counter 222 as a product of the signal from the transmitting circuit 24, and the first counter is reset by the inverted signal of the instruction cycle end signal, and the second counter is reset by the instruction cycle end signal. The outputs of the first and second counters are outputted through the OR gate 23 to detect that the CPU 11 has stopped for a certain period of time or more, and to convert the output of the OR gate 23 into a one-shot signal. The CPU 11 is reset via the conversion circuit 26, and the signal from the OR gate 23 and the oscillation circuit 2 are
4 as the product of the third counter 25 with the signal from
3 and switches from automatic to manual by the output of this third counter 253. Therefore, when the automatic control circuit 2 malfunctions due to noise etc. However, it is possible to recover at approximately the same time interval as the end time of one instruction cycle, and in a situation where the central processing unit 1 is destroyed, the automatic control circuit 2 automatically transfers the manual operation circuit. Since the switching is performed automatically, it is possible to prevent a situation where the system becomes completely uncontrollable.

Further, since the structure of the present invention is adopted, the object can be achieved with an extremely simple structure.

[Brief explanation of drawings]

The drawings are for explaining the present invention, and FIG. 1 is an electric circuit diagram showing a conventional example of the present invention. 2 to 4 are drawings for explaining the present invention, in which FIG. 2 is an electric circuit diagram of the present invention, and FIG.
Time chart diagram of the signals of the electrical circuit diagram shown in the figure,
Figure 4 is a block diagram showing the system of the present invention. A...Controlled system, B...Input signal, C...
...Automatic control circuit section, D...Manual operation circuit section, 1...
...CPU section, 11...CPU, 12...Instruction cycle end signal, 13...Conversion circuit, 131...
Output signal from CPU section, 2...Detection circuit section, 2
DESCRIPTION OF SYMBOLS 1... First counter section, 22... Second counter section, 23... OR gate, 24... Oscillation circuit, 25... Third counter section, 26... One shot signal conversion circuit, 211, 221 ,252
...AND gate, 212, 222, 253...
Counter, 223...NOT gate, 251...
...Switching element, 252...Relay.

Claims (1)

[Scope of Claims] 1. An automatic control circuit unit that operates according to a predetermined program based on input signals to control a predetermined system, and an automatic control circuit unit that controls a predetermined system when the automatic control circuit unit malfunctions. In a system control circuit device including a manually operated circuit unit for manual control, the automatic control circuit unit sequentially outputs control signals according to a predetermined program using at least an input signal, and outputs one control signal according to the predetermined program. A CPU that outputs an instruction cycle end signal indicating that the instruction cycle has ended;
A central processing unit consisting of a conversion circuit that converts the instruction cycle end signal from the CPU into ON and OFF signals at equal intervals and outputs the same, and an instruction cycle end signal output from this central processing unit are provided separately. input to the first counter 212 as a product of the signal from the transmitting circuit 24;
The product of the inverted instruction cycle end signal and the signal from the transmitting circuit is input to the second counter 222, and the first counter is reset by the inverted signal of the instruction cycle end signal, and the second counter is reset by the instruction cycle end signal, and the outputs of the first and second counters are outputted via an OR gate to detect that the CPU has stopped for a certain period of time or more. The CPU is reset through a conversion circuit that converts the output of this OR gate into a one-shot signal, and the product of this OR gate signal and the signal from the oscillation circuit is input to a third counter, and the output of this third counter is A system control circuit device including a detection section that allows switching from automatic to manual mode.