JPH0348961A - Data transfer system - Google Patents

Abstract

PURPOSE:To shorten the data transfer time by securing a constitution where a data transfer unit outputs the prescribed lower rank bit information on the address of a memory and outputs the higher rank bit information via a transmission/reception address designation queue to designate each address. CONSTITUTION:When a data transfer unit 3 receives the data from other devices via a communication bus 11, this fact is informed to a CPU 1 via a control bus 10c. The unit 3 receives the access right and controls a selector 6. Then the unit 3 selects the output of a reception address designation queue 4 and outputs the prescribed higher rank bit value of the designated address of a memory 2 to an address bus 10b. The prescribed lower rank bit value is outputted to the bus 10b from the unit 3 and increased one by one from 0 in accordance with the number of bytes of the transferred data. Thus the reception data received from the bus 11 is transferred to an area of the memory 2 designated by the unit 1 from the unit 3. An approximately same action as a reception mode is available also in a transmission mode. As a result, the data processing load of the unit 1 can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer system in a processor device.

[Conventional technology]

The conventional data transfer method for processor devices is to set up a small-capacity, fixed-address dedicated area for sending and receiving in memory, and the central processing unit transfers data between its own work area and this area for sending and receiving. There is a method in which a data transfer unit performs data transfer processing between this sending/receiving area and other devices.

[Problem to be solved by the invention]

The above-described conventional data transfer method uses a small fixed transmission/reception area as an intermediary, which increases the data processing load on the central processing unit and has the disadvantage that it takes time to send and receive data to and from other devices.

An object of the present invention is to provide a data transfer method that reduces the data processing load on the central processing unit of a processor device and reduces the time required for transmitting and receiving data with other devices.

[Means to solve the problem]

The data transfer method of the present invention includes a central processing unit that performs data processing, a memory that stores data, and a data transfer unit that is connected to other devices via a communication bus,
In a data transfer method for a processor device in which the data transfer unit transmits and receives data between the memory and another device under the control of the central processing unit, a transmission address designation queue stores predetermined upper bit information of the address of the memory. and a receive addressing queue,
When the central processing unit transmits to another device,
Predetermined upper bit information of the address of the data transmission area specifying the use in the memory is set in the order of use in the transmission address specification queue, and when receiving from another device, the use in the memory is specified. Predetermined upper bit information of the address of the data reception area is set in the order of use in the reception address designation queue, and when transmitting or receiving data between the memory and another device,
The data transfer unit outputs predetermined lower bit information of the address of the memory, outputs predetermined upper bit information of the address from a transmission address designation queue or a reception address designation queue, respectively, and transfers information to each of the data transmission area or reception area. It is characterized by specifying an address.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a processor device according to an embodiment of the present invention. The processor device according to the present embodiment includes a central processing unit 1 for processing data, a memory 2 for storing data, and a communication bus 11. a data transfer unit 3 that transfers data between another device and the memory 2 via the memory 2; a reception address designation queue 4 that specifies a predetermined upper bit of the reception data storage address on the memory 2; and a transmission data storage address on the memory 2. A transmit address designation queue 5 that specifies a predetermined upper bit of the transmit address designation queue 5, a selector 6 that selects and outputs the output of the receive address designation queue 4 and the output of the transmission address designation queue 5, and a processor bus 10 (data bus) that connects each of the above parts. 10a, an address bus 10b, and a control bus 10c).

Next, the operation when receiving data from another device will be explained.

The central processing unit 1 specifies in advance a plurality of arbitrary areas on the memory 2 to be used for reception, and sends them via the data bus 10a and the control bus 10c in the order in which predetermined upper bit values of the specified addresses are used. , this predetermined upper bit value set in the reception address specification queue 4 is:
This is an upper bit value indicating a fixed value among address values corresponding to the maximum number of bytes of data transferred per data transfer.

When the data transfer unit 3 receives data from another device via the communication bus 11, it notifies the central processing unit 1 via the control bus 10c. When the central processing unit 1 receives this notification, it hands over all access rights to the processor bus 10 and notifies the data transfer unit 3 to that effect.

The data transfer unit 3, which has received the access right to the processor bus 10, controls the selector 6 to select the output of the reception address designation queue 4, and outputs a predetermined upper bit value of the designated address of the memory 2 to the address bus 10b. The predetermined lower bit value of the designated address of the memory 2 is output from the data transfer unit 3 to the address bus 10b, and increases by 1 from 0° according to the number of bytes of transferred data. The received data is transferred from the data transfer unit 3 to the area of the memory 2 specified by the central processing unit 1.When the data transfer unit 3 finishes the transfer, it sends a message indicating the completion of the transfer via the control bus 10c. Notify the central processing unit 1 and return the lower bit value of the address to 0°.

The central processing unit 1 that received the notification uses the processor bus 1
0 is restored and the reception address designation queue 4 is shifted once so that the next designated address is output from the reception address designation queue 4.

Next, the operation when transmitting data to another device will be explained. The operation in the case of transmission is almost the same as the operation in the case of reception.

The central processing unit 1 specifies in advance a plurality of arbitrary areas on the memory 2 to be used for transmission, and sends them via the data bus 10a and the control bus 10c in the order in which predetermined upper bit values of the specified addresses are used. , is set in the transmission address specification queue 5.

The central processing unit 1 gives up all access rights to the processor bus 10 and notifies the data transfer unit 3 to transmit the data in the memory 2 to another device.

The data transfer unit 3 controls the selector 6 via the control bus 10c to select the output of the transmission address designation queue 5, and outputs a predetermined upper bit value of the designated address of the memory 2 to the address bus 10b. The predetermined lower bit value of the designated address of the memory 2 is output from the data transfer unit 3 to the address bus 10b, and increases by 1' from 0' according to the number of bytes of transferred data. The data to be transmitted in the area of the memory 2 specified by 1 is transferred from the data transfer unit 3 to another device via the communication bus 11.When the data transfer unit 3 finishes the transfer, it sends a message to the control bus 10c indicating the completion of the transfer.
The address is notified to the central processing unit 1 via , and the lower bit value of the address is returned to °O'.

The central processing unit 1 that received the notification uses the processor bus 1
0 is restored and the transmission address designation queue 5 is shifted once so that the next designated address is output from the transmission address designation queue 5.

〔Effect of the invention〕

As explained above, according to the data transfer method of the present invention, in a processor device, any area in the entire address space of the memory can be accessed from the data transfer unit,
Since data can be transmitted and received directly from the work area of the central processing unit to other devices, it is possible to reduce the data processing load on the central processing unit and shorten the time required to transfer data to and from other devices.

1...Central processing unit, 2...Memory, 3...
Data transfer unit, 4... Reception address specification queue 5... Transmission address specification queue 6... Selector,
10... Processor bus, data bus 10a... Data bus, 10b... Address bus, 10c... Control bus, 11... Communication bus.

Claims (1)

[Claims] It has a central processing unit that performs data processing, a memory that stores data, and a data transfer unit that is connected to other devices via a communication bus, and under the control of the central processing unit, the data transfer unit In a data transfer method for a processor device that transmits and receives data between a device and another device, the central processing unit has a transmission address designation queue and a reception address designation queue that store predetermined upper bit information of the address of the memory, and the central processing unit: When transmitting to another device, predetermined upper bit information of the address of the data transmission area designated for use in the memory is set in the order of use in the transmission address designation queue, and when receiving from the other device, When transmitting or receiving data between the memory and another device, predetermined upper bit information of the address of the data reception area designated for use in the memory is set in the order of use in the reception address designation queue. , the data transfer unit is
outputting predetermined lower bit information of the memory address;
A data transfer method characterized in that the address of each of the data transmission area or the reception area is specified by outputting predetermined upper bit information of an address from a transmission address designation queue or a reception address designation queue, respectively.