JPH0348964A - Data transfer method for system bus - Google Patents

Abstract

PURPOSE:To transfer data at a high speed by separating the transfer of data via a system bus from that via a module internal bus and writing data to only an FIFO First in, First out memory which receives and stores the addresses, the data and the commands. CONSTITUTION:A module MA2 fetches the transfer data DTA, a transfer goal address AD, and a write command WT1 in sequence to an FIFO 26 from a module MA1. In this case, an OPRDY serving as a signal showing the presence of data is set to the FIFO 26 and at the same time a DMA request signal DRQ1 is set to a channel 1 of a DMA controller 21 via an AND secured with the output of the WT1. Thus the controller 21 transfers the data stored in the FIFO 26 to a prescribed address of a memory 27 via an address AD. In this case, an address selector 24 selects the AD outputted by the FIFO 26 and a data distributor 25 outputs the output data DTA of the FIFO 26 to an internal bus 23. Thus the data can be transferred at a high speed.

Description

[Detailed description of the invention] [Industrial application field]

This invention relates to a system bus data transfer method in a computer system in which a plurality of functional modules are connected to a system bus, each functional module occupies the system bus in a time-sharing manner, and data is transferred between the functional modules. The present invention relates to a system bus data transfer method that allows a functional module to minimize the time that a functional module occupies the system bus for one data transfer. Note that in the following figures, the same reference numerals indicate the same or corresponding parts.

[Conventional technology]

When configuring a computer system, the general method is to divide the system's functions into multiple functional modules, connect these modules via a system bus, and transfer data to each other to realize the functions of the system as a whole. It's being targeted. Figure 6 shows an example of the configuration of such a computer system.
M (Ml-M5) are various functional modules, such as a processor, a file controller, a communication controller, etc., and 6 is a system bus. Each functional module M has a microprocessor of 10°20
, memory 17.27, internal bus 13.23, system bus interface 113.213, I10 interface 224, etc. In the configuration shown in FIG. 6, when the functional module Ml is a processor and M2 is a file controller, the memory 17
Data transfer between the 110225 and the 110225 is performed, for example, by the following procedure. ■The microprocessor 10 starts the system bus interface 113 and connects the memory 27 via the system bus 6.
Write a transfer command to. ■ Transfer commands are written to the microprocessor 20 via interrupts, etc.
will be notified. ■The microprocessor 20 decodes the instruction and if it is a transfer instruction from the memory 17 to the l10225, starts the system bus interface 213 and first transfers the memory 1
7 to the memory 27. (2) The microprocessor 20 further activates the I10 interface 224 to transfer data between the memory 27 and the I10225. Examples of conventional data transfer methods between the memory 17 and the memory 27 via the system bus 6 are shown in FIGS.
This will be explained in more detail using figures. FIG. 6 shows the main signals on the system bus 6 when data is transferred between the memories 27 and 17, and FIGS. 7 and 8 show their time charts. FIG. 7 shows a write operation from module M2 to module M1, and FIG. 8 shows a read operation from module M2 to module M1. The meanings of the signals in FIG. 7 are as follows. BClK is the system bus synchronous clock (also called pasta lock), and is the system bus interface 1 in Figure 6.
13 and 213 transmit and receive signals on the system bus 6 in synchronization with this. WT is a write command, which is a signal that starts data transfer from module M2 to module M1. AD is an address to which data is to be transferred (also referred to as a destination address), and specifies a predetermined address (allocated in the system bus space) in the memory 17 of the module M1. DTA is transfer data that is read from a predetermined address in the memory rJ27 by the system bus interface 213 and sent to the system bus 6. ACK is a response signal to the write command WT, and is a signal that notifies the system bus interface 213 that the system bus interface 113 has received data. In the time chart of FIG. 7, when the system bus interface 213 acquires the system bus 6, it starts writing in synchronization with the bus clock BCLK (however, the acquisition sequence of the system bus is not directly related to the present invention and is therefore omitted here). Along with the command WT, the transfer destination address AD,
Transfer data DTA is sent to the system bus 6. The system bus interface 113 determines the transfer destination address AD, learns that the transfer is directed to the module M1, and receives the transfer data DTA in response to the write command WT. The system bus interface 113 further writes the received data DTA into the memory 17, and then sends out a response signal ACK. System buff interface 21
3 receives this response signal ACK and issues a write command WT.
is invalidated, and the transfer cycle of the system bus 6 is terminated. In such a conventional transfer method, the internal bus 13 is acquired by the time the system bus interface 113 receives the write command WT and transmits the response signal ACK,
A time Tw is required until it is recessed into the memory 17. When the system bus interface 113 receives data DTA from the system bus 6, if the processor 10 of its own module is accessing the memory 17, the system bus interface 113 waits for the end of the access, and
Data will be written to the memory 17. The meanings of the signals in FIG. 8 are as follows. The bus clock BCLK is the same as in FIG. 7, and RD is a read command, which is a signal that starts data transfer from module M1 to module M2. AD specifies a predetermined address in the memory 17 of the module Ml as the data request destination address (also referred to as a source address). ACK
is the response signal to the read command RD, and the system bus interface 113 receives the requested data DTA.
After reading the data from the memory 17 and sending it to the system bus 6, timing is given to the system bus interface 213 to receive the data. In the time chart of FIG. 8, when the system bus interface 213 acquires the system bus 6, it sends the request destination address AD to the system bus 6 along with the read command RD in synchronization with the bus clock BCLK. The system bus interface 113 determines the request destination address AD, learns that the transfer is intended for the module M1, and receives the request destination address AD in response to the read command RD. The system bus interface 113 further reads data DTA from the address on the memory 17 specified by the request destination address AD, and sends a response signal 'A C
It is sent to the system bus 6 along with K. The system bus interface 213 receives this response signal AC.
After receiving the read data DTA on the system bus 6 by K and writing it into the memory 27, the read command RD is invalidated and the transfer cycle of the system bus is terminated. In the case of the transfer shown in Figure 8, the system bus interface 21
3 acquires the system bus 6 until the end of this data transfer is determined by the system bus interface 113.
It depends on the Vf time TR for reading data from the memory 17 and the time Twl for writing data into the memory 27 by the system bus interface 213. FIG. 9 is a block diagram showing another example of the conventional data transfer method. The difference from FIG. 6 is that data buffers 18 and 28 for temporarily storing data are provided in the system bus interfaces 113 and 213, respectively. Data transfer on the system bus 6 is transferred to this data buffer without waiting for it to be stored in the target memory.
The process ends when the data is stored at 8. As a result, the memory write time Tw in FIG. 7 and the memory write time Twl in FIG. 8 are excluded from the system bus occupation time.

[Problem to be solved by the invention]

However, even in the data transfer method of FIG. 9, the memory successive time TR of FIG. 8 is still required, and the next transfer is started when data is already stored in the data buffer 1 day or 28. As a result, the time the system bus 6 is occupied becomes long. In a computer system as shown in FIG. 6, it is desirable that the time the system bus 6 is occupied during one data transfer be as short as possible; the longer it is, the more the performance of the system will be degraded. Therefore, in the present invention, the occupation time of the system bus 6, which is similar to the conventional data transfer method, is extended due to the time required to acquire the internal bus within the module and the time required to access the memory within the module. This method was developed to solve the problem, and provides a data transfer method in which the occupation time of the system bus 6 is always constant and short, regardless of the internal bus acquisition time or memory access time. That is the issue.

[Means to solve the problem]

In order to solve the above-mentioned problems, the method of the present invention is based on the following method.
etc.), and each functional module occupies the system bus in a time-sharing manner, and transfers data between the functional modules. A first-in-first-out memory (hereinafter referred to as FIFO) for receiving and storing data and commands is provided, and when writing data from the first functional module (MAI, etc.) to the second functional module (MA2, etc.), , a destination address (AD, etc.) sent by the first functional module to the system bus, write data (DTA, etc.) as write transfer data,
When a write command (WTl, etc.) is stored in the FIFO (26, etc.) of the second functional module, the first functional module ends its occupation of the system bus, and the second functional module then uses the FrFO. The stored contents are checked and the write data is stored at the destination address of the first function module. When reading data from the second function module from the first function module, the first function module is connected to the system bus. The source address (such as AD), destination address (such as ADl), and read command (such as RD) sent to the FI of the second functional module are
When the first function module stores the data in the FO, the first function module ends its occupation of the system bus, and the second function module then checks the contents stored in the FIFO, reads data from its own source address, and performs the first function. It is assumed that the data is written to the destination address of the module using the data write method via the FIFO (16, etc.) of the functional module.

[For use]

A first-in first-out memory (also abbreviated as FIFO) for receiving and storing addresses, data, and commands on the system bus 6 is provided for each function module MA, and when writing from module MAL to module MA2, module MA
When L writes the address 1 data and command to the FIFO 26 of module MA2, the bus transfer cycle ends. Also, when reading module MA2 from module MAI, module MAI reads the FI of module MA2.
When the source address (request destination address) of module MA2, destination address (transfer destination address) of module MAI, and read command are written to FO26, the bus transfer cycle is temporarily terminated, and module MA2 is transferred in another cycle. FIF of module MAL
O] 6 to write the requested data and destination address. According to this method, data transfer on the system bus involves only writing to the FIFO of the transfer destination module, and the exclusive time of the system bus is always constant and short. The above data transfer method is
This utilizes the following characteristics of FO. - FIFO can be written and read asynchronously and independently. -FIFO access speeds comparable to high-speed memory are available. ■The number of stages can be selected according to the scale of the system bus.

【Example】

The present invention will be explained in detail below based on FIGS. 1 to 5. Figure 1 shows the new functional module MA (MAI)
An example will be shown in which data is written from 1 to another new functional module MA (MA2). In the same figure, 6 is a system bus, 10.20 is a microprocessor, 11 is
．． 21 is a DMA controller (for example, AMD 823
7 equivalent), 12.22 is the bus controller, 13.2
3 is an internal bus, 14.24 is an address selector (e.g. equivalent to T1's SN74157), 25 is a data distributor (e.g. equivalent to TI's SN74244), and 26 is FIF.
O (e.g. equivalent to NEC @ti P D3341C),
Reference numerals 17 and 27 indicate a memory, 18A a data buffer (eg, equivalent to T1's SN74374), and 120 an address counter (eg, equivalent to TI's SN74161). FIG. 3 shows the bus controllers 12 and 2 in FIG.
The internal block diagram of 2 is shown. BCI in FIG. 3 is the same as the command transmitting side to the system bus 6 in this bus controller (BC2 indicates the command receiving side. In the command receiving side BC2 of the bus controller in FIG. In Figure 1, when module MAI occupies system bus 6 and transfers (writes) data from memory 17 of module MAI to memory 27 of module MA2, the operation is as follows. ■The microprocessor 10 of the module MAI is a DMA
Address counter of channel 0 in controller 11 (
The start address of the transfer data (that is, write data) in the memory 17 is set in a byte counter (not shown) in the DMA controller 11, and the number of bytes to be transferred is set in a byte counter (not shown) in the DMA controller 11. (2) The processor 10 sets the start address of the transfer destination memory 27 (that is, the destination address) in the address counter 120. ■The microprocessor 10 sets the start pulse generator BCII (Fig. 3) of the bus controller 12,
The DMA controller 11 is activated by DRQO (activation (transfer request) signal of channel O of the DMA controller 11). ■The DMA controller 11 sends a signal H to the processor 10.
The internal bus 13 is acquired through the exchange of OLD and HOLD ACK, and the data of memo January 7 specified by the address counter of channel O is transferred to the data buffer 18A.
Transfer to. At this time, the address selector 14 selects DM
The address output by the A controller 11 is selected. (2) A system bus acquisition request is set at the timing when data is stored in the data buffer 18A (at the falling edge of the DMA permission signal DACKO of channel 0 of the DMA controller 11). (Refer to Figure 3 BCI) ■When the bus controller 12 acquires the system bus 6, it sends a write command WT in synchronization with the bus clock BCLK.
I to the system bus 6 and data buffer 1
8A, the gate of the address counter 120 is opened and the transfer data DTA and transfer destination address AD are output to the system bus 6. ■The bus controller 22 determines this transfer destination address AD using a comparator BC21 (FIG. 3), and if it matches its own set address, the bus controller 22 uses the write command WTI to write the contents of the command and the transfer destination address AD. The transfer data DTA is taken into the FIFO 26 and a response signal ACK is sent to the system bus 6. (Refer to FIG. 3 BC2) (1) When the bus controller 12 receives the response signal ACK, it invalidates the write command WTI and terminates the transfer on the system bus 6. The response signal ACK sets the next DMA transfer request DRQO inside module MAI. (3rd
(See Figure BCI) This response signal ACK also provides the timing for incrementing the address counter 120. The address counter and byte counter in the DMA controller 11 are incremented each time one DMA transfer is completed, and an overflow of the byte counter usually notifies the processor 10 of an interrupt, and the processor 10
can read the inside of the DMA controller 11 and know the end of transfer on channel O. On the other hand, the module MA2 that receives data sequentially takes in the transfer data DTA, transfer destination address AD, and write command WTI sent from the module MAI into the FIFO 26, but it receives 0UTPUT READY as a data presence signal in the FIFO 26. Signal 0PRDY
The DMA request signal DRQI of channel 1 of the DMA controller 21 of the module MA2 is set by the AND of the output of the write command WTI of the FIFO 26 and the output of the write command WTI of the FIFO 26. This causes the DMA controller 21 to
The data stored in O26 is transferred to a predetermined address in memory 27 using transfer destination address AD stored in FIFO26. At this time, the address selector 24
selects the address AD output from the FIFO 26, and the data distributor 25 outputs the output data DTA of the FIFO 26 to the internal bus 23. Transfer end signal (DMA permission signal DACKI of channel 1 from the DMA controller 21)
The contents of the FIFO 26 are shifted out by the falling differential signal of
is set, and the next DMA transfer is started (see Figure 3B).
(see C2), and at this time, channel 1 of the DMA controller 21 must be always set in an operable state by the processor 20. FIG. 4 shows the main operation time chart. The meanings of the signals in FIG. 4 are the same as in FIG. 7. The data transfer in Figure 4 is based on the system bus synchronous clock (bus clock) BCL.
The process is executed in two cycles of K, and the time the system bus 6 is occupied is always constant. In this case, it is necessary to select the FIFO 26 that has a sufficient access speed for writing within one cycle of the bus clock BCLK. Further, the number of stages of the FIFO 26 must be selected to have sufficient depth to prevent overflow, taking into account the number of functional modules MA that constitute the computer system and the frequency of data transfer requests. FIG. 2 shows an embodiment in which data of another module MA2 is read from module MAI. Figure 2 is 1. compared to Figure 1. Data distributor 15 on the module MAI side. F I F 016. An address counter 119 is added. In addition, a data buffer 28A and an address buffer 24 are provided on the module MAZ side.
1 has been added. In FIG. 2, module MAI is module MA2
The operation from reading data from the memory 27 to storing it in the memory 17 is as follows. (2) The processor 10 of the module MAL sets the number of transferred bytes in the byte counter (not shown) of channel 3 of the DMA controller 11. (The address counter of channel 3 is not used.) (1) The processor 10 sets the start address (that is, the source address) of the memory 27 where the read data is stored in the address counter 120. ■The processor 10 has a memo 1 in the address counter 119.
Set the start address (that is, the destination address) of the transfer destination of the ride data within month 7. (2) The processor 10 sets the start Hals generator BCII of the bus controller 12 to request acquisition of the system bus 6 (see BCI in FIG. 3). ■When the bus controller 12 receives the system bus 6 51, it outputs the read command RD to the system bus 6 in synchronization with the bus clock BCLK (see Figure 3).
), the gates of the address counters 119 and 120 are opened, and the request destination address AD (i.e., the address of the memory 27) is set as the source address, and the transfer destination address ADI (i.e., the address of the memory 17) is set as the destination address.
address) is output to the system bus 6. At this time, the transfer destination address ADI is output to the data line of the system bus 6 in the form of data DTA. On the other hand, the bus controller 22 of the module MA2 determines the request destination address AD using the comparator BC21 (FIG. 3), and if it matches its own set address, the bus controller 22 of the module MA2 uses the read command RD to determine the contents and the request destination address AD. and data DTA (actually transfer destination address ADI) to FIFO
26 and outputs a response signal ACK to the system bus 6. (2) When the bus controller 12 receives the response signal ACK from the module MA2, it invalidates the read command RD and terminates the transfer cycle of the system bus 6. The bus controller 22 of the module MA2 sets the DMA request signal DRQ2 of the channel 2 of the DMA controller 21 by ANDing the 0UTPUT READY signal 0PRDY as a signal indicating that data exists in the FIFO 26 and the output of the read command RD of the FIFO 26. The DMA controller 21 reads data DTA from the address of the memory 27 stored in the FIFO 26 and stores it in the data buffer 28A. At the same time, the destination address ADI of the FIFO 26 is set in the address buffer 241. At this time, the address selector 24 selects the address ADF output from the FIFO 26, and the data distributor 25 outputs the destination address ADI to the address buffer 241. This DM
At the timing of the end of the A transfer (the falling differential signal of the DMA permission signal DACK2 of channel 2), the data in the FIFO 26 is shifted out, and at the same time, the transfer request of the output bus is set. At this time, channel 2 of the DMA controller 21 needs to be set in an operable state by the processor 20 at all times. When the bus controller 22 acquires the system bus 6, it outputs the write command WT2 in synchronization with the pasta lock BCLK, and opens the gates of the data buffer 28A and address buffer 241 to transfer the transfer destination address AD (actually ADI) and the transfer data. DTA is output to the system bus 6 (see BCI in FIG. 3). Here, a write command WT2 is used to distinguish the transfer of data for which a read request has been made from a normal write. ■Bus controller 1 that received write command WT2
2 takes in the transfer destination address AD and transfer data DTA on the system bus into the FIFO 16, and also outputs a response signal ACK.
is output to the system bus 6. When the bus controller 22 receives this response signal ACK, it invalidates the write command WT2 and ends the transfer cycle of the system bus 6. (2) On the other hand, in the bus controller 12, the DMA request signal DRQ3 of the channel 3 of the DMA controller 11 is set by the AND of the 0UTPUT READY signal 0PRDY as a signal indicating that data exists in the PIFO 16 and the output of the write command WT2 of the 1lFO 16. ■As a result, the DMA controller 11 transfers the transfer data DTA stored in the FIFO 16 to the memory 17 using the transfer destination address ADI stored in the FIF016.
Store in. At this time, the address selector 14 is FIFO
The data distributor 15 selects the address ADI output from the FfFO 16 and outputs the transfer data DTA output from the FfFO 16 to the internal bus 13. [Phase] At the timing of the end of transfer of channel 3 of DMA controller 11 (falling edge of DMA permission signal DACK3), read command RD of next system bus 6 is set, and byte counter and address counter 11 are set.
9,120 is incremented. The end of the DMA transfer is notified to the processor 10 by an interrupt due to an overflow of the byte counter. Memo l727 from module MAI to module MA2
FIG. 5 shows a time chart on the system bus 6 of the operation from reading the data to storing it in the memory 17. FIG. 5 (aJ indicates transmission and reception of a read request signal, and FIG. 5 et al.) indicates data transfer from the module MA2 side of requested data. This (a). In either case, the occupation time of the system bus 6 is constant at two cycles of the bus clock. In this case, read requests and read data transfer are performed in separate cycles on the system bus. Therefore, after the module MAI issues a read request and before the data is actually transferred, different data is written to the address of the memory 17 that was planned by the module MAI by a functional module different from the module MA2. It is possible to put it away. Therefore, if this is inconvenient for the system, a write protection mechanism such as allocating a writable opening for each module MA is required.

【Effect of the invention】

In the conventional data transfer method between functional modules, the system bus occupancy time includes the module's internal bus data transfer time, so the system bus occupancy time depends on the microprocessor and memory installed in the functional module. In contrast, according to the present invention, the system bus transfer is separated from the module internal bus transfer and only writes to the FIFO are performed, so for example, the system bus If the synchronization clock is 8 MHz, all data transfer on the system bus can be completed in 250 ns.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram during a data write operation between modules as an embodiment of the present invention, FIG. 2 is a functional block diagram during a data read operation between modules, and FIG. 3 is the same as in FIG. 1. 2 is a block diagram showing the internal configuration of the bus controller; FIG. 4 is a time chart on the system bus corresponding to FIG. 1; FIG. 5 is a time chart on the system bus corresponding to FIG. 2; The figure is a functional block diagram showing an example of a computer system and conventional inter-module data transfer, Figure 7 is a time chart on the system bus when data is written between modules in Figure 6, and Figure 8 is the module in Figure 6. FIG. 9 is a functional block diagram showing another example of conventional inter-module data transfer. MA: (MAI, MA2-): Function module, 6:
System bus, 10.20 7 microprocessor,
11.21: DMA controller, 12, 22
: Bus controller, 13.23 : Internal bus, 14
, 24 7 address selector, 15, 25 7 data distributor, 16, 26 :F IF 0.17, 27
:Memory, 18A, 28A :Data buffer, 1
19,120 Near address counter, 241: L--knee → ←L--Eng. to APASUKURODUGU BCL. Figure 8 when writing to memory.

Claims (1)

[Claims] 1) A system in which a plurality of functional modules are connected to one system bus, each of which occupies the system bus in a time-sharing manner, and transfers data between the functional modules. A first-in-first-out memory (hereinafter referred to as FIFO) for receiving and storing addresses, data, and commands from the system bus is provided for each of the functional modules, and from the first to the second functional module. When writing data to the FIFO of the second functional module, the destination address sent by the first functional module to the system bus, the write data as write transfer data, and the write command are stored in the FIFO of the second functional module. terminating the occupation of the system bus by the first functional module, and the second functional module then checks the storage contents of the FIFO and stores the write data at its own destination address; When reading data from a second functional module from a functional module, the source address, destination address, and read command sent from the first functional module to the system bus are stored in the FIFO of the second functional module. At this point, the first functional module ends its occupation of the system bus, and the second functional module then checks the contents of the FIFO and reads data from its own source address. A system bus data transfer method, characterized in that the data is written to a destination address using the data write method via the FIFO of the functional module.