JPH0348976A - Picture editing device - Google Patents

Abstract

PURPOSE:To easily process various parts of a picture by selecting the signal of a 1st signal generating means to edit a normal mark and selecting the signal of a 2nd signal generating means to keep the information on the mark. CONSTITUTION:The picture data (b) inputted from a video processing circuit is supplied to a mark area detecting part 9 of a data processing control part 6. Then a mark area signal f25 is produced in a mark area detecting process. The signal f25 is delayed in both main and subscanning directions and therefore a picture data delay circuit 10 matches the delay states between the signal f25 and the data (b). Then the circuit 10 delays the data (b) via a latch set in the main scanning direction and a memory set in the subscanning direction. A CPU 12 binalizes the picture data with input given from a control board and outputs the data on a binarizing threshold level and the trimming, masking and black/white inversion, etc., of a mark area to an editing circuit 11. Thus only an area that is filled with a mark can be worked out.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image editing device, which is capable of specifying an arbitrary area on a document, extracting the arbitrary area, processing such as erasing, black and white inversion, and memory composition. The present invention relates to an image editing device.

[Conventional technology]

With digital copy machines, manual scanners, facsimile machines, etc., if there is a part of the information on the document that does not need to be copied, the relevant part of the document must be cut out before making a copy, or the relevant part of the document must be copied. The necessary parts were copied by covering them with white paper and making copies.

However, with this conventional method, the original must be processed, which may damage the original, and in addition to being time-consuming, it is necessary to obtain multiple copies with unnecessary parts removed. In some cases, for example, the white paper covering unnecessary parts may shift, making it impossible to obtain identical copies.

In order to solve this problem, a color felt-tip pen or the like is used to mark an arbitrary area on a document, and by reading the designated area of the mark, the area for processing and memory composition is specified.

[Problem to be solved by the invention]

By the way, in the prior art, when specifying a mark on a document, the desired area is filled in or surrounded. However, if you want to erase only the middle line m2 of the triple 111m, mz, m3 consisting of the closed loop shown in Fig. 21(a) (see Fig. 21 + dl),
As shown in FIG. 21(b), when the line m2 is marked, masking (inner erasure) may erase vAmz as well, even if the information in Imz (for example, line m) remains (see FIG. 21(b)). (C)), in trimming (outer erasure), even if information outside line m2, such as line m, is to be left, line m may also be erased, and the process shown in FIG. 21(d) It was difficult to do so.

The present invention has been made in view of and to solve the problems of the prior art, and its purpose is to provide an image editing device that can process only the area painted with marks. .

[Means to solve the problem]

In order to achieve the above object, the present invention provides a reading means for reading an original image and generating image information, a specifying means for specifying a desired area of the original by a mark, and an area enclosed by the specifying means. a first signal generating means that generates a signal, a second signal generating means that generates an area signal of only the mark portion specified by the specifying means, and an area signal generated by the first signal generating means, or the second signal generating means and mode setting means for setting one of the area signals generated by the signal generating means.

[Effect]

By means of the means, the signal of the first signal generating means is selected when normal mark editing is desired, and the signal of the second signal generating means is selected when it is desired to leave information on the inside or outside of the mark. This allows processing in a variety of areas.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 shows a block diagram of an image processing apparatus according to an embodiment of the present invention. Reference numeral 4 denotes a scanner section;
As shown in FIG. 2, an image of the reading line l of the original 1 is focused on the CCD line sensor 3 via the coupling lens 2, and the relative position between the original 1 and the CCD line sensor 3 in the Y direction is While updating the read line by mechanically shifting the position (sub-scanning), scan each line 40 times from left to right in the X direction.
Read at a density of 0 dpi (#16 pixels/tsuru) (main scan)
. The read signal becomes an analog signal having an amplitude corresponding to the density of each pixel. 5 is a video processing circuit which A/D converts the read signal a, performs background removal processing, shading correction processing, MTF correction processing, etc. on it, and generates 6-bit (64 gradation) image data 6 (the higher the value, the more This is a circuit that generates high-density). Reference numeral 6 denotes a data processing control unit. This data processing control unit 6 binarizes the read data by setting black pixels to “1”: H level and white pixels to “0”: L level, and performs extraction (trimming) of specified areas. ), erasure (masking), etc., to generate write data d. 8 AO the laser beam
This is a laser printer that modulates (1: recording, O: non-recording) and prints out on recording paper.

In the above-mentioned image processing device, the control device that controls each of these components, the scanner section 4, the video processing circuit 5, and the laser printer 8 are well-known technologies and do not directly relate to the features of the present invention, so a detailed explanation will be given. Omitted.

The data processing control unit 6 detects a mark in a predetermined density range written on the original 1 or an area surrounded by the mark, and performs trimming and masking on the original based on this.

In this embodiment, a mark using a color felt pen (hereinafter referred to as a color mark) is used as a mark for a predetermined density range.
Assume that This is because color felt-tip pens are already available in various densities, which makes marking in a predetermined density range easier and is advantageous in practice.

FIG. 4 is a block diagram showing the configuration of the density determination circuit and the one-pixel noise removal circuit. 34 and 35 are comparators, and these two comparators 34 and 35
constitutes a density determination circuit, and detects halftone read data A. In other words, by comparing read data A and two threshold levels BTI and B7□ (By+ > Byt), B? A signal f such that l>A.

A signal f8 with Byt<A is obtained. Here, the threshold level 13yt is the same as the threshold level for converting into a single m 2 value. As a result, in simple binarization, the so-called range that is not judged as black,
A faint mark will be detected. Also, threshold level B? ! An appropriate level is set for stains on the background of the original, uneven density, etc. 36 is a flip-flop, 37°38 is an OR gate, 39.40 is A
The ND gate constitutes a 1-pixel noise removal circuit.

FIG. 5 is a time chart for explaining one-pixel noise removal.

As an example, assume a signal f as shown in FIG.

Note that the numbers in the time chart indicate the main scanning address of the read pixel, and the signal f1 here is the main scanning address 5.
The place where noise is added and f,==″1′ becomes f,−
The color mark is detected between main scanning addresses 1 to 4 and 6 to 8, and f is set to "1".
This is a clock signal with a period. f, is a signal obtained by latching one period of the signal f1 using the flip-flop 36, and the signal f! By passing the signal f and the signal f through an OR gate 37, a signal f4 from which noise has been removed is obtained.

Since the signal f4 is longer than the signal f before noise removal by one period, the signal f4 is latched for one period using the flip-flop 36 to obtain the signal f4 and the signal f4. By passing f, through the AND gate 39, noise is removed and a signal f having the same length as the signal f is obtained.
, get . Also for the signal ft, a flip-flop 36,
A similar operation is performed using an OR gate 38 and an AND gate 40 to obtain a signal f7. Finally, by passing the signal f and the signal f through an AND gate 41, a signal f indicating the mark density range can be obtained.

Although this example describes the removal of 1-pixel noise, by changing the system, it is possible to remove 2-pixel, 3-pixel, . . . , n-pixel noise. Further, threshold levels BTI and Bo can be varied.

FIG. 6 is a block diagram of the mark area detection circuit.

For example, even if a halftone is detected in a minute area of one to several pixels due to dirt on the background, it will not be detected as a mark area. The marked area is a certain area including the marked area.

The basic unit of this mark area is 12 in this example.
The unit is X 12 pixels, but this can be changed by changing the system. A signal f indicating the mark density range is input to the first sub-scanning mark detection section 42 and the second sub-scanning mark detection section 43.

FIG. 14 T8) shows the function of the first sub-scanning mark detection section 42. In this first sub-scanning mark detection section 42, 12
The basic unit of an area of ×12 pixels is scanned in the sub-scanning direction, and when the signal f = “1” in all 12 pixel blocks, that block is considered “OK” (=1), and even if there is only one pixel, the signal f8- When “O”, the block is “NG” (=0
). And when 12 block scanning is completed,
When all the blocks are OK, the first main scanning mark detection unit 44 identifies this 12×12 pixel basic unit as a mark area, outputs the signal f=“1”, and outputs the signal GATE=“ 1″.

FIG. 7Tb) shows the function of the second sub-scanning mark detection section 43. In this second sub-scanning mark detection section 43, 12
Within a block of pixels, a certain probability (2/3 in this example)
In the above, when the signal f = "1', the block is
When the probability of signal f is less than K'' (-1) and the signal f=11', the block is determined to be NG'' (=O).

Then, when the scanning of 12 blocks is completed, the second main scanning mark detection unit 43 detects 12 X if the block is "OK" with a certain probability (2/3 in this embodiment) or more.
A basic unit of 12 pixels is identified as a mark area, and a signal. ="1" is output. When the mark area has already been detected by the first sub-scanning mark detection unit 42 and the first main-scanning detection unit 44, the signal GATE="1', so the signal II+" is passed through the AND gate 47.
"1" is output. The signal f and the signal fll pass through the OR gate 46, and finally a signal f12 indicating whether the area is a mark area or not is output. The main scanning mark width extension section is used to detect marks as if they were continuous, ignoring the fact that marks are broken and divided by white, or even if a minute area in a mark is white or black. 48 in the main scanning direction and a sub-scanning mark extension section 49 in the sub-scanning direction to output a signal f13 indicating the mark area.

In this embodiment, as shown in FIG. 8, the expansion is performed by 8 pixels in the main scanning direction and 6 pixels in the sub-scanning direction, but this can also be changed by changing the system.

Also, when marking on black printing with a colored felt-tip pen, the black printing part is still black and has a high density.If the halftone area is divided by black like this, the black part The halftone area is enlarged and detected. This is called Kurotogire.

Fig. 9 is a block diagram of the black mark prevention circuit, and Fig. 10 shows a state in which a black line enters a mark and the mark is interrupted, with the horizontal axis in the main scanning direction, and the corresponding signals. This is a diagram showing the following.

Signal f1 with marks extended in the main scanning direction and sub-scanning direction
3 through the inverter gate 50 and inverted as the signal r
+s. The signal f14 is a signal indicating a black area, and the signal f1. = “1”.

Signal f0 is obtained by passing signal flS and signal f+a through NAND gate 51. Signal f1. is latched by the shift register 52 to obtain a signal f+. In this example, 16
6 pixels (approx.
4 pixels (approx. 1.50), 22 pixels in the sub-scanning direction (approx. 1.4
m) Compensating for black spots.

This can be changed by changing the system.

By passing the signal f17 and the signal f+s through the NAND gate 53, a signal fll+ free of black toggles is obtained.

Then, by passing the signal f11 through the inverter gate 54, a signal fl'1 indicating a mark compensated for black toggle is obtained. Similar operations are performed in the sub-scanning direction as well.

Here, the signal f19 is a marker detection signal (signal indicating only the mark area) that prevents black spotting, and is as shown in FIG. That is, the mark area detection signal to be described later performs area detection using this marker detection signal f19, but this marker detection signal f8. is also used as a control signal for editing.

Next, detection of an area surrounded by marks will be explained.

FIG. 11(a) shows a block diagram of the mark area detection section, and FIG. 12 shows an example of marks used for explanation. 13 and 14 are time charts corresponding to each signal in FIG. 11(a), and ■ to ■ in the figures indicate mark signals or mark area signals at points ■ to ■ in FIG. represent.

When detecting the mark area at the point (2), in FIG. 13, the signal r3. The signal "2°" indicating the mark area at the point marked ■ stored in the memory 55 in FIG. 11 is passed through the OR gate 57 to generate the signal f2
get. Then, at the first rise of the signal f19, the set signal generating section 56 generates the set signal rt+, and the signal f19 generates the set signal rt+.
At the falling edge of t6, the reset signal generating section 58 generates the reset signal f21. Signal'! ! + signal f23
．． The signal f0 is passed through the three-man AND gate 59, and the signal r
get za. Then, the signal fZ4 and the signal f19 are passed through an OR gate 60 to obtain a signal fzS indicating the mark area.

When detecting the mark area at the point (3), the same operation is performed to obtain the mark area signal f24.As shown in Fig. 14, the actual mark area signal is equal to fI in this case, so an error occurs. However, this is not a problem because the points ■ and ■ are actually very close at about 0.06 mm.

This error occurs because the reset signal "2." is set at the falling edge of the mark area signal f2° of the previous line. This does not occur if the reset signal is set at the same time, but in cases where there are multiple marks, it is difficult to determine the last fall time.
This method is used.

FIG. 11(b) is a block diagram showing another embodiment of the mark area detection section.

In this figure, 75 is a counter, 76 and 77 are flip-flops, 78 is a comparator, 79 is a set circuit,
80 is a memory, 81 is an AND gate, and 82 is an OR gate.

Counter 75 counts up within the validity period of LGATE
This is a counter for Here, when the mark signal f19 is input, the counter value of the counter 75 is latched by the flip-flop 76 with the signal fll. This latch output is further connected to the LG by a flip-flop 77.
It is latched by the ATE signal. At this time, the flip-flop 76 is cleared once by LSYNC, and also latches the counter value when the mark comes. Then, the output of the flip-flop 77 and the counter value of the counter 75 are compared by the comparator 78, but the output of the flip-flop 77 becomes the address of the previous marker area, and the value of the counter 75 becomes the address of the current line. , the output of the comparator 78 becomes the mark area signal of the previous line, and a reset signal f is output. Also,
Here, when LGATE becomes L, the counter value is cleared, so the rts reset signal becomes H.

In addition, as described above, the mark detected signal f8. is input, the set circuit 79 uses the first mark signal to
A signal is set (for example, address 105), and further, the signal fB from the reset block is reset by the last mark signal in the main scanning direction of the previous line (for example, address 220).

Further, rzo is a signal obtained by detecting the mark area of the previous line, and f. , f□, fo by AND gate 81
The ND signal becomes rt4. Here, the reset signal f
0, the last mark signal end of the previous line becomes the reset edge, so f! The first mark area of No. 4 is the same as the current line, but the rear end of the next mark becomes the mark area of the previous line.

To prevent this, the mark area signal fts of the current line is realized by performing an OR with the mark of the current line using an OR gate 82.

As described above, according to this embodiment, it is possible to detect a halftone and a portion surrounded by a halftone, and the shape thereof is not limited to a rectangle but can be various. Further, the number of areas surrounded by halftones in one document is not limited, and since the detection is performed in parallel with the document adjustment/taking operation, there is no need to perform area detection in advance by, for example, pre-scanning.

That is, for example, it is possible to extract a designated area and simultaneously copy the image of that area. Also,
This embodiment deals with marks made with color felt-tip pens, but other marks are irrelevant as long as the density is within a specific density range, and furthermore, no special sensor or light source is required for detection. This mark is set in the range that is determined to be white by simple binarization, so the mark will not appear in the binarized data and will not appear in copies printed based on the binarized data. , the mark does not appear. Furthermore, since the mark is extended to detect the halftone area, even if the mark is divided by white or black, the area can be detected effectively.

Here, the relationship between the image data and the mark area detection signal will be explained.

The image output from the video processing circuit 5 is (image data b
) enters the mark area detection unit 9 of the data processing control unit 6, and generates the mark area signal rzs by the mark area detection processing described above. Since the mark area signal f□ is delayed in the main scanning and sub-scanning directions,
The image data delay circuit IO matches the delay state of the mark area signal rxs so as to match the delay with the image data b. The delay circuit IO uses a latch in the main scanning direction and a memory in the sub-scanning direction. CPU
12 is an input from an operation board, and outputs data such as a binarization threshold level, mark area trimming, masking, black and white inversion, etc. to the image data binarization and editing circuit 11.

FIG. 15 shows a detailed block diagram of the binarization and editing circuit 11 in FIG. 3, and FIG. 20 shows the relationship between the editing data from the CPU 12 and the output data d corresponding to N, Ml to M3. .

In FIG. 15, 61.62 is a comparator, 63°64, 72 is a selector, 65.66, 69 is an inverter, 67°68, 70.71 is an AND gate, and 73 is a dither ROM.

74 is a selector.

First, a method of binarizing the human data g will be explained.

In the case of character output, the comparator 61 compares the binarization level H from the CPU 12 and the input data g, and outputs the disulfide number I. Furthermore, by the dither method, the dither ROM 73 and the input data are compared in the comparator 62 as pseudo halftone output, and the dither data (halftone data) J
output, and if the operation board is in character mode, C
Data K from the PU 12 becomes 0, and I becomes an L output by the selector 63.

In the case of the halftone (photograph) mode, the data from the CPU 12 is L, and the selector 63 outputs J to L.

At this time, the CPU data N corresponding to the selector 72 is
l Either is fine, and the CPU 12 that corresponds to the selector 72
The data M1 to M3 become 0, and the human power A of the selector 72
A signal corresponding to this will be output.

In addition, in marker editing mode, since the marker supports halftone density, human manuscripts are basically character manuscripts with a clear white/black ratio, in other words, the background is whiter than the lower limit level of the marker, and the characters are It is assumed that the data is blacker than the marker upper limit level.

Therefore, since marker editing is intended for text manuscripts,
When editing markers, K becomes O.

In the embodiment of the present invention, fI and rzs are input as marker signals. As described above, fl is a signal representing only the area filled with marks, and rts is a signal indicating the area filled with marks and the area surrounded by the marks. Here, when normal marker editing is desired, the f's signal is selected, and when it is desired to leave information on the inside or outside of the closed loop as described above, fl'1 is selected. In other words, when the select signal N of the selector 73 is set to 0, f! S
is selected, and when it is set to 1, fl is selected.

Next, the difference in editing modes depending on the marker signals from fl9 and f25 will be explained with reference to FIGS. 15 and 17 to 20.

(11 Masking: In other words, when erasing information in the mark area, the AND gate 67 uses the mark area signal f
19 or rzs inverted by an inverter 66,
The logical product with the binary image signal is taken, the information in the mark area is erased, and the data is input manually to the B input of the selector 72, and the CPU
12 commands M1 to M3: Ml;1, M2. M3;0
By doing so, masking data is output to the d output. That is, when the original shown in FIG. 17 is masked, in the case of r+q manual labor, A as shown in FIG. 19(a)
, B remains and the circle surrounded by the mark is erased, and in the case of fZ5 manual power, only A remains as shown in Figure 18 (al).

(2) Trimming: In other words, when extracting only the information within the mark area, the AND gate 68 uses the signal f19 or r
zs and the binary image signal, extract only the information in the mark area, input it to the C input of the selector 72, and use commands M1 to M3 of the CPU 12 to set M2:LMl,
By setting M3;O, trimming data is output to the d output. That is, when the original shown in Figure 17 is trimmed, only the circle remains as shown in Figure 19 (in the case of f19 manual input), and the circle and B remain as shown in Figure 18 (b) in the case of rts input. .

(3) Black and white inversion of image data outside the marker: In other words, in the image data, only the information inside the marker is inverted in black and white, and the image data outside the marker is output as is. Select image data and inverted data by signal f19 or fts,
When a mark area signal is generated, inverted data is selected and output. Also, the commands M1 to M3 of the CPU 12 are Ml, M2:1. M3:0. That is, when the original shown in Fig. 17 is processed with black-and-white inverted image data outside the marker, in the case of flQ, only the circle part (as shown in C1) is inverted, and in the case of rzs, the first
As shown in Figure 8 (C1), the circle and area B are reversed in black and white.

(4) Outside marker black and white inverted image data inside marker: This is
(3) The signal obtained from the inverted black and white image data outside the marker inside the marker is inverted by the inverter 69, and the CP
Commands M1 to M3 of U12 are Ml, M2:O, M3
:1. That is, when processing the image data of the black and white inverted marker outside the marker on the original shown in FIG. 17, in the case of fI9, the 18th
As shown in Figure 18(d), the area outside the disk is black and white inverted, and in the case of fts, the area outside the disk is a circle and B as shown in Figure 18(d).
Other than that, black and white will be reversed.

(5) Black and white inversion within trimming marker: This is done in the same way as the trimming process in (2) for the image of only the marked area.
The D gate 71 outputs the logical product of the mark signal and the inverted image data signal. Also, C
Commands M1 to M3 of PU12 are Ml, Mll, M2
:O.

That is, when the image data of the original shown in FIG. 17 is processed with black and white inversion within the trimming marker, in the case of fI9, the image data shown in FIG.
As shown in the figure, only the circle is inverted in black and white, and A and B are erased. Further, in the case of ftA, as shown in FIG. 18ff), A is erased, and the circle and B are reversed in black and white.

(6) Masking marker outside black and white inversion: This is an AND operation similar to the masking process in (1) for the image outside the marked area.
The mark signal is output by the inverter 66 of the mark signal and the inverted signal of the image data.

Also, the commands M1 to M3 of the CPU 12 are Mll, M2.
M3:1.

That is, when the image data of the original shown in Fig. 17 is processed with black and white inversion outside the masking marker, in the case of fI, the image data shown in Fig. 19 (f) is obtained.
As shown in FIG. 18, only the circle is erased, and the others are inverted in black and white. In the case of fo, the circle and B are erased, as shown in FIG. 18ff), and the others are inverted in black and white.

In this manner, in the embodiment described above, the user can perform desired editing using the signal fl of only the mark area and the mark area signal ftA. In other words, if you want to erase only the line that forms a closed loop by processing only the area painted by the mark (extracting, erasing, black-and-white inversion of image information for the mark specified area), you can use the information in the closed loop (masking ), editing can be performed without erasing information outside the closed loop (in the case of trimming).

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to process only the area covered by the mark.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1 to 20 show embodiments of the present invention. FIG. 1 is a block diagram of an image editing device according to the present invention, and FIG. 2 is a block diagram of an image editing device according to the present invention. Explanatory perspective view, 3rd
The figure is an explanatory diagram showing the relationship between image data and mark area detection signals, FIG. 4 is a block diagram showing a density determination circuit and a 1-pixel noise removal circuit, and FIG. 5 is a time chart for explaining 1-pixel noise removal. Fig. 6 is a block diagram of the mark area detection circuit, Fig. 7 +a) and (b) are explanatory diagrams explaining the movement of first and second sub-scanning mark detection, and Fig. 8 is an explanation showing expansion of the mark area. Figure 9 is a block diagram of the black line prevention circuit, Figure 10 is an explanatory diagram showing a state in which a black line enters a mark and the mark is interrupted, and each signal corresponding to this, and Figure 11 is a mark area. A block diagram of the detection unit, FIG. 12 is an explanatory diagram showing the relationship between marks and scan lines, FIGS. 13 and 14 are time charts showing each signal when detecting the original in FIG. 12, and FIG.
The figure is a detailed block diagram of binarization and editing in Figure 3, and Figure 16.
The figure is an explanatory diagram showing the relationship between marks and marker detection signals.
Figure 7 is an explanatory diagram showing an example of marking a manuscript, No. 18
The figure is an explanatory diagram showing each side of the manuscript in Figure 17 processed by FTS, and Figure 19 is the manuscript in Figure 17 processed by fI9.
20 is a diagram showing the relationship between output data corresponding to editing data from the CPU, and FIG. 21 is an explanatory diagram illustrating the conventional processing of an area using marks. be. 1...Original, 4...Scanner section, 5.
...Video processing circuit, 6...Data processing control unit, 9...Mark area detection unit, 10...Delay circuit, 11... - Binarization and editing circuit, 12...CPU. 13゜16... Image storage memory, 74... Selector. Figure 2 Figure 3 Muto 8 Figure 9 Figure 10 ys Figure 12 Figure 13 Figure 14 Figure 25 0 I Figure 1I (b) Figure 15 9

Claims (1)

[Claims] a reading means for reading a document image and generating image information; a designation means for designating a desired area of the document by a mark; and a first signal generation means for generating a signal for an area designated by the designation means and enclosed. and a second signal generating means for generating an area signal of only the mark portion specified by the specifying means; and either an area signal generated by the first signal generating means or an area signal generated by the second signal generating means. An image editing device comprising: mode setting means for setting.