JPH02253376A - Picture editing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image editing device, and is an image editing device that enables mixed text/photograph output by specifying an area for a text/photo mixed document. Regarding equipment.

[Conventional technology]

When reproducing an original containing text/photos, there are two methods as described below.

(1) In a mixed text/photograph document, the text portion or photo portion is recognized and the text processing and photo processing (dither processing) are separated and output in the recognized area.

(2) Text/photo area of text or photo area x
, by inputting the y-coordinate, and separately outputs text processing and photo processing in the set area.

[Problem to be solved by the invention]

By the way, in the above-mentioned conventional technology, when there is mixed image information of text/photo, when the image is output through text processing, the photo area loses gradation, and when the photo area has halftone dots, moiré ( Interference fringes caused by the difference between the pitch of the CCD and the pitch of the halftone dots) are formed, leading to deterioration of image quality, and
When outputting an image using photo processing, there is a drawback that the text area becomes blurred and becomes unreadable.In recent years, as a countermeasure,
Text processing and photo area recognition have also been devised, but there are errors in recognition and none of them are fully functional.

In addition, the editing method uses X and Y coordinates to specify the area, and by specifying the area, it is possible to process text and photos by area, but since the X and Y coordinates are input, it is difficult to specify complex areas. .

The present invention has been made in view of the above-mentioned problems of the prior art, and its purpose is to specify an area of a mixed text/photo document by specifying a mark area, and to process text in the text area and to process photos in the photo area. An object of the present invention is to provide an image editing device that can reproduce and output a processed image.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a reading means for reading a document image and generating image information, a specifying means for specifying a desired area of the document, and an area indicating the desired area according to the area specification by the specifying means. A generating means for generating a signal, a storage means for synthesizing the plurality of image information and having a storage means capable of storing a plurality of image information, and a means for binarizing the image information generated by the reading means. , comprising means for performing pseudo-halftone processing on the image information generated by the reading means, and control means for controlling writing and reading of the storage means, wherein the area signal indicating the desired area is stored in the storage means. The control means stores the region signal, the control means reads the region signal from the storage means, and the storage composition means synthesizes the binarized image and the pseudo-halftone-processed image using the desired region signal. It's Nishide.

[Effect]

By means of the above-mentioned means, the text/photograph mixed original is subjected to text processing in the text portion and photo processing in the photo portion based on the area signal. Thereby, it is possible to reproduce and output a good image.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 shows a block diagram of the configuration of an image processing apparatus that is an embodiment of the present invention. 4 is a scanner section, and this scanner section 4
As shown in FIG. 2, an image of the reading line l of the original 1 is focused on the CCD line sensor 3 via the coupling lens 2, and the relative position between the original 1 and the CCD line sensor 3 in the Y direction is While updating the read line by mechanically shifting the position (sub-scanning), scan each line 40 times from left to right in the X direction.
Read at a density of 0 dpi (#16 pixels/tsuru) (main scan)
, the read signal becomes an analog signal having an amplitude corresponding to the density of each pixel. , 5 is a video processing circuit which A/D converts the read signal a, performs background removal processing, shading correction processing, MTF correction processing, etc. on it, and generates 6-bit (64 gradation) image data 6 (higher numerical values). This is a circuit that generates (higher concentration). 6 is a data processing control unit, and this data processing control unit 6 reads the data and sets the black pixel to “1”: H level, and the white pixel to “O”: L level.
As a level, the data is binarized, and specified areas are extracted (trimmed), erased (masked), etc., to generate write data d. Also, the write data d is
As will be described later, this is a mark area signal. Reference numeral 7 denotes a memory control unit, which stores the write data d in a memory, and the memory in the memory control unit 7 has a plurality of frame memories, and also performs compositing between the memories. and outputs a signal e. 8 modulates the laser beam (1
: recording, 0: non-recording) and prints out on recording paper.

In the above-mentioned image processing device, the control device that controls each of these components, the scanner section 4, the video processing circuit 5, and the laser printer 8 are well-known technologies and do not directly relate to the features of the present invention, so a detailed explanation will be given. Omitted.

The data processing control unit 6 detects a mark in a predetermined density range written on the original 1 or an area surrounded by the mark, and performs trimming and masking on the original based on this.

In this embodiment, a mark using a color felt pen (hereinafter referred to as a color mark) is used as a mark for a predetermined density range.
Assume that This is because color felt-tip pens are already available in various densities, which makes marking in a predetermined density range easier and is advantageous in practice.

FIG. 1) is a block diagram showing the configuration of a density determination circuit and a one-pixel noise removal circuit. 34° and 35 are comparators, and these two comparators 34.3
5 constitutes a density determination circuit and detects halftone read data A. In other words, by comparing the read data A and two threshold levels BT1 and BT2 (BTI>BT□), the signal f1 becomes BTI>A, and the signal f2 becomes BT□<A.
get. Here, the threshold level 13t+ is the same level as the threshold level for simple binarization. As a result, in simple binarization, a so-called faint mark is detected in a range that is not determined to be black. Further, the threshold level BTt is set at an appropriate level for stains on the background of the document, density unevenness, and the like. 36 is a flip-flop, 37°38 is OR
Gates 39 and 40 are AND gates, which constitute an l pixel noise removal circuit.

FIG. 12 is a time chart for explaining 1-pixel noise removal.

As an example, assume a signal f as shown in FIG.

Note that the numbers in the time chart indicate the main scanning addresses of the read pixels. The signal f here is the main scanning address 5
Noise is added at the point where fl−“1′ becomes f,=“
The color mark is detected between main scanning addresses 1 to 4 and 6 to 8, and fI becomes "1". The clock CK has one cycle equal to one main scanning pixel. The clock signal f3 is a signal obtained by latching the signal f for one cycle using the flip-flop 36. By passing the signal f2 and the signal f through an OR gate 37, the signal f4 from which noise has been removed is obtained. obtain.

Since the signal f4 is longer by one period than the signal f before noise removal, the signal f4 is latched for one period using the flip-flop 36 to obtain the signal r5, and the signal f4 and the signal f are latched for one period. , through the AND gate 39, noise is removed and a signal of the same length as the signal f is obtained.
, get . Also for the signal f2, the flip-flop 36,
A similar operation is performed using an OR gate 38 and an AND gate 40 to obtain a signal f7. Finally, by passing the signal f6 and the signal f7 through the AND gate 41, a signal f indicating the mark density range can be obtained.

Although this example describes the removal of 1-pixel noise, by changing the system, it is possible to remove 2-pixel, 3-pixel, . . . , n-pixel noise. Also, the threshold level BTI and E3'
rz can be varied.

FIG. 13 is a block diagram of the mark area detection circuit. For example, even if a halftone is detected in a minute area of one to several pixels due to dirt on the background, etc., it is not detected as a mark area. That is, over a certain area, only in the case of an intermediate tone, a certain area including that area is set as a mark area.

The basic unit of this mark area is 12 in this example.
The unit is x12 pixels, but this can be changed by changing the system. The signal fa indicating the mark density range is input to the first sub-scanning mark detection section 42 and the second sub-scanning mark detection section 43.

FIG. 14 (al indicates the function of the first sub-scanning mark detection section 42. In this first sub-scanning mark detection section 42, 12
The basic unit of ×12 pixel area is scanned in the sub-scanning direction, and the signal f, = “1′” in all 12 pixel blocks.
When , the block is set as “OK” (=1), and when even one pixel has signal f=“0”, the block is set as “NG” (=
0). When the 12 block scanning is completed, the first main scanning mark detection unit 44 identifies this basic unit of 12 x 12 pixels as a mark area when all blocks are "OK", and sends a signal f,= It outputs "1" and sets the signal GATE="1".

FIG. 14 (bl shows the function of the second sub-scanning mark detection section 43. In this second sub-scanning mark detection section 43, 1
Within a block of 2 pixels, there is a certain probability (in this example, 2/3
) With the above, when the signal f = “1”, the block is “
If the probability is less than "OK" (=1) and the signal f = "1', the block is determined to be "NG" (=0).

Then, when the scanning of 12 blocks is completed, the second main scanning mark detection unit 43 detects 12 X if the block is "OK" with a certain probability (2/3 in this embodiment) or more.
A basic unit of 12 pixels is identified as a mark area, and a signal. ="1" is output. When the mark area has already been detected by the first sub-scanning mark detection section 42 and the first main scanning detection section 44, the signal GATE="1m" is passed through the AND gate 47 and the signal flI=
“1” is output. The signals f and flll pass through an OR gate 46, and finally a signal f12 indicating whether or not the area is a mark area is output.

Even if the area identified as the mark area is interrupted in the middle and divided by white, or if a small area within the mark is white or black, it is ignored and the mark is continuous. In order to detect this, the mark area is expanded in the main scanning direction through the main scanning mark width expanding section 48 and in the sub scanning direction through the sub scanning mark expanding section 49, and a signal f13 indicating the mark area is output.

In this embodiment, the expansion is performed by 8 pixels in the main scanning direction and 6 pixels in the sub-scanning direction as shown in FIG. 15, but this can also be changed by changing the system.

Furthermore, when marking the black print with a color felt-tip pen, the black print part is still black and has a high density. In this way, if the halftone area is divided by black, the halftone area is expanded to include the black part for detection. This is called Kurotogire.

Fig. 16 is a block diagram of the black blur prevention circuit, and Fig. 17 shows a state in which a black line enters a mark and the mark is interrupted, with the horizontal axis in the main scanning direction, and the corresponding signals. This is a diagram showing the following.

Signal f1 with marks extended in the main scanning direction and sub-scanning direction
3 is passed through an inverter game 1-50 and inverted, and the signal is designated as signal f15. The signal r+a is a signal indicating a black area, and the signal f14="1" in the black area.

A signal r+a is obtained by passing the signal ``8.'' and signals f and 4 through the NAND gate 51.The signal f16 is latched by the shift register 52 to obtain the signal f17.In this embodiment, 166 pixels (approximately 1 mm) are latched. In addition to the previously expanded 8 pixels in the main scanning direction and 6 pixels in the sub-scanning direction, there are 24 pixels in the main scanning direction (approximately 1.5 mm), and an additional 22 pixels in the scanning direction (
Approximately 1. -4m1+) Compensates for dark spots on the back.

This can be changed by changing the system.

By passing the signal f17 and the signal r+s through the NAND gate 53, a signal f18 free from black toggles is obtained.

Then, by passing the signal flll through the inverter gate 54, a signal f19 indicating a mark compensated for black toggle is obtained. Similar operations are performed in the sub-scanning direction as well.

Next, detection of an area surrounded by marks will be explained.

FIG. 18 shows a block diagram of the mark area detection section, and FIG. 19 shows an example of marks used for explanation.

FIGS. 20 and 21 are time charts corresponding to the signals shown in FIG. 18, and ``■'' to ``■'' in the figures represent mark signals or mark area signals at points ``■'' to ``■'' in FIG. 19.

When detecting the mark area at the point ■, in FIG. 20, the signal f19 indicating the mark at the point ■ and the signal f2° indicating the mark area at the point ■ stored in the memory 55 in FIG. 18 are used. The signal f2□ is obtained by passing through the OR gate 57 in FIG. and signal fl.

At the first rising edge of signal rzo, the set signal generating section 56 in FIG. 18 generates the set signal fZI, and at the falling edge of the signal rzo, the reset signal generating section 58 in FIG. 18 generates the reset signal fZ3. Signal f2□, signal f2. .

The signal f23 is passed through the three-man power AND gate 59 in FIG. 18 to obtain the signal ft4. and signal f24 and signal f3
．． is passed through the OR gate 60 in FIG. 18 to obtain a signal [25 indicating the mark area.

When detecting the mark area at point (3), the same operation is performed to obtain the mark area signal fT14.As shown in Fig. 21, the actual mark area signal is equal to f19 in this case, so there will be an error. , this is actually ■ and ■
There is no problem because the point is very close at about 0.06 m. This error occurs because the reset signal f0 is set at the falling edge of the mark area signal rzo of the previous line.

This is the point where you want to detect the mark area signal, e.g.
This will not occur if the reset signal is set at the fall of the mark signal [19 at the point, but when there are multiple marks, it is difficult to determine the last fall, so this method is used.

Here, the relationship between the image data and the mark area detection signal will be explained.

The image output from the video processing circuit 5 is (image data b
) enters the mark area detection unit 9 of the data processing control unit 6, and generates a mark area signal f25 by the mark area detection processing described above. Since the mark area signal rzs is delayed in the main scanning and sub-scanning directions, the image data delay circuit 10 matches the delay state with the mark signal "2" so as to match the delay with the image data b. The delay circuit 10 uses a latch in the main scanning direction and a memory in the sub-scanning direction.CPU 12
is inputted from the operation board and outputs data such as the binarization threshold level, mark area trimming, masking, black and white inversion, etc. to the image data binarization and editing circuit 1).

FIG. 22 shows a detailed block diagram of the binarization and editing circuit 1) of FIG. 3. Further, FIG. 24 shows the relationship between the editing data from the CPU 12 and the output data d corresponding to M1 to M3.

First, a method of binarizing input data g will be explained.

In the case of character output, the comparator 61 compares the binary level H from the CPU 12 with the input data g, and outputs the binary signal I. Further, by using the dither method, the dither ROM 25 and the input data are compared in a comparator 62 as pseudo halftone output, and dither data (halftone data) J
output, and if the operation board is in character mode, C
The data K from the PU 12 becomes 0, and the selector 63 outputs ■ as an L output.

In the case of halftone (photo) mode, the data from the CPU 12 becomes 1, and the selector 63 outputs J to L.

At this time, data M of the CPU 12 corresponding to the selector 72
1-%-M3 becomes O and corresponds to input A of selector 72. A signal will be output.

Also, in marker editing mode, the marker is in the middle 1M?
By supporting m degrees, input documents are basically white/white.
It is assumed that the character document with a clear black ratio, that is, the background, is whiter than the lower limit level of the marker, and the character data is blacker than the upper limit level of the marker. Therefore, if document information that falls within the density level range of the marker falls within a range that is greater than or equal to the marker detection block, erroneous detection may occur.

This occurs when there is a color document, a document with a photographic area, or faint text information, and is also a drawback in marker detection.

Returning to the explanation of marker editing, as explained above, since a character manuscript is targeted, K is 0 during marker editing. A marker detection area (if it is determined to be a marker area, it becomes an H:1 signal) signal comes in from f's, and the following processes can be performed.

(1) Masking 2 In other words, when erasing information in the mark area, the AND gate 67 uses the mark area signal f
The signal obtained by inverting 'Z5 by the inverter 66 and the binary image signal are ANDed, the information in the mark area is erased, the signal is input to the B input of the selector 72, and the commands M1 to M3 of the CPU 12 ;1, M2. By setting M3 to 0, masking data is output to the d output.

(2) Trimming: In other words, when extracting only the information within the mark area, the AND gate 68 performs the AND of the mark area signal f□ and the binary image signal ri, and extracts only the information within the mark area. M2: 1.
By setting Ml and M3 io, masking data is output to the d output.

(3) Black and white reversal inside the marker Image data outside the marker 2 In other words, only the information inside the marker in the image data is inverted in black and white, and the image data outside the marker is output as is.
Input marker signal f of select signal of selector 64
's selects image data and inverted data, and when a mark area signal is generated, inverted data is selected and output. Also, the commands M1 to M3 of the CPU 12 are Ml, M2:1. M3:0.

(4) Outside marker black and white inverted image data inside marker: This is
(3) The signal obtained from the black-and-white inversion inside the marker image data outside the marker is inverted by the inverter 69, and the CP
Commands M1 to M3 of U12 are Ml, M2:0. M3:
It is 1.

(5) Black and white inversion within trimming marker: This is done in the same way as the trimming process in (2) for the image of only the marked area.
The D gate 71 outputs the mark signal and the inverted signal of the image data, and the CPU 1
2 commands M1 to M3 are Ml, M3:1. M2:O
It is.

(6) Masking marker outside black and white inversion: This is an AND operation similar to the masking process in (1) for the image outside the marked area.
The gate 70 outputs the mark signal by the inverter 66 and the inverted signal of the image data.
Commands M1 to M3 of the CPU 12 are Ml:0. M2. M
The ratio is 3:1.

(7) The mark area signal is sent to the command M1 of the CPU 12,
M2. M3: 1 makes the output d.

Next, the memory control section 7 will be explained.

As mentioned above, in the data processing control section 6,
It is possible to edit the mark area, such as extraction, deletion, and inversion of white/black within the mark area.

In addition, the signals output from the data processing control section to the memory control section are (1) normal binarized images (including dithered images) (
2) Output of mark area signal (3) There are three outputs of the mark-edited image, each of which is selected and output to the memory control unit 7, or three outputs are output to the memory control unit 7 in parallel. It's okay. However, in this example, the above output is selected for each different document (mode),
It is output to the memory control section.

The memory that stores images is divided into multiple blocks, and each block is independently controlled.

Examples of this memory are shown in FIGS. 4 to 8 and 23.
As shown in the figure. In this embodiment, it is assumed that there are two memory blocks. First, image storage memories 13a, 13b,
13c, a memory of a bone reading area in the scanner section 4 is secured. For example, the reading density is 4 in the reading area of A3.
In the case of 00 dpi (2971m÷25.4X400
) X (420fl÷25.4x400) #
A memory amount of 4MBYTE is required.

This memory configuration is shown in FIG.

The aforementioned 4MBYTE memory has 32 IMD-RAMs 22 arranged in parallel. In other words, the image data (
IN DATA) is converted by 32-bit serial/parallel converters 20 and 21, and the data is input to each of 32 memories (RAM 22). Therefore, signals 1/32W CLK and 1/32RCLK are generated by dividing the read/write clock WCLK and RCLK by 32. This 1/32W CL K, 1/32RCL K
For example, it is synchronized with WLGATE and RLGATE. Therefore, as described above, the entire area of A3 can be read.

23 and 24 are parallel/serial converters. Also,
As shown in FIG. 4, the memory address is controlled by address counters 14a, 14b, 14c.
14c is the aforementioned 1/32CLK (1/32W CLK for writing, 1/32R for reading)
CL K) and LGATE (WLG for light)
ATE (in the case of reading, RLGATE) is counted up by a clock signal generated by passing the data through AND gates 15a, 15b, and 15c. Also,
FGATE (WFGATE for write, RFGATE for read) as the counter clear signal.
) is controlled by As mentioned above, memory glue/
When writing, it is necessary to switch the clock, LGATB, etc.

FIG. 6 shows signals switched by memory read/write. The selection signal is a read/write controlled by the CPU 12, which determines whether data is written to or read from memory. This lead/
The signal that is switched by the light is 1/32W CL K (
A clock (WCL) synchronized with the above-mentioned input image data
K, ) signal divided by 32) and 1/32RCL K
(a signal obtained by dividing the frequency of the clock (RCL K) that outputs image data to the laser printer 8 by 32) to 1/3
2CLK, and similarly, write signal WLSYNC and read signal RLSY are main scanning direction synchronization signals.
Write signal WLGAT with NC and main scanning effective area signal
E read signal RLGATE and sub-scan effective area signal, write signal WFGATE and read signal RFGATE,
It is switched by read/write.

In addition, in FIG. 8, in order to count the sub-scanning effective area, WLSYNC is divided by n by the frequency divider 29, inputted to the CPU 31 through the I10 controller 30, and then
31 and detects the length of the sub-scanning, and when reading, RLSYNC is divided by n by a frequency divider 33 in the same way as dividing when writing.
Enter the WLSY of WFGATE mentioned above into P U31.
Output the NC portion FGATE and use it as RFGATE. Furthermore, since a D-RAM is used, a refresh circuit is required, but the J refresh circuit uses a known technology and will not be described here. Note that I) -RAM, not 5-RAM
may be used. Note that 19 is an output control section.

FIG. 23 shows a timing chart corresponding to each signal in the main scanning and sub-scanning directions for the original.

Since the maximum size of the document is A3, the A3 width in the main scanning direction becomes valid data and becomes LGATE. Also, FGATE may be the maximum width of the original, and if the original is smaller than the maximum width, FGATE may be the width of the original, or depending on the relationship with the transfer width,
The FGATE width may also be determined. Also, F shown in FIG.
GATE, LSYNC, LGATE when writing memory,
WFGATE.

WLSYNC, WLGATE and when reading memory,
RFGATE, RLSYNC, LGATE.

FIG. 7 shows a composite circuit, 26a, 26b, 26
c, 26d are AND gates, 27 is an inverter, 28a
, 28b is an OR gate, 17 is a selector, DOOT1~
DOOT3 is the output from the first to third memories, and DOO
Tl is a character processed image, DOOT2 is a photo processed image,
DOOT3 is a mark area signal.

In this circuit, the character processed image from DOOTI is ANDed with the inverted mark area signal (by inverter 27).
By passing through the gate 26a, the photo area is erased, leaving only the text area. Furthermore, by passing the photo processed image from DOOT2 and the mark area signal through the AND gate 26b, the character area is erased and only the photo area remains. By combining the text processing and photo processing output from the AND gates 26a and 26b mentioned above at the OR gate 28a, a document containing text and photos is output as a good image.

Also, at this time, the mark area surrounds the photo area, but when surrounding the character area, the AND gates 26c and 26d
, is similarly realized by the OR gate 28b, and
The selector 17 is output from the CPU as a determination signal indicating whether the mark area surrounds the photo area or the character area. Further, an image obtained by inverting the text area and a photo area are combined, and after this process is completed, editing using the mark area and image data as shown in FIG. 10 may be performed.

As described above, by specifying the text/photo area using marks and performing memory composition, it is possible to output a mixed text/photo original as a good image.
Trimming, masking, etc. can also be performed.

As mentioned above, from the first memory to the third memory, respectively,
A text processed image, a photo processed image, and a marker area image are input, and then a good text/photo image can be obtained based on the marker area.

FIG. 27 is a block diagram showing the overall configuration.

78 is a binarization processing unit similar to the above, and 79 is a mark area detection unit similar to the above, and the binary image data from the binarization processing unit 78 and the marker detection signal from the detection unit 79 are In response to a signal from the CPU 81, the memory selector 80 selects and outputs which memory the first . Second. Character images, photographic images, and mark area signals are stored in the third memories 82, 83, and 84, and an editing and synthesis circuit 86 shown in FIG.
simultaneously outputs each image to obtain a character/photo image by marker synthesis.

The operation of the first embodiment configured as described above will be explained based on the flowchart of FIG.

In FIG. 9, first, mode settings are performed (9-1). This mode setting is input from an operation unit not shown. 1. Marker, text/photo area classification, 2. Trimming, masking, Specifies black and white inversion marker editing.

According to the specified mode, first, before reading the document information (text/photo combination) with the reading device, set it to text mode,
The notch level, AE level, etc. are set (9-2), the image is read (9-3), and the image subjected to character processing is input into the first memory 82 (9-4). At this time, no copy is output. After the storage is completed (9-5), set the photo mode, set the notch level, AE level, etc. 9-6), read the image (97), and input the processed image into the second memory 83 (9-6). 9-8). After the storage is completed (9-9), read the paper on which the marker area specifying the photo area or the marker area specifying the text area is written (9-10,
9-1)), Detect mark area 9-12), 3rd
(9-13). Note that the method of inputting data to the first to third memories 82, 83, and 84 is performed as described above. After the storage is completed (9-14), the first.
Second. 9-15) Retrieve image information from 82.83.84 from the third memory 84), separate text and photo areas using marker areas from the third memory 84, combine and output (9-16.9) -17).

This state is shown in FIG. In FIG. 10, the mark area indicates a photographic area, whereby a text-processed image and a photographic-processed image are synthesized.

Note that the document 1 and the paper on which the mark area is written are placed on the contact glass 7 of the copying machine, as shown in FIG.
By abutting against the positioning means 75 provided along the side edge of the document 4 and having the scanner unit 4 read the document, the designation of the mark area and the position of the area of the document to be edited can be easily aligned, and editing can be performed reliably. I can do it.

Further, the paper on which the mark area is written may be constructed in the form of a carrier sheet by fixing one edge of a transparent synthetic resin plate 76 or 77 on at least one side, as shown in FIG. That is, the original 1 is sandwiched between the synthetic resin plates 76 and 77,
By marking a transparent synthetic resin plate 76 located on the surface of the original, it is possible to reliably match the designation of the mark area with the position of the area of the original to be edited.

FIG. 28 and FIG. 29 show a second embodiment of the present invention, with FIG. 29 being a block diagram composed of two memory blocks, and FIG. 30 being a flowchart showing the control operation.

In FIG. 28, 87 is a binarization processing section, 88 is a power detection section, 89 is an editing/synthesizing section, 90 is a CPU, 91 is a memory selector, 92.93 is a first memory controller, and 2.94 is a memory controller. , 95 are selectors.

In FIG. 30, first, areas are divided by marks on the mark area paper to separate character images and photographic images (29-1). The mark sheet on which the area has been written is read by the scanner section 4 (29-2), the signal of the mark area from the marker detection section 88 is passed through the editing/synthesizing section 87, and the signal from the CPU 90 is sent to the memory selector 91. Select which memory to output.

In this embodiment, the mark area is stored in the first memory 92 (29-3, 29-4), and the control for storing is performed by the memory controller 92 after the storage is completed (29-3.29-4).
5) When loading originals with mixed text/photos 29-6
), the scanner section 4 reads it, and the binarization processing section 87 simultaneously performs character processing and photo processing (29-7, 29-
8).

In the case of the second embodiment, the binarized character processing signal I,
The photo processing signal J is directly sent to the editing/synthesizing unit 87 without changing the selector 63 in FIG. 22 as in the first embodiment.
input. At this time, the mark area signal stored in the first memory 92 is read out (29-9), and the read signal is selectively outputted by the selector 95 and inputted into the editing/synthesizing section 89 again.

The character processing, photo processing, and mark area signals are processed as shown in FIG. 7, and the character area is output as a character processed image and the photo area is output as a photo processed image according to the mark area (2!)-10), Memory selector 91
(29-1))
, after completion of storage in the second memory 93 (29-12),
The text/photo image is output to the image output device through the selector 95 (29-13, 29-14).

FIGS. 30 and 31 show a third embodiment of the present invention, and FIG. 30 is a block diagram composed of one memory,
FIG. 31 is a flowchart showing operation control.

In FIG. 30, 96 is a binarization processing section, 97 is a marker detection section, 98 is an editing/synthesizing section, 99 is a CPU, 100 is a selector, 101 is a first memory, and 102 is a memory control.

In FIG. 31, first, areas are divided by marks on the mark area paper to separate character images and photographic images (31-1). The mark sheet on which the area has been written is read by the scanner section 4 (312), and the marker detection section 9
The mark area signal from the first
(31-3.31-4)
. Memory writing and reading are controlled by the memory control 102 as described above. After storage is completed (31-5),
Set the original containing text/photographs (3l-6), read it with the scanner section 4 (31-7), and binarize it with the binarization processing section 9.
6 performs text processing and photo processing at the same time. The binarized character processing signal I and photo processing signal J are directly input to the editing/synthesizing section 98 without going through the selector 63 in FIG. 22 (31-8.31-9). At this time, the mark area signal stored in the first memory 101 is read out.
10) The read signal is input to the editing/synthesizing section 98 (31-9), and the character processing/photo processing marker area signal is processed according to the mark area as described above. The area is output as a photo-processed image and is also input to the first memory 101 (
31-1)). Since this operation is completed within the same time for the addresses, for example, the mark signal of the n address is first read out, and then the mark-edited character/photo image is written. This operation is continued until the reading by the scanner unit 4 is completed, and after the completion, the synthesized character/photo processed image is output from the memory 101 of the cylinder 1 to the image output device (31-1
3.3l-14).

As described above, it is possible to obtain an image with good text processing for similar text areas and photo processing for photo areas, regardless of whether three, two, or one memory blocks are used. Also, as mentioned above, it is possible to combine and edit a mixed image of text/photos using the mark area with only one or two blocks of memory.
Memory control in the case of a block or two blocks will be explained.

FIG. 32 is a block diagram showing a memory control control circuit, and FIG. 33 is a time chart of control operations.

The memory configuration of the two-block memory is the same as described above, but the control method is different. That is, as described above, in order to read the image information stored in the memory block and synthesize the read image information with the image information obtained by the reading means, the write LGATE and read L
GATB, write clock, read clock and write FGATE, read FGATE and write LS
YNC.

It is necessary to set the read LSYNC to the same write control signal. This requires, for example, reading the image data at address n, combining the read image data with the image data read by the reading means into address n of another memory block, and storing the combined image data. This is because there is. Therefore, for example, taking the memory 13a in FIG. 4 mentioned above as an example, the read control signal for the memo January 3a is as shown in FIG.
, WFGATE and R of the memory 13a in FIG.
This is achieved by setting the /w1 signal to read. Also, R/w in this figure 6 and R/w in figure 4.
wl is controlled by the CPU.

Next, one block memory will be explained.

The memory configuration of one block memory is the same as above, but
Control methods are different. That is, in order to read out the image data stored in the memory block as described above and synthesize the read image information with the image information obtained by the successive output means, the aforementioned write LGATE and read LG are used.
ATE and write clock, read clock and write FGATE, read FGATE and write L
SYNC.

It is necessary to make the read LSYNC the same write control signal. For example, this reads the image data at address n, combines the read image data and the image data read by the reading means into address n of another memory block, and stores the combined image data. This is because it is necessary. Up to this point, the control operation is the same as the control operation of the 2-block memory described above, but the 2-block memory read/write described above reads 1' image information or transfers 1 image from the memory block. When reading a block, the read/write signal for a memory is fixed, whereas for a block memory, it is necessary to switch the read/write signal at one address. Taking January 33 as an example, the read control signal of memo January 3a changes to write mode R/wi#I? in Figure 6. Execute il signal, 1/31WC
Select LK, WLGATE, WLSYNC, and WFGATE.

As shown in Figure 32, R/w 1 and 1/3 of Figure 4
2 CLKI (here 1/32W CLKI)
is set to 1/32CL K 1 as R/w 1' by the signal P from the CPU, and the address n is set as shown in Fig. 33.
The data at the address I)+(n)) is read, and the composite data (Dl(n)) of that data and the data obtained by the reading means described above is written to the same address n.

As mentioned above, the memory only requires one memory block,
Also, the two memory blocks described above may be used.

Furthermore, this R/w in Fig. 6 and R/w in Fig. 4
1 is controlled by the CPU.

In the first embodiment configured in this way, for a text/photo mixed original, (1) the character processed image is stored in the first memory, and 2) the photo processed image is stored in the second memory. , 3) Store a mark area signal in a third memory, distinguish between a text area and a photo area based on the mark area signal in the third memory, and
Since the image information signals read from the memory are selectively outputted, it is possible to obtain a good image of a mixed text/photograph original in which the text portion is processed with text and the photo portion is processed with photo processing.

Furthermore, since the area setting is specified using marks, it is possible to easily set an area with a complex shape.

Further, the second and third embodiments also provide the same effects as the first embodiment, and can also reduce the amount of memory.

〔Effect of the invention〕

As described above, according to the present invention, a good image can be obtained by performing literature processing on text portions and photo processing on photo portions of text/photo mixed manuscripts.

[Brief explanation of drawings]

1 to 27 show a first embodiment of the present invention, FIG. 1 is a block diagram of an image editing apparatus according to the present invention, and FIG. 2 is a perspective view illustrating reading of a document by a scanner. , FIG. 3 is an explanatory diagram showing the relationship between image data and mark area detection signals, FIGS. 4 to 8 are blocks configuring the memory controller, FIG. 4 is a block diagram of two image storage memories, and FIG. Figure 5 is a block diagram showing the configuration of the image storage memory, Figure 6 is an explanatory diagram showing signals switched by reading/writing to the memory, Figure 7 is a block diagram showing the synthesis circuit, and Figure 8 is the sub-scanning effective area. FIG. 9 is a flowchart showing control of image editing, FIG. 10 is an explanatory diagram explaining the image editing process, and FIG.
) is a block diagram showing the density determination circuit and 1-pixel noise removal circuit, FIG. 12 is a time chart for explaining 1-pixel noise removal, FIG. 13 is a block diagram of the mark area detection circuit, and FIG. 14 (a ), (b) is the first
, an explanatory diagram explaining the function of second sub-scanning mark detection, first
Figure 5 is an explanatory diagram showing the expansion of the mark area, Figure 16 is a block diagram of the black line prevention circuit, and Figure 17 is a diagram showing a state in which a black line enters a mark and the mark is interrupted, and each signal corresponding to this. 18 is a block diagram of the mark area detection unit, FIG. 19 is a plan view showing an example of a marked document, and FIGS. 20 and 21 are each signal when detecting the document in FIG. 19. Figure 22 is the time chart showing the 3rd
Figure 23 is a detailed block diagram of binarization and editing. Figure 23 is a timing chart corresponding to each signal in the main scanning and sub-scanning directions for the original. Figure 24 shows the relationship between output data corresponding to editing data from the CPU. 25 is a side view showing a modification of the specifying means, FIG. 26 is a plan view showing the positioning means, FIG. 27 is a block diagram showing the overall configuration, and FIG.
FIG. 29 shows a second embodiment of the present invention,
FIG. 28 is a block diagram showing the overall configuration, FIG. 29 is a flow chart showing control operations, FIGS. 30 and 31 show a third embodiment of the present invention, and FIG. 30 shows the overall configuration. A block diagram, FIG. 31 is a flowchart showing the control operation, FIGS. 32 and 33 explain the control of memory control in the second and third embodiments, FIG. 32 is a block diagram, and FIG. 33 is a flowchart showing the control operation. is a time chart. l...Original, 4...Scanner section, 5.
...Video processing circuit, 6...Data processing control section, 7...Memory control L
78,87.96...Binarization processing unit, 79,
88.97... Marker detection section, 80.90.9
9...CPU, 81.91...Memory selector, 82,92,101...First memory, 83.93...Second memory Memory, 84・
...Third memory, 85, 94. IO2...
・・Memory control, 86.89.98・・・・
・Editing/Composition Department, 95.100...Selector. Fig. 1 Fig. 2 Fig. 4 Fig. 7 Fig. 1 O Fig. Mark detection Fig. 5 Fig. 6 Fig. 15 Fig. 15 Sagging Fig. 16 C Figure 24 Figure 25 Figure 26

Claims (2)

[Claims] (1) a plurality of reading means for reading a document image and generating image information; a specifying means for specifying a desired area of the document; and a generating means for generating an area signal indicating the desired area in accordance with the area specification by the specifying means; a storage means for composing a plurality of pieces of image information, a means for binarizing the image information generated by the reading means, and an image generated by the reading means; means for pseudo-halftone processing information; and writing in the storage means;
The controller further comprises a control means for controlling reading, wherein the control means stores an area signal indicating the desired area in the storage means, the control means reads out the area signal from the storage means, and the storage composition means reads out the area signal from the storage means. An image editing device characterized in that a binarized image and a pseudo-halftone-processed image are synthesized using the desired area signal. (2) a plurality of reading means for reading a document image and generating image information; specifying means for specifying a desired area of the document; and generating means for generating an area signal indicating the desired area in accordance with the area specification by the specifying means; a plurality of storage means capable of storing image information, a composition means for combining image information read from the plurality of storage means, a means for binarizing the image information generated by the reading means, and the reading means. and control means for controlling writing and reading of the plurality of storage means, the binarized image and pseudo-halftone processing being carried out in the plurality of storage means. The processed image and the area signal indicating the desired area are stored by the control means, and the binarized image, the pseudo-halftone processed image, and the desired area signal are stored by the storage means by the plurality of storage means. An image editing apparatus characterized in that an image read from a target area and binarized by the combining means and an image subjected to pseudo halftone processing are combined using the desired area signal.