JPH0349437A - Separation circuit - Google Patents

Abstract

PURPOSE:To reduce the number of circuits ought to be operated at the same high speed as that of an input signal by performing bit switching at a matrix circuit after performing the S/P conversion of a block interleave multiplex signal, and performing block separation after performing P/S conversion. CONSTITUTION:The circuit is equipped with a first serial/parallel conversion circuit 18 which separates the input signal to 1/multiple numbers bit by bit, second serial/ parallel conversion circuits 19 and 20 which further convert the output of the circuit 18 to a parallel signal of (n+1) bits, a matrix circuit 21 which rearranges the sequence of the bits that are the output of the circuits 10 and 20 in the same sequence as that of nBlPcode input, parallel/serial conversion circuits 22 and 23 which input the output of the circuit 21 by every (n+1) bits and convert them to serial signals, and parity count circuits 24 and 25 which count the parity of the output signals of the circuits 22 and 23. An output switching circuit 29 which switches the sequence to output the input signals from the parallel/serial conversion circuits 22 and 23 to a frame synchronization circuit, frame synchronization circuits 30 and 31 when a large error rate exists furthermore are provided. In such a way, it is possible to evade necessity to operate the parity count circuits 24 and 25, and the output switching circuit 29 at the speed same as that of a multiplexed signal.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a digital communication system, and more particularly to a separation circuit that uses nB1P as a transmission path code, inputs block interleaf multiplexed signals with nB1P as one block, and outputs separated signals. [Prior Art] nB1P is a transmission line code used in a digital communication system. A block interleaf multiplex signal in which nB1P is one block will be explained using FIG. here,
An example will be explained in which two 4B1P transmission line codes are multiplexed. 13 in Figure 3. 14 indicates a data string before multiplexing. l block (Bl-1, Bl-2, Bl-3, B2-
1.82-2, B2-3) consists of 4 bits of data pits and 1 bit of parity bit. l5
indicates a data string after block interleaf multiplexing. nB
1P blocks are Bl-1, B2-1, Bl-2, B2
-2, Bl-3, and B2-3 are arranged in this order. Also, each data string 13. 14 each has a frame including a frame synchronization signal, and each frame has a different frame synchronization signal or a channel identification signal is inserted into the frame, so that each data string 13, l4 It shall be possible to distinguish between Next, in the conventional separation circuit, the block interleaf multiplexed signal 1 is input to an output switching circuit 3 and a parity counting circuit 4, as shown in FIG. The block interleaved nB1P data is (n+1) in the parity counting circuit 4.
The number of "l" levels in a bit can be counted repeatedly. nB
If the position where the 1P code starts and the position where the parity counting circuit 4 starts counting match, the pulse output from the counting circuit 4 to the error rate detection circuit 5 matches an error in the input data, for example, When the error rate is 10"-", the output of the parity counting circuit 4 also outputs error pulses at a rate of 10-". On the other hand, the position where the nB1P code starts and the parity counting circuit 4
If the counting start position and the counting start position do not match, the error rate of the output of the parity counting circuit 4 will be approximately 1/2. The error rate detection circuit 5 monitors the output of the parity counting circuit 4, and if the error rate is large, it determines that the parity counting circuit 4 is not synchronized with the nB1P code, and the clock stop circuit 6 detects the parity counting circuit 4. The position at which the parity counting circuit 4 starts counting is set at 1 by 1 bit missing the clock supplied to the
After delaying the bit, the output of the parity counting circuit 4 is monitored again, and this is repeated until the output error rate becomes sufficiently smaller than 1/2. The parity counting circuit 4 outputs a signal indicating the position to start parity counting to the output switching circuit 3, and at this timing, the output switching circuit 3 transfers (n+1) bits to the speed conversion circuits 7 and 8.
output in order. After the parity counting circuit 4 is synchronized with the nB1P code by the above operation, the output switching circuit 3 is
(n+1) bits separated by the period of the B1P code can be output to the speed conversion circuits 7 and 8. The burst data of (n+1) bits sequentially written to the speed conversion circuits 7 and 8 is speed-converted to the average speed of the writing speed, and the data is output to the frame synchronization circuits 9 and 1O. The frame synchronization circuit 9.10 performs frame synchronization from the input data string, but when the output switching circuit 3 sequentially outputs the nBfP code string to the speed conversion circuits 7 and 8, the nB1P code string on the channel i side is transferred to the speed conversion circuit. 7, n on the channel ■ side
If the B1P code string is not output to the speed conversion circuit 8, the frame synchronization circuits 9 and 10 output a signal indicating that the channel is not being output correctly to the output switching circuit 3, and the speed conversion circuits 7 and 8 Perform an operation to replace the signals that are being output. By the above operations, the separated signal output 11. Get 12.

[Problem to be solved by the invention]

In the conventional separation circuit described above, the block interleaf multiplexed signal is directly input to the parity counting circuit 4 and the output switching circuit 3, so the parity counting circuit 4 and the output switching circuit 3 operate at the same speed as the multiplexed signal. The drawback is that you have to do it. An object of the present invention is to provide a separation circuit that solves the above problems. [Means for Solving the Problems] In order to achieve the above object, the separation circuit of the present invention provides an nB1
A separation circuit that receives a block interleaf multiplexed signal in which one block is a P code and outputs a separated signal, a first serial-to-parallel conversion circuit that separates an input signal bit by bit into 1/the number of multiplexed signals; a second serial-to-parallel conversion circuit that further converts the output of the serial-to-parallel conversion circuit into an (n+1)-bit parallel signal, and the bits of the output of the second serial-to-parallel conversion circuit are arranged in the same order as the nB1P code input. A frog matrix circuit, a parallel-to-serial conversion circuit for inputting the output of the matrix circuit (n+1) bits at a time and converting it into a serial signal, and counting the parity of the output signal of the parallel-to-serial conversion circuit, and calculating the counting result and the signal. a parity counting circuit that outputs an error pulse by comparing the parity with the parity of the parity, an error rate detection circuit that counts the error pulse output from the parity counting circuit and converts it into an error rate, and monitors the output of the error rate detection circuit. If the error rate is large, a clock stop circuit that outputs a clock to the second serial-to-parallel converter, parallel-to-serial converter, and parity counting circuit is provided with a one-bit missing clock, and a control signal from the frame synchronization circuit is used. An output switching circuit that switches the order in which input signals from the parallel-to-serial conversion circuit are output to the frame synchronization circuit; and a frame synchronization circuit that synchronizes the frames from the signal of the output switching circuit, and outputs an output order switching request signal when frame synchronization cannot be achieved. It includes a frame synchronization circuit that outputs to an output switching circuit. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 18 is a serial-to-parallel conversion circuit (hereinafter referred to as an S/P conversion circuit) that separates the input signal bit by bit into 1/the number of multiplexes; 19. 20 is a serial-to-parallel conversion circuit (hereinafter referred to as S/P) which further converts the output of the serial-to-parallel conversion circuit l8 into an (n+1) bit parallel signal.
(referred to as a conversion circuit), 21 is a serial-parallel conversion circuit 1
9. This is a matrix circuit that rearranges the bits of the 20 outputs in the same order as the nB1P code input. 22. 23
24. is a parallel-to-serial conversion circuit (hereinafter referred to as a P/S conversion circuit) that inputs the output of the matrix circuit 2l (n+1) bits at a time and converts it into a serial signal; 25 is a parallel-to-serial conversion circuit 22. a parity counting circuit that counts the parity of the output signal of 23, compares the counting result with the parity in the signal, and outputs an error pulse; 26. 2
7 is a parity counting circuit 24. 25 is an error rate detection circuit that counts the output error pulses and converts it into an error rate; 28 is an error rate detection circuit that monitors the output of the error rate detection circuits 26 and 27, and when the error rate is large, serial-parallel conversion circuits 19, 20,
Parallel-serial conversion circuits 22, 23, parity counting circuit 24. This is a clock stop circuit that outputs a clock to 25 with one bit missing. 29 is a frame synchronization circuit 30. The parallel-to-serial converter circuit 22. The input signal from 23 is sent to the frame synchronization circuit 30. an output switching circuit for changing the order of output to 31; 30. Reference numeral 31 denotes a frame synchronization circuit that synchronizes frames from the input signal from the output switching circuit 29 and outputs an output order change request signal to the output switching circuit 29 when frame synchronization cannot be achieved. In the embodiment, the block interleaf multiplexed signal l6 undergoes serial-to-parallel conversion (S/P conversion) to a multiplex number of 17 in the S/P conversion circuit 18, and then is sent to the S/P conversion circuit 19.2.
Input to 0. The S/P conversion circuits 19 and 20 S/P convert the input signal to (n+1) and send it to the matrix circuit 2l.
Output to . The matrix circuit 2l is an S/P conversion circuit l9
Swap the ■■■■■ input from the S/P conversion circuit 20 and the ■■■■ [phase] input from the S/P conversion circuit 20, and input the ■■■■■ to the P/S conversion circuit 22 and the input to the P/S conversion circuit 23.は■■■■ [phase]
Output each. P/S conversion circuit 22. The output signals of 23 are respectively sent to parity counting circuits 24. At 25 (n
+1) The number of "l" levels in a bit can be counted repeatedly. S/P conversion circuit 19. If the above operation is performed when the nB1P code is input to each of the counting circuits 24. 25 is an error rate detection circuit 26. The pulse output to 27 corresponds to an error in the input data. On the other hand, nB
1P code starting position and S/P conversion circuit 19. 20 is different from the position where the S/P conversion is performed, the counting circuit 2
4.25 output has an error rate of approximately 1/2. Error rate detection circuit 26. 27 is a parity counting circuit 24. 25, and if the error rate is large, it is determined that the block separation of the nB1P input signal is not synchronized with the nB1P code, and the clock stop circuit 28 changes the clock input from the S/P conversion circuit 18 to 1 bit. As a precaution, the operations of the S/P conversion circuits 19, 20, P/S conversion circuits 22, 23, and parity counting circuits 24.25 are delayed by l bit, and the operations of the counting circuits 24.25 are delayed by l bit. 25 outputs are monitored, and the output error rate is l/
Repeat this until it becomes sufficiently smaller than 2. By the above operation, the P/S conversion circuits 22 and 23 are nB1
The (n+1) bits separated by P codes can be separated and output to the output switching circuit 29. The output of the output switching circuit 29 is sent to the frame synchronization circuits 30 and 3I.
However, if the output switching circuit 29 does not output the nB1P code on the channel I side to the frame synchronization circuit 30 and the channel ■ side to the frame synchronization circuit 3l, the frame synchronization circuit 30 ．． 31 outputs a signal indicating that the channel is not being output correctly to the output switching circuit 29, and performs an operation to replace the output signal. By the above operation, the separated signal output 32. Get 33. [Effects of the Invention] As explained above, the present invention performs S/P conversion on a block interleaf multiplexed signal, then performs bit swapping in a matrix circuit, performs P/S conversion, and performs block separation, thereby converting the input signal into This has the effect of reducing the number of circuits that must operate at the same high speed.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2
FIG. 3 is a block diagram showing a conventional separation circuit. FIG. 3 is a diagram showing an nB1P code string subjected to block-increase multiplexing. 18, 19. 20...5, JP conversion circuit 2
1...Marix circuit 22.23...P/S conversion circuit 24.25...Validity counting circuit 26.27...Error rate detection circuit 28...Clock stop circuit 29... Output switching circuit 30, 3]...
Frame synchronization circuit 32.33...minute 1! signal output

Claims (1)

[Claims] (1) A first serial-to-parallel conversion circuit that separates an input signal bit by bit into 1/the number of multiplexes in a separation circuit that receives a block interleaf multiplexed signal in which one block is an nB1P code and outputs a separated signal; a second serial-to-parallel conversion circuit that further converts the output of the first serial-to-parallel conversion circuit into an (n+1)-bit parallel signal; and a bit order of the output of the second serial-to-parallel conversion circuit is set to an nB1P code input. A matrix circuit that rearranges the same order and the output of the matrix circuit (n+1
) A parallel-to-serial conversion circuit that inputs bits bit by bit and converts it into a serial signal, and a parity unit that counts the parity of the output signal of the parallel-to-serial conversion circuit and compares the counting result with the parity in the signal to output an error pulse. a counting circuit; an error rate detection circuit that counts error pulses output from the parity counting circuit and converts the result into an error rate; and a second error rate detection circuit that monitors the output of the error rate detection circuit and if the error rate is large, A clock stop circuit that outputs the clock to the serial-to-parallel converter, parallel-to-serial converter, and parity counting circuit by one bit, and a control signal from the frame synchronizer to convert the input signal from the parallel to serial converter to the frame synchronizer. The output switching circuit includes an output switching circuit that switches the output order, and a frame synchronization circuit that synchronizes frames from the signal of the output switching circuit and outputs an output order switching request signal to the output switching circuit when frame synchronization cannot be achieved. A separation circuit featuring: