JPH034996B2 - - Google Patents

Description

Detailed Description of the Invention The present invention mainly relates to metal-insulating film-semiconductor (hereinafter referred to as
The present invention relates to a word line driving method for a memory device (hereinafter referred to as memory) using transistors (referred to as MIS).

FIG. 1 is a plan view of the main circuit blocks of a memory chip, which consists of memory cell blocks 1 and 2 constituting two memory element groups, and a row decoder 3 arranged between them corresponding to the row. and,
It is composed of column decoders 4 and 5 arranged corresponding to the columns of each memory cell block.

FIG. 2 is a conventional circuit showing the connection relationship between row decoders XD ₀ to _{XD (o-1)} , word lines W ₀ to W _(o-1), and memory elements in the memory chip shown in FIG. In the configuration, a total of n row decoders XD ₀ to XD ( _{o-1) from 0 to (n-1)} arranged between memory element groups 1 and 2 as described above are selected. It operates by setting only the voltage level of the word line of the row to "High" and setting the voltage level of all other word lines to "Low". For example, when row 0 is selected, only the output voltage level of row decoder XD ₀ is “High”.
The output voltage level of XD ₁ to _{XD (o-1)} becomes “Low”.

Therefore, only the word line W ₀ becomes “High” and all other word lines W ₁ to _{W (o-1)} become “Low”,
All memory elements in the 0th row of memory element groups 1 and 2 will be selected, and all that is left to do is to select one necessary column using the column decoder, and only one element at this intersection will be selected. The Rukoto.

However, such conventional memory devices
Since the word lines W ₀ to W _(o-1) are shared by the two memory element groups 1 and 2, they have a large stray capacitance, and the row decoder placed in the center must drive this large stray capacitance. This has the disadvantage that it takes a long time to select a memory element.

For example, if the word line Wi is selected, the word line is “High” across all columns for that row.
Therefore, for example, when a memory element is configured with a static type circuit as shown in Figure 3, for all memory elements in the same row, one of a pair of bit lines is connected to the memory element. This has the disadvantage that current flows into it.

That is, when "High" is stored at node 19 and "Low" is stored at node 20 in FIG.
Since the MIS transistor 14 is conductive, current flows through the path from power supply to load 18 to MIS transistor 16 to MIS transistor 14 to ground, and "Low" is stored at node 19 and "High" is stored at node 20. When the current is on, conversely, current flows through the path of load 17 - MIS transistor 15 - MIS transistor 13 - ground. This current flowing from the bit line is unavoidable in static memory circuits, and the drawback of conventional circuits is that the current flows through all rows and columns, including memory element groups 1 and 2, resulting in extremely high power consumption. That's what it means.

The present invention has been made in order to eliminate the drawbacks of conventional memories as described above, and includes a signal transmission transistor for each word line of a static memory element group shared on the left and right sides of a row decoder. A discharge transistor is provided between each word line and a predetermined potential point, and only the word line to which the selected memory element is connected is activated via the signal transmission transistor, and the selected memory element is activated via the signal transmission transistor. A discharge transistor provided on each word line of a memory element group that does not include any element is turned on to short-circuit those word lines to a predetermined potential point.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In Figure 4, T _OL ~ _{T (o-1)L} and [T _OR ~
T _(o-1)R is a MIS transistor for signal transmission,
Q _OL ~Q _(o-1)L and Q _OR ~Q _(o-1)R drive the word line to a predetermined potential point, such as a fixed potential at or near the ground potential point, when the word line is in a floating state. This is a MIS transistor for discharge. Aα1, Aα2,
Aα1 and Aα2 are signals obtained by inverting the column selection address signal Aα using an inverter or the like, or performing desired processing such as amplification. As shown in the figure, signal 1 is input to the gate of MIS transistor T _OL ~ T _(o-1)L for signal transmission to memory element group 1, and MIS transistor T _{OR ~} for signal transmission to memory element group 2.
The signals Aα1 input to the gate of T _(o-1)R are inverted to each other, and are used for discharging memory element group 1.
Signal Aα2 is input to the gate of MIS transistor Q _OL ~Q _(o-1)L , and signal 2 is input to the gate of MIS transistor Q _OR ~Q _(o-1)R for discharging to memory element group 2. They are in an inverted relationship. Moreover, address signals Aα1 and Aα2 are also in an inverted relationship with each other,
Aα1 and Aα2 are also in an inverted relationship with each other. Therefore
Aα1 and Aα2 may be the same signal, 1
and 2 may also be the same signal.

The operation in this embodiment will be explained below. Now, the column selection address signal Aα is “High” and the above signals Aα1, Aα2 are “High”, 1, 2
is “Low”, and the 0th row is selected, the output of row decoder XD ₀ is “High”, and the outputs of other row decoders XD ₀ to XD _(o-1) are “Low”.
Consider the case where . At this time, the MIS transistor
T _OR ~T _(o-1)R and Q _OL ~Q _(o-1)L are in the on state and have low impedance, and the MIS transistor
T _OL ~ _{T (o-1)L} and Q _OR ~Q _(o-1)R are in a cut-off state, resulting in high impedance. As a result, the row decoder signal is not transmitted to memory element group 1, and the MIS
It is made unselected by transistors T _OL to T _(o-1)L . On the other hand, for memory element group 2, all row decoder signals are transmitted, but “High” is XD ₀
In the end, only the word line W _OR becomes “High” and is activated, and all other word lines W _1R ~
W _(o-1)R and W _OL to W _(o-1)L become “Low”.

Therefore, row decoder XD ₀ outputs the word line W _OR of the selected row (row 0) of selected memory element group 2.
The word line _WOL of the unselected memory element group 1 in the same row is not driven. In other words, the load capacitance driven by the row decoder is only the stray capacitance of the memory element group on one side, which is reduced by approximately half compared to the conventional circuit system. Therefore, the on-resistance of MIS transistors T _OL ~ T _(o-1)L , T _{OR ~} T _{(o-1 )R} can be expressed as
If made small enough, word lines can be driven approximately twice as fast as conventional circuits.

Further, according to the present invention, since none of the word lines of the unselected memory element group is activated, it is possible to eliminate the current flowing into the memory element from the bit line of the unselected memory element group, and the word line of the unselected memory element group is not activated. The current flowing through the device can also be reduced to half of the conventional one, making it easier to reduce the power consumption of memory chips. Furthermore, since each word line is fixed at a predetermined potential by a discharge transistor provided on each word line of the memory element group that does not include the selected memory element,
There is no risk of malfunction, etc.

Above, the present invention has been explained with respect to the case where it is configured with N-channel MIS transistors, but P-channel
The present invention can be applied to MIS memory using MIS transistors as well as memory using bipolar transistors.

As described above, according to the present invention, word lines of unselected memory element groups are not activated, and
Since these word lines are configured to be fixed at a predetermined potential, a static type semiconductor memory device that is high speed, consumes low power, and has no risk of malfunction can be obtained.

[Brief explanation of the drawing]

Figure 1 is a plan view of the main circuit blocks of a memory chip, Figure 2 is a circuit diagram of the main parts of a conventional memory, and Figure 3 is a plan view of the main circuit blocks of a memory chip.
The figure is a circuit diagram of a static type memory element, and FIG. 4 is a circuit diagram of a main part showing an embodiment of the memory of the present invention. 1...Memory element group, 2...Memory element group,
XD ₀ ~XD _(o-1) ...Row decoder, W _OR ~W _(o-1)R and W _OL ~W _(o-1)L ...Word line, T _OR ~T _(o-1)R and
T _OL ~T _(o-1)L ……Signal transmission transistor, Q _OR ~
Q _(o-1)R and Q _OL ~Q _(o-1)L ...discharge transistor.

Claims (1)

[Claims] 1. A first memory element group having a first word line group consisting of a plurality of word lines to which static memory elements are connected, and a second word line consisting of a plurality of word lines to which static memory elements are connected. a second memory element group having a second memory element group, and a word line in the same row of the first and second word line groups arranged between the first and second memory element groups so as to be located on the left and right sides; a row decoder provided in common to each of the row decoders, and a row decoder provided between the row decoder and the first and second memory element groups and connected to each word line of the first and second word line groups; and a discharging transistor provided between each word line of the first and second word line groups and a predetermined potential point, the output signal of the row decoder is transmitted. At the same time, a signal based on the column selection address signal is applied to the signal transmission transistor connected to the first word line group, and a signal based on the column selection address signal is applied to the signal transmission transistor connected to the second word line group. A signal having an inverse relationship with a signal based on the column selection address signal is applied to the discharge transistor provided in each word line of the first word line group. A signal having an inverse relationship with a signal based on the selection address signal is applied, and a signal in phase with the column selection address signal is applied to the discharge transistor provided in each word line of the second word line group. of the word lines in the selected row to which the selected static memory element is connected is activated through the signal transmission transistor, and the word line including the selected word line is activated. A semiconductor memory device in which the discharge transistors provided in a line group are turned off, and the discharge transistors provided in a word line group that does not include the selected word line are turned on.