JPH0350516B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention is applicable to the NTSC system and the video tape recorder.
This invention relates to a tracking servo device for switching between PAL systems.

1. Problems with the Conventional Structure FIG. 1 shows a typical block diagram of the servo system of a home video tape recorder during playback. In Figure 1,
Reference numeral 1 denotes a cylinder motor that drives a rotating cylinder to which a head for recording and reproducing video signals is attached. A position detector 3 that generates a single position detection signal is connected.

The output signal of the frequency generator 2 is amplified and waveform-shaped by a frequency power generation signal (hereinafter referred to as FG signal) amplifier 4, and its output is supplied to a frequency divider 5 and a controller 6, and the output signal is supplied to a frequency divider 5 and a controller 6. The output is a phase detection signal (hereinafter referred to as PG signal)
The signal is amplified and waveform-shaped by an amplifier 7, and its output is supplied as a reset signal to the frequency divider 5 and a 1/2 frequency divider 8.

Furthermore, the output signal of the clock generator 9 is transmitted to the frequency divider 1.
0, and the output signal of the frequency divider 10 is supplied to a cylinder phase system counter 11, a cylinder speed system counter 12, a capstan phase system counter 32 (described later), and a capstan speed system counter 28 (described later).
are respectively supplied as clock signals.

The number of bits of the cylinder phase system counter 11 is
It has a 16-bit configuration, and preset data is supplied from a 16-bit cylinder phase read-only memory (hereinafter referred to as ROM) 13, and its output is supplied to a decoder 14 and a 10-bit latch 15. 15 is supplied with data of the lower 10 bits including the least significant bit (hereinafter referred to as LSB) of the 16-bit output data. ],
The output of the decoder 14 is used as a preset signal to the cylinder phase system counter 11 and the delay circuit 16.
The output of the latch 15 is data 10.
The signal is supplied to a bit digital-to-analog converter (hereinafter referred to as a DA converter) 17.

Further, the output of the frequency divider 8 is supplied to the latch 15 as a load signal, and the output of the frequency divider 8 is supplied to the latch 15 as a load signal.
The first output of the 8-bit latch 18 is supplied as a load signal, and the second output is supplied as a preset signal to the cylinder speed counter 12.

The cylinder speed system counter has a 12-bit configuration, and a 12-bit cylinder speed system ROM
The preset data is supplied from the latch 19, and of the output data, the lower 8 bits including the LSB are supplied to the latch 18.
The output data is an 8-bit D-A converter 20.
is supplied to.

Furthermore, the D-A converter 17 and the D-A converter 17 and the D-A converter 17 and
The outputs of the A converter 20 are combined by a combining circuit 21, and the output signal of the combining circuit 21 is supplied to a cylinder motor drive circuit 22.

On the other hand, a frequency generator 24 is connected to a capstan motor 23 for running the magnetic tape, and the output signal of the frequency generator 24 is amplified and waveform-shaped by an FG signal amplifier 25 and then sent to a controller 26. The first output of the controller 26 is supplied as a load signal to an 8-bit latch 27, and the second output is supplied as a preset signal to a 10-bit capstan speed counter 28.

Also, a control head 29 plays back control signals recorded on the magnetic tape at regular intervals.
The output signal is amplified and waveform-shaped by a control signal amplifier 30, and then supplied to a 10-bit latch 31 as a load signal.

The capstan speed counter 28 and 15
A clock signal is supplied from the frequency divider 10 to each of the bit capstan phase system counters 32.

The capstan phase system counter 32 has 15
Preset data is supplied from the bit capstan phase system ROM 35, and a preset signal is also supplied from the delay circuit 16. Of the output data, the lower 10 bits including the LSB are supplied to the latch 31, The output data of 31 is supplied to a 10-bit DA converter 33.

Preset data is supplied to the capstan speed system counter 28 from a 10-bit capstan speed system ROM 34, and among the output data,
The lower 8 bits of data including the LSB are supplied to the latch 27, and the output data of the latch 27 is supplied to an 8-bit DA converter 36.

Furthermore, the D-A converter 33 and the D-A converter 33 and the D-A converter 33 and the D-A converter 33 and
The outputs of the A converter 36 are combined by a combining circuit 37, and the output signal of the combining circuit 37 is supplied to a capstan motor drive circuit 38.

In addition, the output of the NTSC/PAL switching circuit 39 is the cylinder phase system ROM 13, cylinder speed system
It is supplied to the ROM 19, the capstan phase system ROM 35, the capstan speed system ROM 34, and the decoder 14.

In FIG. 1, it is assumed that a frequency generator 2 connected to a cylinder motor 1 generates an AC signal of 6 cycles per rotation, and a frequency divider 5 is set to 1/3.
It is assumed that the frequency divider 8 performs a frequency division operation of 1/2.

Therefore, in the NTSC specification, cylinder motor 1
The reference frequency is 1800 rpm, and at this time, the output frequency of the frequency generator 2 is 180 Hz, and the output frequency of the position detector 3 is 30 Hz. In addition, in the PAL specification, the reference frequency of cylinder motor 1 is
1500 rpm, and at this time, the output frequency of the frequency generator 2 is 150 Hz, and the output frequency of the position detector 3 is 25 Hz.

Further, a clock signal of a constant frequency is supplied to the cylinder phase system counter 11, and when a predetermined count value is reached, the decoder 14 generates an output pulse, so that the output of the decoder 14 is a reference phase signal of the cylinder phase system. At the same time, the signal passes through the delay circuit 16 for tracking adjustment and becomes a reference phase signal of the capstan phase system.

Furthermore, since the control head 29 obtains a control reproduction signal that depends on the running phase of the magnetic tape, the output signal of the control signal amplifier 30 becomes a running phase signal of the capstan phase system.

On the other hand, the FG signal amplifier 4 obtains a rotational speed signal of the rotating cylinder, and the FG signal amplifier 25 obtains a rotational speed signal of the capstan.

At the leading edge of the output signal of the FG signal amplifier 4, the controller 6 first latches the count value of the cylinder speed counter 12.
8, and subsequently generates a preset signal for the cylinder speed counter 12.

In addition, the capstan speed controller 26
The operation of is also the same as that of the controller 6.

Therefore, the cylinder phase system latch 15 holds the measurement result of the phase difference between the rotational phase signal of the cylinder system and the reference phase signal, and the cylinder speed system latch 18 holds the measurement result of the period of the rotational speed signal. Similarly, the latch 31 of the capstan phase system holds the measurement result of the phase difference of the capstan system, and the latch 27 of the capstan speed system holds the measurement result of the period of the rotational speed signal of the capstan.

A detailed explanation of these operations can be found in Japanese Patent Publication No. 53-19745 or U.S. Patent No.
Since this is done in the specification of No. 3836756, it will be omitted here.

The output of the latch 15 (measured output of the cylinder phase counter 11) is converted into a DC voltage by the DA converter 17, and the latch 18 (measured output of the cylinder speed counter 12) is converted to a DC voltage by the DA converter 17. Therefore, it is converted into a DC voltage, and these DC voltages are combined by a combining circuit 21 to create an error output signal for the cylinder system, and the error output signal is used to generate a cylinder motor drive circuit 22.
Cylinder motor 1 is driven via.

Further, the output of the latch 31 (measured output of the capstan phase system counter 32) is converted into a DC voltage by the DA converter 33, and the output of the latch 27 (measured output of the capstan speed system counter 28) is converted to a DC voltage by the DA converter 33. 36 into a DC voltage, these DC voltages are combined by a combining circuit 37 to create a capstan system error output signal, and the error output signal is output via a capstan motor drive circuit 38. The capstan motor 23 is driven.

FIG. 2 is a time chart showing the tracking state of the cylinder phase system and capstan phase system in the block diagram of FIG. 1 in the NTSC mode. In FIG. 2, 1a is the output of the cylinder phase system counter 11, 1b is the output of the frequency divider 8,
1c represents the output of the delay circuit 16, 1d represents the output of the capstan phase system counter 32, and 1e represents the output of the control signal amplifier 30, respectively. The first reference phase signal output from the decoder 14 at time _t1 causes the cylinder phase system counter 1 to
1 is preset and the delay circuit 16 is triggered. The delay time of the delay circuit 16 is set to 16.7 msec, which corresponds to one half of one period of the reference phase signal in the NTSC mode. (Here, it is assumed that the value of the variable resistor for fine-tuning the delay time is set to the center value.) The delay circuit 16 is triggered at time _t1 , and the capsyn is activated at time _t2 after the set delay time has elapsed. A preset signal for the phase system counter 32 is output.

The cylinder phase system is a rotational phase signal of the cylinder motor 1. The output of the frequency divider 8 is set so that the falling edge is the center of the slope section of the output of the cylinder phase system counter 11 (state at time _t2 ).
control.

The capstan phase system operates the capstan motor 2 so that the rising edge of the output of the control signal amplifier 30, which is the tape running phase signal, is at the center of the slope section of the output of the capstan phase system counter 32 (state at time _t3 ). Control.

Therefore, since the phase difference between the cylinder rotational phase signal and the tape running phase signal is controlled to be constant, tracking can be achieved.

The same thing happens in PAL mode, but
Since the period of the reference phase signal in PAL mode is 40 msec, the delay time of the delay circuit 16 is set to 20 msec, which is one half of the period. The reason why the delay time is set to one-half of one period of the reference phase signal of each mode is to widen the variable range of the delay time when tracking is performed.

However, in the above-mentioned NTSC/PAL compatible machine, the delay time of the delay circuit 16 is
The delay time varies between 16.7msec and 20msec depending on the PAL mode, so it is necessary to change the size of the capacitor and variable resistor that determine the delay time of the delay circuit 16, or adjust the resistance value of the variable resistor. This is undesirable because it increases the number of steps or parts in manufacturing the video tape recorder.

OBJECT OF THE INVENTION The object of the present invention is to provide a servo device in which the delay time of a delay circuit must be changed in order to perform tracking in modes in which the period of the reference phase signal is different. It is an object of the present invention to provide a servo device that makes it possible to set a phase difference to a desired value without changing the values of a capacitor or variable resistor that determines the delay time of a delay circuit.

Configuration of the Invention The servo device of the present invention includes a first phase error detection counter that measures a phase difference between a rotational phase signal of a first rotating body and a first reference phase signal, and a first phase error detection counter that measures a phase difference between a rotational phase signal of a first rotating body and a first reference phase signal. a first latch circuit that latches the count output of the first latch circuit, a first digital-to-analog converter that converts the output of the first latch circuit from digital to analog, and a repetition period of the rotational speed signal of the first rotating body. a first speed error detection counter that measures the speed error detection counter, a second latch circuit that latches the count output of the first speed error detection counter, and a second latch circuit that converts the output of the second latch circuit from digital to analog. a digital-to-analog converter; and the first and second digital-to-analog converters;
a first control means for synthesizing the outputs of the analog converters to generate an error output signal and controlling the rotational speed and rotational phase of the first rotating body to be constant; and a count output of the first phase error detection counter. a delay time correction circuit for creating a delay circuit trigger signal having a phase difference from the first reference position signal; a selection means for selecting a correction time of the delay time correction circuit; and an output signal of the delay time correction circuit. The second reference phase signal is the output of the delay circuit that starts its operation, and the second rotating body rotates in synchronization with the first rotating body.
a second phase error detection counter that measures the phase difference between the rotational phase signal of the rotating body and the second reference phase signal; and a third latch circuit that latches the count output of the second phase error detection counter. , a third digital-to-analog converter for digital-to-analog conversion of the output of the third latch circuit, and a second speed error detection counter for measuring the repetition period of the rotational speed signal of the second rotating body; a fourth latch circuit that latches the count output of the second speed error detection counter; a fourth digital-analog converter that converts the output of the fourth latch circuit from digital to analog; It is characterized by comprising a second control means for synthesizing the outputs of the fourth digital-to-analog converter to generate an error output signal and controlling the rotational speed and rotational phase of the second rotating body to be constant. It is something.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram of a servo system according to an embodiment of the present invention. In FIG. 3, blocks that are the same as those in FIG.

The system shown in FIG. 3 is different from the system shown in FIG. The output of the counter is input to the delay time correction circuit 40, and the output of the delay time correction circuit 40 is supplied to the delay circuit 16.
This is because the output of the NTSC/PAL switching circuit 39 is input.

In FIG. 3, the delay time correction circuit 40 includes a decoder that decodes the output of the cylinder phase system counter 11, and an output of the decoder that converts the output of the decoder into NTSC and PAL.
It consists of a circuit that switches between modes.

The operation of the servo device of this embodiment configured as described above will be explained below. First, NTSC
The case of mode will be explained. Figure 4 is NTSC
This is a time chart showing the tracking status in this mode. In Fig. 4, 1a to 1e are the second
Represents the same signal as in the figure. 1f represents the output of the delay time correction circuit 40. In this embodiment, the delay time of the delay circuit 16 is set to 16.7 msec in NTSC mode.

The first reference phase signal output from the decoder 14 at time _t1 causes the cylinder phase system counter 11 to
At the same time, the delay time correction circuit 40 outputs a signal that triggers the delay circuit 16, and the delay circuit 16 starts operating. Delay circuit 1
6 outputs a preset signal for the capstan phase system counter 32 at time _t2 when a set delay time (in this case, 16.7 msec in NTSC mode) has elapsed. Therefore, in the NTSC mode, although the signal that triggers the delay circuit 16 is changed from the output of the decoder 14 to the output of the delay time correction circuit 40, the output time is the same, and the delay time of the delay circuit 16 is also the same as that of the NTSC mode. Since the mode is 16.7 msec, the capstan phase system counter 32 is preset to the same time _t2 as the time chart in FIG. Then,
The phase relationship between the cylinder phase system and the capstan phase system is the same as in FIG.

Next, the case of PAL mode will be explained.
FIG. 5 is a time chart showing the state of tracking in PAL mode in this embodiment.

In FIG. 5, 2a represents the output of the cylinder phase system counter 11, 2b represents the output of the frequency divider 8, and 2c represents the output of the frequency divider 8.
2d is the output of the capstan phase system counter, 2e is the output of the control signal amplifier 30, and 2f is the delay time correction circuit 4.
Each represents an output of 0. Here, the delay time of the delay circuit 16 is set to 16.7 msec in NTSC mode. Therefore, the delay time of the delay circuit 16 is
From the standard delay time of 20.0msec in PAL mode
It has become shorter by 3.3msec.

The first reference phase signal output from the decoder 14 at time _t1 causes the cylinder phase system counter 11 to
is preset. The delay time correction circuit 40 is
From the output of the cylinder phase system counter 11, time t ₁
A signal that triggers the delay circuit 16 at time _t2 delayed by the time (3.3 msec) when the delay time of the delay circuit 16 is shortened is output. The delay circuit 16 outputs a preset signal for the capstan phase system counter 32 at time _t3 after the set delay time (16.7 msec) has elapsed. Therefore, the time interval from time t ₁ to time t ₃ is the sum of the correction time (3.3 msec) by the delay time correction circuit 40 and the delay time (16.7 msec) of the delay circuit 16, and the total delay time is the normal delay. The time will be the same as 20.0msec. Therefore, the time at which the preset signal of the capstan phase system counter is output differs depending on whether the capacitor or resistor of the delay circuit 16 is changed and the delay time is set to 20 msec, which is the delay time of the PAL mode, or when the delay time of the delay time correction circuit 40 is set. This is the same as adding a circuit and not adjusting the delay time of the delay circuit 16.

The cylinder phase system is configured such that the falling edge of the output of the frequency divider 8, which is the rotational phase signal of the cylinder motor 1, is the center of the slope section of the output of the cylinder phase system counter 11 (state at time _t3 ).
control.

The capstan phase system operates the capstan motor 2 so that the rising edge of the output of the control signal amplifier 30, which is the tape running phase signal, is at the center of the slope section of the output of the capstan phase system counter 32 (state at time _t4 ). Control.

Therefore, in this embodiment, as in the conventional example, the phase difference between the cylinder rotational phase signal and the tape running phase signal is controlled to be constant, and tracking can be achieved.

As described above, according to this embodiment, by providing the delay time correction circuit 40 that corrects the delay time, the first standard in both NTSC/PAL modes can be achieved without changing the delay time of the delay circuit 16. The phase difference between the phase signal and the second reference phase signal can be set to one half of the period of each reference phase signal.

Therefore, even if the mode changes, there is no need to change the value of the capacitor or variable resistor that changes the delay time of the delay circuit 16. This reduces the number of adjustment points in manufacturing and also reduces the number of parts.

Addition of the delay time correction circuit 40 increases the circuit scale, but normally the delay time correction circuit 40 is connected to other circuits (here, each counter for four channels of cylinder phase system/speed system, capstan phase system/speed system, (a circuit consisting of each latch, each DA converter, each ROM, etc.), and when integrating other circuits, the chip area will be reduced by adding the delay time correction circuit 40. The increase is hardly a problem. Adjusting the delay time or increasing the number of parts is more undesirable than a slight increase in chip area because it increases costs.

Effects of the Invention As is clear from the above description, the present invention provides a phase error detection counter (described in the embodiments described above) that measures the phase difference between the rotational phase signal of a rotating body such as a cylinder motor and the first reference phase signal. (corresponding to the cylinder phase system counter 11 in the above) and a first phase error detection counter that latches the count output of the first phase error detection counter.
latch circuit (latch 15 in the previous embodiment)
), a first digital-to-analog converter (corresponding to the D-A converter 17 in the above-described embodiment) that converts the output of the first latch circuit from digital to analog; A first speed error detection counter (corresponding to the cylinder speed system counter 12 in the above embodiment) that measures the repetition period of the rotational speed signal, and a second latch that latches the count output of the first speed error detection counter. circuit (latch 1 in the previous embodiment)
8) and a second digital latch circuit for digital-to-analog conversion of the output of the second latch circuit.
The outputs of an analog converter (corresponding to the D-A converter 20 in the above-described embodiment) and the first and second digital-to-analog converters are synthesized to create an error output signal, and (latch 15, 18, D in the above-mentioned embodiment)
- Corresponds to a control system including A converters 17, 20, synthesis circuit 21, and cylinder motor drive circuit 22)
and a delay time correction circuit (delay time correction circuit 40 in the above-described embodiment) that creates a delay circuit trigger signal having a phase difference with the first reference phase signal from the count output of the first phase error detection counter.
) and selection means for selecting the correction time of the delay time correction circuit (equivalent to
(corresponding to an NTSC/PAL switching circuit) and the output of a delay circuit that starts its operation based on the output signal of the delay time correction circuit as a second reference phase signal, and a second rotating body that rotates in synchronization with the first rotating body. a second phase error detection counter (corresponding to the capstan phase in the above embodiment) that measures the phase difference between the rotational phase signal of the rotating body (corresponding to the capstan motor 23 in the above embodiment) and the second reference phase signal; system counter 32) and a third latch circuit that latches the count output of the second phase error detection counter (corresponding to the latch 31 in the above-described embodiment).
and the output of the third latch circuit is digitally output.
A third digital-to-analog converter that performs analog conversion (DA converter 3 in the above embodiment)
3), a second speed error detection counter (corresponding to the cylinder speed system counter 28 in the aforementioned embodiment) that measures the repetition period of the rotational speed signal of the second rotating body, and a second speed error detection counter (corresponding to the cylinder speed system counter 28 in the above-described embodiment) A fourth latch circuit (corresponding to the latch 27 in the above embodiment) that latches the count output of the error detection counter, and a fourth digital-to-analog converter (corresponding to the latch 27 in the above-mentioned embodiment) that performs digital-to-analog conversion of the output of the fourth latch circuit. (corresponding to the D-A converter 36 in the above-described embodiment) and the outputs of the third and fourth digital-to-analog converters are synthesized to create an error output signal, and the rotational speed of the second rotating body and A second control means (corresponding to the control system including the latches 31 and 27, the D-A converters 33 and 36, the synthesis circuit 37, and the capstan motor drive circuit 37 in the above-mentioned embodiment) controls the rotational phase to be constant. Since the period of the reference phase signal changes, the first reference phase signal and the second reference phase signal can be changed without changing the capacitor or variable resistor of the delay circuit or adjusting the value of the variable resistor. An excellent effect can be obtained in that the phase difference between the phase signals can be set to a desired value (in the above-described embodiment, the period is one-half of the reference phase signal).

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional servo device, FIG. 2 is a time chart for explaining the operation of the block diagram in FIG. 1, and FIG. 3 is a block diagram of a servo device according to an embodiment of the present invention. 4 and 5 are time charts for explaining the operation of the block diagram in FIG. 3. 11...Cylinder phase system counter, 14...Decoder, 16...Delay circuit, 40...Delay time correction circuit.

Claims (1)

[Claims] 1. A first phase error detection counter that measures the phase difference between the rotational phase signal of the first rotating body and the first reference phase signal, and a first phase error detection counter that latches the count output of the first phase error detection counter. latch circuit,
a first digital-to-analog converter for digital-to-analog conversion of the output of the first latch circuit; a first speed error detection counter for measuring a repetition period of a rotational speed signal of the first rotating body;
a second latch circuit that latches the count output of the first speed error detection counter; a second digital-to-analog converter that converts the output of the second latch circuit from digital to analog;
and the output of the second digital-to-analog converter to generate an error output signal, and control the rotational speed and rotational phase of the first rotating body to be constant; a delay time correction circuit for creating a delay circuit trigger signal having a phase difference from the first reference phase signal from the count output of a phase error detection counter; a selection means for selecting a correction time of the delay time correction circuit; The output of the delay circuit that starts its operation in response to the output signal of the delay time correction circuit is used as a second reference phase signal, and the rotational phase signal of a second rotating body rotating in synchronization with the first rotating body and the second a second phase error detection counter that measures the phase difference between reference phase signals; a third latch circuit that latches the count output of the second phase error detection counter; and a digital output of the third latch circuit. - a third digital-to-analog converter that performs analog conversion; a second speed error detection counter that measures the repetition period of the rotational speed signal of the second rotating body; and a count output of the second speed error detection counter. a fourth latch circuit that latches the output of the fourth latch circuit, a fourth digital-to-analog converter that converts the output of the fourth latch circuit from digital to analog, and the outputs of the third and fourth digital-to-analog converters. A servo device comprising second control means that synthesizes an error output signal and controls the rotational speed and rotational phase of the second rotating body to be constant.