JPH0351273B2 - - Google Patents

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a dimming control device for lighting such as a stage, and more specifically, channels corresponding to a plurality of lighting loads are grouped, and dimming is controlled for each grouped unit. The present invention relates to a dimming control device that performs control.

Prior Art In conventional dimming control devices, a plurality of channels are grouped and dimming control is performed for each grouped unit. However, this grouping is merely a matter of dividing and grouping the entire channel, and a channel does not belong to multiple groups at the same time.
That is, referring to FIG. 7, channels CH1,
CH2,... belong to group Gg1, and channel CH
3, 4,... belong to group Gg2 and are channel CH
5,... belong to group Gg3. The remaining groups Gg4, Gg5, Gg6, . . . include the remaining channels without duplication. these groups
Gg1, Gg2, Gg4, ... belong to group GG1,
Also, groups Gg3, Gg5, Gg6,... are groups
It belongs to GG2. Groups GG3, . . . include remaining groups Gg7, . Reference mark M includes all these groups GG1, GG2, . . . . As is clear from this figure 7, channels CH1, CH2,... are small groups Gg
1, Gg2, ... and the large group GG that includes it
Although they may belong to 1, GG2, etc. at the same time, there was no overlap between groups of the same rank.

FIG. 8 is a specific electrical circuit diagram of a group fader and the like in such a conventional dimming control device. In this Fig. 8, the reference mark MF indicates the master fader, GF1 and GF2 indicate the group fades of the large group, and gF1, gF2, gF
3 indicates a group fade of a small group, PF
1, PF2, PF3, . . . indicate preset faders for setting channels. Also reference mark D1,
D2, D3, D4, D5, and D6 indicate current amplifiers. The current given to fader PF1 changes by the operation of fader gF1, and the current applied to fader gF1 changes.
1 operates as a group fader for feeders PF1 and PF2. When operating Fader GF1,
The current applied to faders gF1 and gF2 changes. As a result, feeders PF1, PF2, PF3,
The current applied to PF4 also changes. If you operate the master fader MF, it will similarly affect the lower faders and change the setting levels of all channels. In the case of this type of group fade method, when creating a lighting effect, depending on the progress of the scene, you can perform arbitrary operations such as darkening a certain part of the scene as a whole, and darkening a different part of the scene at other times. I couldn't do that part.

That is, in lighting production for a stage or the like, there are times when it is desired to simultaneously control the dimming levels of the lighting loads at the front and center of the stage, and the dimming levels of the lighting loads at the rear and center, respectively.
At this time, conventionally, the center cannot be included in the group including the front part and the group including the rear part in an overlapping manner. Therefore, the front, center, and rear lighting loads must each be dimmed and controlled individually. Therefore, there are restrictions on the operation of the lighting effects, and the effects of the lighting effects cannot be fully exhibited.

Purpose An object of the present invention is to provide dimming control that can control the lighting load of a common channel included in a plurality of groups for each group, and improve the effect of lighting effects. The purpose is to provide equipment.

Configuration The present invention provides a dimming control device in which each channel CH includes one or more lighting loads 4 and which performs dimming control of the lighting loads 4 included in that channel CH for each channel CH. A level memory 12 in which an initial level aj is stored, and one or more groups to which each channel CHj belongs, each channel CHj and m groups G
The correspondence relationship bij with the i-th group Gi among 1 to Gm is stored with the value expressed as "1" when each channel CHj belongs to each group Gi, and the value expressed as "0" when it does not belong. Compatible memory 13
and a group fader gF1 that is provided for each group G1 to Gm and derives a signal representing levels g1 to gm for performing a group fade that simultaneously changes the dimming levels of channels CHj belonging to each group G1 to Gm. ~gFm,11, the stored contents of the level memory 12 and the corresponding memory 13, and the output of the group fader gFi,11, the dimming level Zj for each channel CHj, Zj=aj _n 〓 ⁱ⁼¹ ( gi) ^bij ...(2) and derives the result.
3; and means 5 for controlling the dimming so that the dimming level of the lighting load 4 for each channel CHj becomes Zj in response to the outputs Zj of the calculation means 10 and 23. It is a device.

Embodiment FIG. 1 is a block diagram of an embodiment of a dimming device using a dimming calculation device according to the present invention. The light control device 1 includes an input section 2 for inputting light control data;
Each channel CH1, CH2,... is controlled by the dimming calculation device 3 and the dimming control signal from the dimming calculation device 3.
A lighting control unit 5 that controls the lighting loads 4 (indicated collectively by the reference symbol CH). The input unit 2 has group faders gF1, gF2, . . . as dimming level setting means for grouping each channel into overlapping combinations and individually setting a dimming level for each grouped unit. (generally indicated by the reference symbol gF), and a setting means 6 for setting control data bij regarding whether the j-th channel CHj belongs to the i-th group Ggi. The dimming calculation device 3 includes a control unit 10 that performs predetermined calculation processing, and a group fader gF.
a first memory 11 that stores the dimming level of each channel, and a second memory 12 that stores the initial level of each channel and the calculation results of the calculation processing from the control unit 10.
and a third memory 13 in which the control data bij from the setting means 6 is stored.

In the present invention, each channel CH is grouped into a plurality of groups, and this group mode is divided so that each channel CH is selectively included in group Gg, and the dimming level is controlled for each grouped unit. Ru. An example of this group aspect is shown in FIG. For example, channel CH3 belongs to group Gg1 and group Gg5, and channel CH3 belongs to group Gg1 and group Gg5.
7 belongs to groups Gg2, Gg3, Gg4, and Gg5. The present invention allows group federation to be performed without any inconvenience by performing the calculation shown in the first equation in such overlapping groups.

Zj=aj _n 〓 ⁱ⁼¹ (gi) ^bij ...(3) aj indicates the initial level of each channel, gi indicates the level of each group fader, and bij indicates whether channel j belongs to group i or not. It shows that. Further, Zj indicates the j-th channel output level.

Calculate the output level Zj based on this first equation,
Light control is performed according to this Zj. For example, the second
In the illustrated group mode, the output level Z3 of channel CH3 is expressed by the second equation.

Z3=a3(g1) ¹ (g2) ⁰ (g3) ⁰ (g4) ⁰ (g5) ¹ =a3g1g5
...(4) Here, a3 is the initial level of channel CH,
g1 is the level of group fader gF1, g5
is the level of group fader gF5, therefore channel CH3 can perform dimming operation at both g1 and g5.

FIG. 3 is a flowchart showing the procedure of arithmetic control by the arithmetic and control device 3. In this embodiment, it is assumed that the number of channels CH is n and the number of group faders Gg is m. First channel
Calculations are performed for the first, second, . . . m-th group faders Gg for CH. That is, in step n1, control data b11 is read from the third memory 13, and in step n2, b11 is set to "1".
It is determined whether or not. When it is "1",
That is, when the first channel belongs to the first group _Gg1 , the initial level a1 of the first channel is read from the second memory 12 in step n3, and the first level a1 is read from the first memory 11 in step n4. Read the level g1 of the th group fader gF1, and at step n5 a1×g1
Performs the multiplication of In step n6, the result of this multiplication is written into the second memory 12 as a new level a1 of the first channel CH1.

In the step n2, the data b11 is 0.
If so, return to step n1 again.

Next, return to step n1 from step n6, and
The operations from step n1 to step n6 are performed for the second group Gg2 per channel. This operation is repeated m times. Then the second
Move to the channel CH2 and perform the same operation as the channel CH2.
By repeating the same operation twice, the arithmetic processing is completed for all channels. The desired output level of each channel will be stored in the second memory 12.

For example, if the third channel CH3 belongs to the first group Gg1 and the fifth group Gg5, the second
The value "a ₃ ×g ₁ " is stored in the memory 12 as the level of the third channel. Next, the value "a ₃ ×g ₁ " is read out from the second memory 12 as the initial level by calculation regarding the fifth group, and the group fader level g5 of the fifth group Gg5 is set to this value.
is multiplied, so the value "A3 x g1 x g5" is stored in the second memory 12 as the output level of channel 3.

FIG. 4 is a block diagram showing the configuration of a dimming calculation device 3a of another embodiment. This embodiment is similar to the previous embodiment and corresponding parts are provided with the same reference numerals. What should be noted is that in this embodiment, the control section 6 is configured as a counter 20. Oscillator 21 outputs a clock square wave. Further, in this embodiment, the counter 20 may be constituted by a 15-bit binary counter, and a clock signal is input to the input terminal CLK. The output terminal Q1 is the oscillator 21
Derive the 1/2 frequency division output of the clock rectangular wave CP output from . Similarly, the output terminal Q2 derives a 1/2 ² frequency divided output, the output terminal Q3 derives a 1/2 ³ frequency divided output, . . . , the output terminal Q15 derives a 1/2 ¹⁵ frequency divided output, respectively.
In this example, the number of groups is 32 and the number of channels is 32.
256. The output of the output terminal Q1 of the counter 20 is used as the write signal WR of the second memory 12. Further, the channel selection signal J is derived by the output terminals Q2 to Q9, and the lower addresses A0 to A7 of the third memory 13 and the address A of the second memory 12 are output.
Given as 0 to A7. Also, output terminal Q10
Deriving the group selection signal I by ~Q15,
Addresses A0 to A5 of the first memory 11 and the third
It is given as upper addresses A8 to A13 of the memory 13. The output from the output terminal Q1 of the counter 20 is one input terminal 22a of the AND gate 22.
and the output from the third memory 13 is AND
It is applied to the other input terminal 22b of the gate 22. The output of the AND gate 22 is
write is applied to the control terminal.

Address “i” of the second memory 12 stores the dimming level to be output from the i-th channel CHi. Further, at address "i" of the first memory 11, the illumination level gi of the i-th group fader is stored. Also, the third memory 13
Control data bij indicating whether the j-th channel belongs to the i-th group is stored at the address "i×2 ⁸ +j".

FIG. 5 is a timing chart explaining the operation of the dimming calculation device 3a shown in FIG. The operation of the dimming calculation device 3a will be described with reference to FIGS. 4 and 5. The output of output terminal Q1 is at time t
In the state before 1, it is at a low level, and the output levels of the output terminals Q2 to Q15 are all at a low level. Therefore, from the first memory 11, the dimming level g1 of the first group fader gF1 from the address "1" corresponding to such an address signal is given to the multiplication circuit 23, and the second memory 12
1st channel from similar address "1"
The level a1 of CH1 is output to the multiplication circuit 23,
Further, control data b11 indicating whether or not channel CH1 belongs to group Gg1 from address "1, 1" in third memory 13 is applied to the other input terminal 22b of AND gate 22. On the other hand, in the multiplication circuit 23, g1 and a1 are multiplied.

The output of this output terminal Q1 (hereinafter, this output will be explained with the same reference numeral as the output terminal Q1) Q
At time t1 when 1 rises, one input terminal 22a of the AND gate 22 becomes high level. At this time, only when the output from the third memory 13 is at a high level, the output from the AND gate 22 becomes a high level, and the calculated value from the multiplication circuit 23 is stored at address "1" of the second memory 12.

Next, at time t2 when the output of the terminal Q2 shown in FIG.
2 outputs the illumination level a2 of the second channel CH2, and the first memory 11 outputs the level g1 of the first group fader gF1. Further, the third memory 13 transfers the control data b12 of address "1" to the other input terminal 22 of the AND gate 22.
Output to b. When this data b12 is 0, no write signal is given to the second memory 12 at the next rise time t3 of the output terminal Q1, and the second
The contents stored at address "2" in the memory 12 remain in the previous state. That is, the write signal W is
Although a pulse is output each time the combination of the channel selection signal J and the group selection signal I changes, since the other input terminal 22b of the AND gate 22 is the output of the third memory 13,
bij is "1", that is, channel CHj is a group
Only when it belongs to Ggj, the output of the AND gate 22 becomes high level, and only then a pulse is given to the second memory 12 as the write control signal W.

When such processing is repeated and the counter 20 has fully counted all the combinations of the channel selection signal J and the group selection signal I,
The output levels of all channels will be stored in the second memory 12. Incidentally, based on the output of this second memory 12, dimming control of the lighting load is performed.

In the above embodiment, the group fader level g
Although a memory is used as a means for deriving , the structure shown in FIG. 6 may also be used. That is, the levels of the group faders gF1, gF2, . . . , gFi are given to the multiplexer 30. The multiplexer 30 is provided with a fader selection signal via line 31, thereby causing the fader
One level among gF1 to gFi is selectively applied to the analog/digital converter 32, and the data is output as a digital value to the multiplication circuit 23.

Effects As described above, according to the present invention, the dimming level of the lighting load 4 of the common channel CH included in a plurality of groups G can be controlled for each group G. This makes it possible to perform dimming control by combining desired channels CH, depending on the lighting needs of a stage or the like, for example. Therefore, detailed lighting effects can be achieved and the lighting effect can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
3 is a flow chart for explaining the operation of the embodiment shown in FIG. 4, and FIG. 4 is a block diagram of a dimming calculation device 3a of another embodiment. , FIG. 5 is a timing chart for explaining the control operation of the dimming calculation device 3a, FIG. 6 is a block diagram of another embodiment of group fade level deriving means, and FIG. 7 is a diagram of a conventional group fade level deriving means. FIG. 8, which is a diagram showing a group mode of channels in the fade method, is a specific electrical circuit diagram of the level setting means in the conventional group fade method. 1... Light control device, 2... Input section, 3, 3a...
Dimming calculation device, 4... Lighting load, 5... Lighting control unit, 11... First memory, 12... Second memory,
13...Third memory, 20...Counter, 21...
...oscillator, 22...AND gate, 23...multiplication circuit.

Claims (1)

[Claims] 1. Each channel CH has one or more lighting loads 4
In the dimming control device which performs dimming control of the lighting load 4 included in each channel CH for each channel CH, a level memory 12 in which an initial level aj is stored for each channel CHj, and a level memory 12 where each channel CHj stores an initial level aj; For one or more groups to which it belongs, each channel CHj and m groups G
The correspondence relationship bij with the i-th group Gi among 1 to Gm is stored with the value expressed as "1" when each channel CHj belongs to each group Gi, and the value expressed as "0" when it does not belong. Compatible memory 13
and a group fader gF1 that is provided for each group G1 to Gm and derives a signal representing levels g1 to gm for performing a group fade that simultaneously changes the dimming levels of channels CHj belonging to each group G1 to Gm. ~gFm,11, the stored contents of the level memory 12 and the corresponding memory 13, and the output of the group fader gFi,11, the dimming level Zj for each channel CHj, Zj=aj _n 〓 ⁱ⁼¹ ( gi) ^bij ...(1) and derives the result.
3; and means 5 for controlling the dimming so that the dimming level of the lighting load 4 for each channel CHj becomes Zj in response to the outputs Zj of the calculation means 10 and 23. Device.