JPH0351388U

JPH0351388U -

Info

Publication number: JPH0351388U
Application number: JP11319789U
Authority: JP
Priority date: 1989-09-27
Filing date: 1989-09-27
Publication date: 1991-05-20

Description

[Brief explanation of drawings]

第１図はこの考案の一実施例を示す構成図、第
２図はこの考案の具体例を示す構成図、第３図は
位相量変換器の詳細な構成図、第４図はこの考案
の別の具体例を示す構成図、第５図は位相量検出
器の詳細な構成図、第６図はこの考案のさらに別
の具体例を示す構成図、第７図は従来のレーダ信
号処理装置の構成図である。図において、１ａ，１ｂ，１ｃ，１ｄ……１Ｒ
ＰＩの遅延メモリ、２ａ，２ｂ，２ｃ，２ｄ……
乗算器、３ａ，３ｂ，３ｃ，３ｄ……加算器、４
ａ，４ｂ，４ｃ，４ｄ，４ｅ，４ｆ，４ｇ，４ｈ
，４ｉ，４ｊ，４ｋ，４ｌ……コヒーレント積分
器、５ａ，５ｂ……追尾プロセツサ、６……位相
量変換器、１１……位相量検出器、１２……セレ
クタ、１６ａ，１６ｂ，１６ｃ……乗算器、１７
……入力バツフアメモリ、１８……バタフライ演
算器、１９……演算メモリ、２２ａ，２２ｂ，２
２ｃ……ウエイテイング関数メモリーである。な
お、図中同一符号は同一または相当部分を示す。 Fig. 1 is a block diagram showing an embodiment of this invention, Fig. 2 is a block diagram showing a specific example of this invention, Fig. 3 is a detailed block diagram of a phase amount converter, and Fig. 4 is a block diagram of this invention. A block diagram showing another specific example, FIG. 5 is a detailed block diagram of a phase amount detector, FIG. 6 is a block diagram showing yet another specific example of this invention, and FIG. 7 is a conventional radar signal processing device. FIG. In the figure, 1a, 1b, 1c, 1d...1R
PI delay memory, 2a, 2b, 2c, 2d...
Multiplier, 3a, 3b, 3c, 3d... Adder, 4
a, 4b, 4c, 4d, 4e, 4f, 4g, 4h
, 4i, 4j, 4k, 4l... Coherent integrator, 5a, 5b... Tracking processor, 6... Phase amount converter, 11... Phase amount detector, 12... Selector, 16a, 16b, 16c... multiplier, 17
...Input buffer memory, 18... Butterfly computing unit, 19... Arithmetic memory, 22a, 22b, 2
2c... Weighting function memory. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims

[Claims for Utility Model Registration] (1) Input a received signal of 1PRI (pulse repetition period) that has been A/D converted after phase detection, and
A memory that outputs data with a delay of I, a multiplier that performs phase correction by multiplying the output data of this memory by a phase amount corresponding to the target Doppler frequency, and coherent integration by adding the received signal to the output of this multiplier. A coherent integrator consisting of an adder that outputs an integral result, a coherent integrator consisting of the above memory, a multiplier, and an adder, and one or more coherent integrators connected in series to the coherent integrator. Radar signal processing equipment. (2) As a means of calculating the phase amount corresponding to the target Doppler frequency from the target speed, there is a tracking processor that inputs target information, predicts the target speed, and outputs it, and this predicted speed corresponds to the target Doppler frequency. Utility model registration claim No. (1)
) The radar signal processing device described in item 2. (3) As a means for determining the phase amount corresponding to the target Doppler frequency from the target position, there is a tracking processor that inputs target information, predicts and outputs the target position, and receives signals from multiple PRIs at this predicted position. Utility model registration claim No.
) The radar signal processing device described in item 2. (4) As a means of weighting the phase amount corresponding to the target Doppler frequency and suppressing side lobes during coherent integration, a weighting function memory storing a weighting function and a phase amount corresponding to the target Doppler frequency are used. 2. A radar signal processing device according to claim 1, which is a utility model, and further comprises a multiplier that multiplies weighting function memory outputs.