JPH0445983U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram showing one embodiment of the present invention;
The figure is a block diagram showing another embodiment of the present invention, Fig. 3 is a detailed block diagram of a phase quantity converter, Fig. 4 is a block diagram showing still another embodiment of the present invention, and Fig. 5 is a phase shifter. A detailed configuration diagram of the amount detector, FIG. 6 is a configuration diagram showing still another embodiment of the present invention, FIG. 7 is a configuration diagram of a conventional pulse Doppler filter, and FIG. 8 is a conventional moving target indicating device. Fig. 9 is a block diagram of a conventional radar signal processing device, and in the figure, 1a, 1
b, 1c, 1d are delay memories of 1PRI, 2a,
2b, 2c, 2d are multipliers, 3a, 3b, 3c,
3d is an adder, 4a, 4b, 4c, 4d are selectors, 5a, 5b, 5c, 5d, 5e, 5f, 5g,
5h, 5i, 5j, 5k, 5l are coherent integrators, 6a, 6b are tracking processors, 7 is a phase amount converter, 12 is a phase amount detector, 13 is a selector,
18a, 18b, 18c are multipliers, 27a, 27
b, 27c are weighting function memories, 19
The input buffer memory 20 is a butterfly arithmetic unit,
21 is an arithmetic memory, 24a, 24b, 24c are digital filters, 25 is an MTI, and 26 is a pulse Doppler filter. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims for Utility Model Registration] (1) Input a received signal of 1PRI (pulse repetition period) that has been A/D converted after phase detection, and
A memory for outputting with a delay of I, a means for supplying a phase amount corresponding to the target Doppler frequency or "-1" as a phase correction coefficient, and a multiplication for performing phase correction by multiplying the output data of the memory by the phase correction coefficient. an adder that performs coherent integration by adding a received signal to the multiplier output and outputs the integration result; a selector that selects and outputs data from either the adder output or the multiplier output; A radar signal processing device comprising a coherent integrator constituted by the above memory, multiplier, adder, and selector, and one or more coherent integrators connected in series to the coherent integrator. (2) As means for supplying the phase correction coefficient,
A utility model characterized in that it is equipped with a tracking processor that inputs target information, predicts and outputs the speed of the target, and a phase amount converter that converts this predicted speed into a phase amount corresponding to the Doppler frequency of the target. A radar signal processing device according to registered claim (1). (3) As means for supplying the phase correction coefficient,
A tracking processor that inputs target information, predicts and outputs the target position, and a plurality of PRIs for this predicted position.
A radar according to claim (1) of claim 1, characterized in that the radar is equipped with a phase amount detector that detects a phase amount corresponding to a target Doppler frequency by processing a received signal of Signal processing device. (4) A weighting function memory that stores a weighting function and a weighting function memory that outputs a phase amount corresponding to the target Doppler frequency as a means for weighting the phase correction coefficient and suppressing sidelobes during coherent integration. The radar signal processing device according to claim 1, further comprising a multiplier for multiplying the .