JPH0351519U - - Google Patents
Info
- Publication number
- JPH0351519U JPH0351519U JP11079389U JP11079389U JPH0351519U JP H0351519 U JPH0351519 U JP H0351519U JP 11079389 U JP11079389 U JP 11079389U JP 11079389 U JP11079389 U JP 11079389U JP H0351519 U JPH0351519 U JP H0351519U
- Authority
- JP
- Japan
- Prior art keywords
- diagram showing
- variable attenuator
- frequency variable
- pin
- pin diodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Attenuators (AREA)
Description
第1図aは本考案に係る減衰器の第1の実施例
を示す回路図であり、同図bはその減衰特性図で
ある。第2図aは従来の減衰器の第1の例を示す
回路図であり、同図bはその減衰特性図である。
第3図aは従来の減衰器の第2の例を示す回路図
であり、同図bはその減衰特性図である。第4図
aは従来の減衰器の第3の例を示す回路図であり
、同図bはその減衰特性図である。第5図aはP
INダイオードの構成図であり、同図bはその等
価回路図である。第6図は本考案に係る減衰器と
従来の減衰器の、その減衰度が最小の時と最大の
時の等価回路と減衰特性を示す説明図である。第
7図は本考案の第2の実施例を示す回路図である
。第8図aは従来のRFスイツチ回路であり、同
図bはそれに本考案を適用した場合の回路図であ
る。第9図はPINダイオード3個を用いた本考
案の実施例を示す回路図であり、第10図はRF
スイツチ回路に本考案を適用した第2の例を示す
回路図である。
FIG. 1a is a circuit diagram showing a first embodiment of an attenuator according to the present invention, and FIG. 1b is a diagram showing its attenuation characteristics. FIG. 2a is a circuit diagram showing a first example of a conventional attenuator, and FIG. 2b is a diagram showing its attenuation characteristics.
FIG. 3a is a circuit diagram showing a second example of a conventional attenuator, and FIG. 3b is a diagram showing its attenuation characteristics. FIG. 4a is a circuit diagram showing a third example of a conventional attenuator, and FIG. 4b is a diagram showing its attenuation characteristics. Figure 5 a is P
It is a block diagram of an IN diode, and the same figure b is the equivalent circuit diagram. FIG. 6 is an explanatory diagram showing equivalent circuits and attenuation characteristics of the attenuator according to the present invention and the conventional attenuator when the attenuation degree is minimum and maximum. FIG. 7 is a circuit diagram showing a second embodiment of the present invention. FIG. 8a shows a conventional RF switch circuit, and FIG. 8b shows a circuit diagram to which the present invention is applied. Fig. 9 is a circuit diagram showing an embodiment of the present invention using three PIN diodes, and Fig. 10 is a circuit diagram showing an embodiment of the invention using three PIN diodes.
FIG. 7 is a circuit diagram showing a second example in which the present invention is applied to a switch circuit.
Claims (1)
波可変減衰器において、 該PINダイオードを複数の直列接続PINダ
イオードに分割し、隣接PINダイオード間の接
続点を、コンデンサを介して接地したことを特徴
とする高周波可変減衰器。[Claim for Utility Model Registration] In a high-frequency variable attenuator that uses a PIN diode as a variable resistor, the PIN diode is divided into a plurality of series-connected PIN diodes, and the connection point between adjacent PIN diodes is grounded via a capacitor. A high frequency variable attenuator characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11079389U JPH0351519U (en) | 1989-09-21 | 1989-09-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11079389U JPH0351519U (en) | 1989-09-21 | 1989-09-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0351519U true JPH0351519U (en) | 1991-05-20 |
Family
ID=31659310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11079389U Pending JPH0351519U (en) | 1989-09-21 | 1989-09-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0351519U (en) |
-
1989
- 1989-09-21 JP JP11079389U patent/JPH0351519U/ja active Pending
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