JPH035171B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a device that generates a heartbeat sound synchronized with the heartbeat cycle and then changes the generation cycle of the heartbeat sound over time, and further relates to a device that changes the generation cycle of the heartbeat sound as time passes. The rate of change in the generation cycle can be set according to preference.

(Prior Art) Conventionally, as described in Japanese Patent Application Laid-Open No. 54-98651, a pulse wave, that is, a heartbeat is detected by a pulse wave detection device, and a heartbeat sound corresponding to this detection signal is generated. Measuring devices are known.

By the way, the heart rate under normal conditions is 70-80 beats per minute.
It is known that this number decreases to about 50 to 60 times per minute during sleep or in a relaxed state of mind, and increases to about 90 to 100 times per minute when excited or mentally tense. It is said that it is possible to control one's own heartbeat and mental state by concentrating on a certain sound.

(Problems to be Solved by the Invention) The present invention is a further development of the conventional heart rate measuring device described above, and its purpose is to provide a device that can easily control the mental state of the user. It is in.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention generates a heartbeat sound synchronized with the heartbeat cycle, and then adjusts the generation cycle of the heartbeat sound to the user's control over time. It is characterized by changing according to a set rate of change.

(Embodiments) Preferred embodiments of the present invention will be described below based on the drawings. FIG. 1 shows an embodiment in which a heartbeat sound generating device according to the present invention is combined with a watch with an alarm function.

The oscillation circuit 2, the frequency dividing circuit 4, the waveform shaping circuit 6, the motor 8, the wheel train 10, and the pointer display 12 constitute a conventionally well-known analog timepiece. The reference mechanism 14 is built into the wheel train 10, and supplies the AND gate 16 with an alarm start signal that remains "H" for about 20 minutes when the set time arrives. The AND gate 16 is also supplied with the output of a ring stop switch 18, and when an alarm start signal is generated when the switch 18 is closed, a heartbeat signal is supplied to the sound generation circuit 19 from a heartbeat signal generation circuit 70, which will be described later.
The sound generation circuit 19 is a circuit that converts a heartbeat signal into a heartbeat sound.

The heartbeat detection unit 20 is a device that detects a heartbeat and outputs a detection signal corresponding to the heartbeat to an output a as shown in FIG. When external light is applied to the fingertips, the amount of reflected light is modulated by blood flow.
The transmitted light is detected by a phototransistor. The output a of the heartbeat detection section 20 is supplied to a waveform shaping circuit 22, and the supplied detection signal is shaped into a square wave with a constant pulse width and outputted as an output b.

The heart rate storage circuit 24 is a circuit that counts the detection signal from the heartbeat detection section 20 for a certain period of time, one minute in this case, and stores the count value. The detection signal via the waveform shaping circuit 22 is supplied to a counter 28 via an AND gate 26, and when the AND gate 26 is open, the detection signal, that is, the heart rate is counted by the counter 28. The output G of a flip-flop (hereinafter referred to as FF) 30 is supplied to the other input terminal of the AND gate 26, and when the output G is "H", the AND gate 26 is in an open state. Note that the output G is also supplied to the heartbeat detection section 20, and the detection operation of the heartbeat detection section 20 is enabled only when the output G is "H". Further, the output H of the FF 30 is supplied to the reset terminal R of the counter 28. The set terminal S of the FF 30 is supplied with an output D of an OR gate 54 in an operation control circuit 48, which will be described later, and the reset terminal R is supplied with a timer circuit 5.
6 is supplied via a delay circuit 32. Further, the latch circuit 34 is supplied with the count value of the counter 28, and stores the count value when a single pulse is outputted to the output E of the timer circuit 56.

The variable oscillation circuit 36 is a circuit whose oscillation frequency is varied by an external operating member, and includes a CR oscillator 37,
It is comprised of a variable resistor 38 which also serves as an external operating member, and a frequency dividing circuit 39 for the oscillation output of the CR oscillator 37. As output signals, a clock signal _φ1 varying between 3/4 and 1/4 Hz and a clock signal _φ2 varying between 3/60 and 1/60 Hz are output.

The count circuit 40 is a circuit that counts the output signal of the variable oscillation circuit 36 after the heart rate storage circuit 24 has finished counting. The counter 41 counts the clock signal supplied from the AND gate 42.
46 outputs are provided. Switching gate 44
are supplied with clock signals φ ₁ and φ ₂ from a frequency dividing circuit 39 in the variable oscillation circuit 36, and output B is supplied to the switching control terminal. Then, if the output B is "H", the clock signal φ ₁ is selectively output, and if the output B is "L", the clock signal φ ₂ is selectively output.

The operation control circuit 48 is a circuit that outputs a control signal for controlling the operations of the heart rate storage circuit 24 and the counting circuit 40. One shot circuit 5
The single pulses generated from 0 and 52 are both supplied to the OR gate 54, and the single pulse generated at the output D of the OR gate 54 is applied to the set terminal S of the FF 30 as a control signal for starting heart rate counting as described above. Supplied. Further, the single pulse generated at the output D starts the operation of the timer circuit 56, and after one minute has elapsed, a single pulse is generated at the output E again. This single pulse generated at the output E is used to store the count value of the counter 28 in the latch circuit 34 as described above, to terminate the counting of the heart rate, and to start the counting operation in the counting circuit 40. The preset end of the latch circuit 34, the delay circuit 32 and the FF 46 are used as control signals.
is supplied to the set terminal S of. The output A is output to the one shot circuit 50, and the output A is output to the one shot circuit 52.
are respectively supplied with an output B.

Further, the output A is inverted and supplied to the OR gate 58, and the output C of the OR gate 58 is supplied to the reset terminal R of the counter 41 as a control signal for resetting the counter 41. The output L of a timer circuit 60, which will be described later, is also supplied to this OR gate 58.

Further, the comparison circuit 62 is a circuit that compares an output signal from an arithmetic circuit 68, which will be described later, and a code signal from the encoder 64. When the output B is "H", the value of the code signal from the encoder 64 is used to A single pulse is generated at output K when the value of the output signal from B becomes large, and conversely, when the output B becomes small, a single pulse is generated at output K. In this embodiment, the encoder 64
The code signal is "80" if output B is "H",
It is set to be "50" if output B is "L". The single pulse generated at the output K is supplied to the reset terminal R of the FF 46 as a control signal for stopping the counting operation of the counting circuit 40. Further, the output K is supplied to the other input terminal of the AND gate 66, which is an inverted version of the output B, and when the output B is "L", the single pulse generated at the output K is used to control the timer circuit 60. is operated, and a single pulse is generated at the output L after one minute has elapsed.

The arithmetic circuit 68 is a circuit capable of adding and subtracting the heart rate stored in the heart rate storage circuit 24 and the count value of the count circuit 40, and when the output B is "H", the heart rate and the count value are calculated. The output B is
If "L", the count value is subtracted from the heart rate.
The calculation output of the calculation circuit 68 is supplied as a period setting signal to the comparison circuit 62 and the frequency division ratio converter 72 in the heartbeat signal generation circuit 70.

The heartbeat signal generation circuit 70 is a circuit that generates a heartbeat signal for generating a heartbeat sound with a period corresponding to the calculation output of the calculation circuit 68. The programmable counter 74 composed of 8 bits and the frequency dividing circuit 76 composed of 8 stages divide the clock signal φ ₃ (32768Hz) from the frequency dividing circuit 4, and the frequency division ratio of the programmable counter 74 is as follows. Division ratio converter 7
The output of the lower 4 bits of the frequency divider circuit 76 is set by the frequency division ratio setting signal from the AND gate 7.
8. The frequency division ratio converter 72 converts the period setting signal into a frequency division ratio setting signal for setting the frequency division ratio necessary for counting the period corresponding to the period setting signal. The relationship is expressed by the following relationship. In other words, if the value of the period setting signal is N1 and the value of the division ratio setting signal is N2, then
It is approximately expressed by the relationship N2 = 32768Hz/256÷N1/60sec. This frequency division ratio setting signal is transmitted to the programmable counter 7 every 4 seconds by the clock signal φ ₄ (1/4 Hz) from the frequency divider circuit 4.
Preset to 4. The above clock signal _φ3 ,
φ ₄ is supplied to the clock input terminal φ and the preset terminal PE via AND gates 80 and 82, respectively, and the output J of the FF 84 is also supplied to the AND gates 80 and 82. Further, the output E is supplied to the set terminal S of the FF 84, and the output C is supplied to the reset terminal R.

On the other hand, a pulse signal with a duty ratio of 1/16 corresponding to the period setting signal is generated at the output M of the AND gate 78, and this output M is further supplied to the AND gate 86. And the AND gate 86 also receives the audio frequency signal φ ₅ (for example, 2048Hz) from the frequency divider circuit 4.
is supplied to the sound generation circuit 19, and an output N from which a heartbeat signal is generated is supplied to the sound generation circuit 19.

This embodiment is constructed as described above, and the operation of this embodiment will be explained below using the time chart shown in FIG.

At time _t1 , when the ring stop switch 18 is closed, the output C becomes "L", so the counter 38 and
The reset of FF84 is released. At the same time, a single pulse from the one-shot circuit 50 is generated at the output D, FF30 is set, and the output G becomes "H".
At the same time, the output H is inverted to "L" and the operation of the timer circuit 56 is started. Therefore, heartbeat detection section 2
0 detection operation is started, and the counter 28 counts the detection signal via the waveform shaping circuit 22.

Then, at time _t2 , one minute after time _t1 , a single pulse from the timer circuit 56 is generated at the output E, so the count value of the counter 28, that is, the heart rate for one minute, is stored in the latch circuit 34, and the delay is delayed. The FF 30 is reset via the circuit 32, and the output G is inverted to "L" and the output H to "H". Therefore, the detection operation of the heartbeat detecting section 20 is stopped and the counter 28 is reset. Also, at time _t2 , the single pulse generated at output E causes FF4 to
6 is set to start the operation of the counting circuit 40, and FF84 is set to start the operation of the heartbeat signal generation circuit 70. That is, in the count circuit 40, the output I is inverted to "H", allowing the counter 41 to perform a counting operation, and since the output B is "L" at this time, the clock signal _φ2 is counted.

On the other hand, in the heartbeat signal generation circuit 70, the output J is inverted to "H" and the programmable counter 74 is operated. At time _t2 , the count value of the counter 41 is "0", so the heart rate (for example, "70") stored in the latch circuit 34 is directly supplied to the frequency division ratio converter 72 as a period setting signal. Therefore, a frequency division ratio of "110" is preset in the programmable counter 74, which results in a pulse signal having a period of approximately 0.86 seconds being generated at the output M. As a result, a heartbeat signal is similarly generated at the output N at a period of 0.86 seconds, and this is converted into a heartbeat sound by the sound generation circuit 19.

By the way, since the output B is "L", the arithmetic circuit 68 calculates the counter 41 from the heart rate of the latch circuit 34.
For example, if the clock signal _φ2 is set to 1/30Hz, the value of the frequency division ratio setting signal will increase every 30 seconds. Furthermore, the programmable counter 74 has 4
Since the presetting operation is performed every second, as the frequency division ratio becomes larger, the generation cycle of the pulse signal generated at the output M becomes longer, and the generation cycle of the heartbeat sound also becomes longer. For example, after 5 minutes have elapsed from time _t2 , the count value of the counter 41 is "10", the period setting signal is "60", and the frequency division ratio setting signal is "128", which is generated at the output M. The period of the pulse signal is 1 second, and the period of the heartbeat sound is also 1 second.
seconds. It will be understood that the generation cycle of the heartbeat sound gradually becomes longer in the same way.

Furthermore, the generation frequency of the clock signal φ ₂ can be varied by operating the variable resistor 38, and if the frequency is lowered, the counting operation of the counter 41 becomes slower, so that the rate of change at which the generation cycle of the heartbeat sound becomes longer becomes smaller. It is easily understood that if the frequency is increased, the rate of change will be increased.

Then, at time _t3 , when the cycle setting signal becomes smaller than "50" since the signal from the encoder 64, here the output B is "L", a single pulse is generated at the output K, the FF 46 is reset, and the output I
Since the counter 41 is inverted to "L", the counting operation of the counter 41 is stopped. At the same time, and gate 66
Since the timer circuit 60 is in an open state, the operation of the timer circuit 60 is started, and a heartbeat sound is generated at the same period while the timer circuit 60 is operating. and time t ₃
At time _t4 , one minute has passed since then, a single pulse from the timer circuit 60 generated at the output L is generated at the output C, and the FF 84 is reset and the operation of the heartbeat signal generation circuit 70 is stopped, so that the heartbeat sound is no longer heard. Occurrence is also stopped. At the same time, the count value of the counter 41 is also cleared.

On the other hand, when the set time arrives at time _t5 , the alarm start signal from the reference mechanism 14 causes the output B to become "H", and the output D is connected to the one-shot circuit 5.
A single pulse from 2 is generated. Therefore, like the operation from time t ₁ to time t ₂ , the number of heartbeats per minute is counted and stored in the latch circuit 34 . Then, at time _t6 , the single pulse generated at output E causes the counting circuit 40 and heartbeat signal generation circuit 70 to start operating in the same manner as at time _t2 . For example, if the heart rate stored in the latch circuit 34 is "50", the division ratio setting signal becomes "154" at time _t6 , so the output M has a pulse signal with a period of approximately 1.2 seconds. Occur. Also, since the output B is "H" at this time, the clock signal φ ₁ is supplied to the counter 41, and the arithmetic circuit 68 operates to add the heart rate stored in the latch circuit 34 and the count value of the counter 41. do. For example, if the clock signal φ ₁ is set to 1/2 Hz, the value of the frequency division ratio setting signal will decrease every 2 seconds. Further, since the programmable counter 74 performs a preset operation every 4 seconds, the smaller the frequency division ratio, the shorter the generation period of the pulse signal and heartbeat sound generated at the output M. For example, after 30 seconds have passed since time t ₆ , the count value of the counter 38 is "15", and the period setting signal is "65".
Since the frequency division ratio setting signal is "118", the period of the pulse signal generated at the output M is approximately 0.92 seconds, and similarly, the period of generation of the heartbeat sound is also approximately 0.92 seconds. It will be understood that the generation cycle of the heartbeat sound gradually becomes shorter in the same manner.

Of course, if the generation frequency of the clock signal φ ₁ is lowered by operating the variable resistor 38, the counting operation of the counter 41 will be slowed down, and the rate of change in which the generation period of the heartbeat sound will be shortened will be reduced; if the generation frequency is increased, the opposite will occur. The rate of change increases.

Then, at time _t7 , when the cycle setting signal becomes greater than "80" from the encoder 64, here since the output B is "H", a single pulse is generated at the output K, the FF 41 is reset, and the output I
is inverted to "L", so the counting operation of the counter 41 is stopped. Therefore, since the cycle setting signal does not change thereafter, the generation cycle of the heartbeat sound is also kept constant. Then, at time _t8 , when the ring stop switch 18 is opened, the output C becomes "H", and the FF84
Since the heartbeat signal generation circuit 70 is reset and the operation of the heartbeat signal generation circuit 70 is stopped, the generation of heartbeat sounds is also stopped. At the same time, the counter 41 is also reset.

(Effects of the Invention) As described above, according to this embodiment, the heartbeat sound generating device according to the present invention is combined with a watch with an alarm function, and after setting the alarm, the heartbeat sound synchronized with the heartbeat cycle is generated. By lengthening the generation cycle of the heartbeat sound over time, the user's heartbeat gradually decreases and acts to relax the user's mental state, thereby inducing a comfortable sleepiness in the user. In addition, when the set time arrives, a heartbeat sound synchronized with the heartbeat cycle is generated, and the cycle of the heartbeat sound is shortened as time passes, gradually increasing the user's heartbeat and normalizing the mental state. Because it works to put you in a state of , it can induce a comfortable awakening.

Furthermore, in this embodiment, the rate of change for lengthening and shortening the generation cycle of the heartbeat sound can be freely set by operating the variable resistor 38, which also serves as an external operation member. You can control your mental state according to your physical condition at the time.

In the heartbeat sound generating device according to the present invention, an external switch may be provided in place of the stop switch 18 and operated independently, or the oscillation frequency of the CR oscillator 37 may be set to the variable resistor 38 in the variable oscillation circuit 36. Although the clock signals φ ₁ and φ ₂ are thus made variable, a configuration may also be adopted in which the frequency division ratio is externally set using a programmable frequency divider.

As described above, according to the present invention, a heartbeat sound synchronized with the heartbeat cycle is generated, and the generation cycle of the heartbeat sound is changed over time and at a rate of change set by the user. By doing so, the user's mental state can be gradually relaxed, tense, or brought closer to normal, and the user's mental state can be controlled effortlessly.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a timepiece with an alarm function to which a heartbeat sound generator according to the present invention is applied. 2 and 3 are time charts showing the operation of FIG. 1. 14...Guide mechanism, 16...And gate, 1
8...Sound stop switch, 19...Sound generation circuit, 2
0... Heart rate detection unit, 24... Heart rate storage circuit, 3
6...Variable oscillation circuit, 40...Count circuit, 4
8...Operation control circuit, 68...Arithmetic circuit, 70...
...heartbeat signal generation circuit.

Claims (1)

[Scope of Claims] 1. A heartbeat sound generating device comprising: a heartbeat detection section that detects a heartbeat and outputs a detection signal thereof; and a sound generation circuit that converts the detection signal into a sound as a heartbeat signal; inputs an external signal, outputs an operation start signal in response to input of a first external signal or inputs a second external signal when the first external signal is input, and responds to the second external signal; The upper or lower limit set value of the heart rate per predetermined time set in advance is varied, and the operation is terminated when the heart rate per predetermined time of the heartbeat signal becomes larger or smaller than the upper or lower set value. an operation control circuit that outputs a signal, a heart rate storage circuit that counts the detection signal for a certain period of time after receiving the operation start signal and stores it as an initial heart rate, and a variable oscillation circuit that can arbitrarily vary the output frequency; a count circuit that counts the reference signal of the variable oscillation circuit from the end of the counting operation of the heart rate storage circuit until the time when the operation end signal is generated; an arithmetic circuit that adds or subtracts at regular time intervals in response to the signal; and a heartbeat signal having a cycle corresponding to the heart rate per predetermined time calculated by the arithmetic circuit for each cycle of the reference signal, and outputs to the sound generation circuit. A heartbeat sound generating device comprising: a heartbeat signal generating circuit;