JPS6182734A - Pulse sound generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a device that generates a heartbeat sound synchronized with the heartbeat cycle and then changes the generation cycle of the heartbeat sound over time, and further relates to a device that changes the generation cycle of the heartbeat sound over time, and The rate of change in the generation cycle can be set according to preference.

(Prior Art) Conventionally, as described in Japanese Patent Application Laid-Open No. 54-98651, there has been a heartbeat measuring device that detects a pulse wave, that is, a heartbeat, using a pulse detection device and generates a heartbeat sound corresponding to this detection signal. is publicly known.

By the way, the heart rate is about 70 to 80 beats per minute in normal conditions, and 50 to 80 beats per minute during sleep or in a state of mental relaxation.
It is known that the number of beats per minute decreases to about 60, and on the other hand increases to about 90 to 100 beats per minute during times of excitement or mental stress. It is said to be able to control people's mental states, etc.

(Problems to be Solved by the Invention) The present invention is a further development of the conventional heart rate measuring device described above, and its purpose is to provide a device that can easily control the mental state of the user. It is in.

(Means for Solving the Problems) In order to solve the above problems, the present invention generates a heartbeat sound synchronized with the heartbeat cycle, and then adjusts the generation cycle of the heartbeat sound to the user's control over time. It is characterized by changing according to a set rate of change.

(Example) Preferred embodiments of the present invention will be described below based on the drawings.

FIG. 1 shows an embodiment in which a heartbeat sound generating device according to the present invention is combined with a watch with an alarm function.

Oscillation circuit 22 frequency divider circuit 4. Waveform shaping circuit 6. motor 82
The wheel train 10 and the pointer display 12 constitute a conventional analog timepiece. The reference mechanism 14 is the wheel train 10
built into the system, and will run for about 20 minutes when the set time arrives.
An alarm start signal that becomes HJ is supplied to the AND gate 16. The AND gate 16 is also supplied with the output of a ring stop switch 18, and when the switch 18 is closed, an alarm start signal is generated by a heartbeat signal generation circuit 70, which will be described later.
A heartbeat signal is supplied to the sound generation circuit 19 from.

The sound generation circuit 19 is a circuit that converts a heartbeat signal into a heartbeat sound.

The heartbeat detection unit 20 is a device that detects a heartbeat and outputs a detection signal corresponding to the heartbeat to an output a as shown in FIG. External light is applied to the fingertip, and a phototransistor detects reflected light and transmitted light whose intensity is modulated by blood flow. The output a of the heartbeat detecting section 20 is transmitted to the waveform shaping circuit 22.
The supplied detection signal is shaped into a square wave with a constant pulse width and output to the output terminal.

- The heart rate storage circuit 24 is a circuit that counts the detection signal of the heartbeat detection section 20 for a certain period of time, one minute in this case, and stores the counted value. The detection signal via the waveform shaping circuit 22 is supplied to a counter 28 via an AND gate 26, and when the AND gate 26 is open, the detection signal, that is, the heart rate is counted by the counter 28. The output G of a flip-flop (hereinafter referred to as FF) 30 is supplied to the Ikekata input terminal of the AND gate 26, and when the output G is rHJ, the AND gate 26 is in an open state.

Note that the output G is also supplied to the heartbeat detection section 20, and the detection operation of the heartbeat detection section 20 is enabled only when the output G is rHJ. Further, the output H of the FF 30 is supplied to the reset terminal R of the counter 28. The set terminal S of the FF 30 is connected to an OR gate 54 in the operation control circuit 48, which will be described later.
The output of the timer circuit 5 is supplied to the reset terminal R.
6 is supplied via a delay circuit 32. Further, the latch circuit 34 is supplied with the count value of the counter 28, and stores the count value when a single pulse is output to the output E of the timer circuit 56.

The variable oscillation circuit 36 is a circuit whose oscillation frequency is varied by an external operating member, and includes a CR oscillator 37 and a variable resistor 38 which also serves as an external operating member. It is composed of a frequency dividing circuit 39 that divides the frequency of the oscillation output of the CR oscillator 37. As output signals, a clock signal φ1 varying between 3/4 Hz and 1/4 Hz and a clock signal φ2 varying between 3/6 oH3 are output.

The count circuit 40 is a circuit that counts the output signal of the variable excavation circuit 36 after the heart rate storage circuit 24 has finished counting. The counter 41 counts the clock signal supplied from the AND gate 42, and the clock signal selected by the switching gate 44 and the output 2 of the KFF 46 are supplied to the AND gate 42. The switching gate 44 is supplied with the signals φ07 and φ2 from the frequency dividing circuit 39 in the variable oscillation circuit 36, and the output B is supplied to the switching control terminal. Then, if the output B is rHJ, the clock signal φ1 is applied, and if the output B is “L”, the clock signal φ
Select and output 2.

This is a circuit that outputs a summons. The single pulses generated from the one-shot circuits 50 and 52 are both supplied to the OR gate 54, and the single pulse generated at the output of the OR gate 54 is applied to the center of the FF 30 as described above as a control signal to start counting the heart rate. Supplied to terminal S. Further, the single pulse generated at the output E starts the operation of the timer circuit 56, and after one minute has elapsed, a single pulse is generated at the output E again.

The single pulse generated at this output E is processed by the counter 2 as described above.
The preset terminal of the latch circuit 34, the delay circuit 32 and It is supplied to the cent terminal S of the FF46. The output A is supplied to the full shot circuit 50, and the output B is supplied to the one shot circuit 52.

Further, the output A is inverted and supplied to the OR gate 58, and the output C of the OR gate 58 is supplied to the reset terminal R of the counter 41 as a control signal for resetting the counter 41. The OR gate 58 is also supplied with the output of a timer circuit 60, which will be described later.

Furthermore, the comparison circuit 62 is a circuit that compares an output signal from an arithmetic circuit 68, which will be described later, and a code signal from the encoder 64. When the output B is "H", the value of the code signal from the encoder 64 is compared to the arithmetic circuit 68. A single pulse is generated at output K when the value of the output signal from B becomes large, and conversely, when output B becomes low, a single pulse is generated at output K. In this embodiment, the code signal of the encoder 64 is r80J if the output B is rHJ.

It is set to be "50" if the output B is rLJ. The single pulse generated at the output K is supplied to the reset terminal R of the FF 46 as a control signal for stopping the counting operation of the counting circuit 40. Further, the output is supplied to the other input terminal of an AND gate 66 which is supplied with an inverted output B, and when the output B is rLJ, the timer circuit 60 is operated by a single pulse generated at the output K. After 1 minute has elapsed, a single pulse is generated at the output.

The arithmetic circuit 68 is a circuit that can add and subtract the heart rate stored in the heart rate storage circuit 24 and the count value of the count circuit 40, and if the output B is rHJ, it adds the heart rate and the count value, If the output B is rLJ, the count value is subtracted from the heart rate.

The calculation output of the calculation circuit 68 is then sent to the comparison circuit 62 and the frequency division ratio converter 7 in the heartbeat signal generation circuit 70 as a period setting signal.
2 is supplied.

The heartbeat signal generation circuit 70 is a circuit that generates a heartbeat signal for generating a heartbeat sound with a period corresponding to the calculation output of the calculation circuit 68. A programmable counter 74 composed of 8 bits and a frequency dividing circuit 76 composed of 8 stages divide the clock signal φ3 (32768 Hz) from the frequency dividing circuit 4, and the frequency division ratio of the programmable counter 74 is It is set by the frequency division ratio setting signal from the frequency ratio converter 72, and the outputs of the lower four pins of the frequency division circuit 76 are supplied to the AND gate 78. The frequency division ratio converter 72 converts the period setting signal into a frequency division ratio setting signal for setting the frequency division ratio necessary for counting the period corresponding to the period setting signal, and is a fixed setting signal. The relationship is expressed by the following relationship. That is, if the value of the period setting signal is Nl and the value of the frequency division ratio setting signal is N2, the relationship is expressed as approximately 32768 Hz Nl. This frequency division ratio setting signal is applied to the frequency division circuit 4.
The programmable counter 74 is preset by the clock signal φ4 (1/4 Hz) from the clock signal φ4 (1/4 Hz), that is, every 4 seconds. The clock signals φ3 and φ4 are passed through AND gates 80 and 82 to the clock input terminals φ and φ4, respectively.
is supplied to the preset terminal PE, and the AND gates 80, 8
2 is also supplied with the output J of FF84. Also FF8
The output E is supplied to the set terminal S of No. 4, and the output C is supplied to the reset terminal R of No. 4, respectively.

On the other hand, a pulse signal with a duty ratio of 1/16 corresponding to the period setting signal is generated at the output M of the AND gate 78, and this output M is further supplied to the AND gate 86. The AND gate 86 is also supplied with an audio frequency signal φ, (for example, 2048 Hz) from the frequency dividing circuit 4, and supplies an output N from which a heartbeat signal is generated to the sound generation circuit 19.

This embodiment is constructed as described above, and the operation of this embodiment will be explained below using the time chart of FIG. 3.

At time t, when the ring stop switch 18 is closed, the output C becomes rLJ, and the reset of the counter 38 and the FF 84 is canceled. At the same time, a single pulse from the one-shot circuit 50 is generated at the output D, the FF 30 is set, the output G is inverted to rHJ, the output H is inverted to rLJ, and the timer circuit 56 starts operating. Therefore, the detection operation of the heartbeat detecting section 2° is started, and the counter 28 counts the detection signal via the waveform shaping circuit 22.

Then, at time L2, one minute after time t1, a single pulse from the timer circuit 56 is generated at the output E, so the count value of the counter 28, that is, the heart rate for one minute, is stored in the latch circuit 34, and the delay circuit 32 FF30 via
is reset, the output G is inverted to rLJ, and the output H is inverted to rHJ. Therefore, the detection operation of the heartbeat detecting section 20 is stopped and the counter 28 is reset. Also time t2
In this case, the single pulse generated at the output E causes the FF4
6 is set to start the operation of the counting circuit 4o, and at the same time, the FF 84 is set to start the operation of the heartbeat signal generation circuit 70. That is, in the count circuit 40, the output is inverted to rHJ, allowing the counter 41 to perform a counting operation, and since the output B is rLJ at this time, the clock signal φ2 is counted.

On the other hand, in the heartbeat signal generation circuit 70, the output J is inverted to rHJ and the count value of i of the programmable counter 74 is "0", so the heartbeat rate (for example, r70J) stored in the launch circuit 34 is directly used as the cycle setting signal. The signal is supplied to a frequency division ratio converter 72. Therefore, the frequency division ratio rlloj is preset in the programmable counter 74, so that a pulse signal with a period of approximately 0.86 seconds is generated at the output M. As a result, a heartbeat signal is similarly generated at the output N at a period of 0.86 seconds, and this is converted into a heartbeat sound by the sound generation circuit 19.

By the way, since the output B is "L", the arithmetic circuit 68 acts to subtract the count value of the counter 41 from the heart rate of the latch circuit 34, and for example, the clock signal φ2 is 1 /
If it is set to 30 Hz, the value of the frequency division ratio setting signal will increase every 30 seconds. Further, since the programmable counter 74 performs a preset operation every 4 seconds, as the frequency division ratio increases, the generation period of the pulse signal generated at the output M becomes longer, and the generation period of the heartbeat sound also becomes longer. For example, after 5 minutes have passed from time t2, the count value of the counter 41 is "10", the period setting signal is r 60 J, and the frequency division ratio setting signal is [1
28'', the cycle of the pulse signal generated at the output M is 1 second, and similarly the cycle of the heartbeat sound is 1 second. It will be understood that the generation cycle of the heartbeat sound gradually becomes longer in the same way.

Furthermore, the frequency at which the clock signal φ2 is generated can be varied by operating the variable resistor 38.
It is easily understood that since the counting operation of 1 becomes slower, the rate of change in the generation period of the heartbeat sound becomes longer is small, and if the frequency is made higher, the rate of change becomes larger.

Then, at time t3, the cycle setting signal is output to the encoder 6.
The signal from 4, here output B is "L", so it is "5".
0", a single pulse is generated at the output K and F
Since F46 is reset and the output r is inverted to rLJ, the counting operation of the counter 41 is stopped. At the same time, since the AND gate 66 is open, the timer circuit 60 starts operating, and heartbeat sounds are generated at the same cycle while the timer circuit 60 is operating. and time t3
At time t4, one minute has passed since then, a single pulse from the timer circuit 60 is generated at the output C, and the FF
84 is reset and the operation of the heartbeat signal generation circuit 70 is stopped, so that the generation of the heartbeat sound is also stopped. At the same time, the count value of the counter 41 is also cleared.

On the other hand, when the set time arrives at time t, the output B becomes "H" in response to the alarm start signal from the reference mechanism 14, and a single pulse is generated from the shot shot circuit 52 at the output. Therefore, in the same way as the operation from time t to time t2, the heart rate for one minute is counted and stored in the launch circuit 34. Then, at time t6, the single pulse generated at the output E causes the count circuit 4 to
0 and the operation of the heartbeat signal generation circuit 70 is started. If the heart rate stored in the latch circuit 34 is, for example, "50", then at time t6 the frequency division ratio setting signal is r1.
54j, a pulse signal with a period of about 1.2 seconds is generated at the output M. Further, since the output B is rHJ at this time, the clock signal φ1 is supplied to the counter 41, and the arithmetic circuit 68 acts to add the heart rate stored in the launch circuit 34 and the count value of the counter 41. and,
For example, if the clock signal φ1 is set to 1/2 Hz, the value of the frequency division ratio setting signal will decrease every 2 seconds. Furthermore, since the programmable counter 74 performs a preset operation every 4 seconds, the smaller the frequency division ratio, the shorter the generation period of the pulse signal and heartbeat sound generated at the output M. For example, 30 from the time 〇
After seconds have passed, the count value of the counter 38 is "15"
Since the period setting signal is r65J and the frequency division ratio setting signal is rL18J, the period of the pulse signal generated by the output MK is approximately 0.92 seconds, and similarly the period of the heartbeat sound is approximately 0.92 seconds. seconds. It will be understood that the generation cycle of the heartbeat sound gradually becomes shorter in the same manner.

If the generation frequency of the clock signal φ is lowered by operating the thermal variable resistor 38, the counting operation of the counter 41 will be slowed down, and the rate of change in which the generation period of the heartbeat sound will be shortened will be reduced; if the generation frequency is increased, the opposite will occur. The rate of change increases.

Then, at time t, the cycle setting signal is output to the encoder 6.
Since the output B is rHJ, the signal is "8".
When υ becomes larger than 0, a single pulse is generated at the output K and F
Since F41 is reset and the output is reversed to rLJ, the counting operation of the counter 41 is stopped. Therefore, since the cycle setting signal will not change from now on, the generation cycle of the heartbeat sound will also change.
remains constant. Then, at time t8, when the noise stop switch 18 is opened, the output C becomes rHJ, and the FF8
4 is reset and the operation of the heartbeat signal generation circuit 70 is stopped, so that the generation of the heartbeat sound is also stopped. At the same time, the counter 41 is also reset.

(Effects of the Invention) As described above, according to this embodiment, the heartbeat sound generation device according to the present invention is combined with nine watches with an alarm function, and after the alarm is set, a heartbeat sound synchronized with the heartbeat cycle is generated. By increasing the period of heartbeat sound generation over time,
Since it acts to gradually reduce the user's heart rate and relax the user's mental state, it can induce a comfortable sleepiness in the user.

In addition, when the set time arrives, a heartbeat sound synchronized with the heartbeat cycle is generated, and then the cycle of the heartbeat sound is shortened as time passes, gradually increasing the user's heartbeat and improving the user's mental state. It works to bring you back to your normal state, so you can wake up comfortably.

Furthermore, in this embodiment, the rate of change to lengthen and shorten the heartbeat sound generation cycle can be freely set by operating the variable resistor 38, which also serves as an external operation member.
It is possible to control the mental state according to individual differences in heart rate and physical condition at the time of use.

In the heartbeat sound generating device according to the present invention, an external switch may be provided in place of the ringing stop switch 18 and operated independently, and the CR oscillator 3 may be operated independently in the variable oscillation circuit 36.
Although the oscillation frequency of clock signals φ1 and φ2 is varied by the variable resistor 38, the frequency division ratio may be set externally using a programmable frequency divider.

As described above, according to the present invention, a heartbeat sound synchronized with the heartbeat cycle is generated, and the generation cycle of the heartbeat sound is changed over time and at a rate of change set by the user. As a result, the user's mental state can be gradually relaxed, tense, or brought closer to normal, and the user's mental state can be controlled effortlessly.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing a watch with an alarm function to which a heartbeat sound generator according to the present invention is applied. 2 and 3 are time charts showing the operation of FIG. 1. 14... Reference mechanism, 16... And gate, 18... Ring stop switch, 19... Sound generation circuit,
20... Heartbeat detection unit, 24... Heart rate storage circuit, 36... Variable oscillation circuit, 4o... Count circuit, 48... Operation control circuit, 68... Arithmetic circuit,
70... Heartbeat signal generation circuit.

Claims (1)

[Claims] A heartbeat detection unit that detects a heartbeat and outputs a detection signal corresponding to the heartbeat; a heartbeat rate storage circuit that counts the detection signal for a certain period of time and stores the count value; and an oscillation frequency that is variable by an external operating member. a variable oscillation circuit that counts the output signal of the variable oscillation circuit after the count operation of the heart rate storage circuit is completed; and a count circuit that counts the output signal of the variable oscillation circuit after the heart rate storage circuit has finished counting; a heartbeat signal generation circuit that generates a heartbeat signal for generating a heartbeat sound with a period corresponding to the calculation value of the calculation circuit at regular intervals;
A heartbeat sound generation device comprising: a sound generation circuit that converts the heartbeat signal into a heartbeat sound.