JPH0351948A - Memory controller - Google Patents

Abstract

PURPOSE:To omit the hardware, etc., required for a CPU to control the sequence of process requests given to a memory by transmitting the memory reply data to a requester processor in the reception order of the memory process requests. CONSTITUTION:A reply timing buffer 43 holds a process request selected by a priority deciding circuit 42, a bank address, and a reception register number until the transmission timing is received from a memory 4 for the reply data. A reply data control circuit 44 reads the reply data to be sent to the CPU 1 and 2 out of the reply data reception buffers 45 and 46 and controls these replay data based on the output of the buffer 43 and in the reception order of process requests of a memory controller 3. Thus the process requests given to the memory 4 from the CPU can be processed without loosing the sequence of those requests. As a result, an effective process is ensured without adding any extra hardware nor firmware to the CPU.

Description

TECHNICAL FIELD The present invention relates to a memory control device, and more particularly to priority determination control for memory processing requests in a data processing device.

Prior Art Conventionally, priority determination processing for memory processing requests in a memory control device is performed as follows.

That is, the busy state of the memory bank in response to the first processing request from the arithmetic processing unit is checked by referring to the bank busy indicator, and if the bank is not busy, the priority among the arithmetic processing units is determined, and the processing The request is accessed from memory and processing is started.

If the memory bank for the first processing request is in a bank busy state, priority is given to the next processing request. At this time, it is assumed that the request code sent from the arithmetic processing unit is processed without order in the memory.

In addition, as another conventional method, address information for a processing request is set, a register is provided in which the address information is sequentially shifted, and the system waits until the memory bank for that address becomes free, thereby preventing access conflicts. When this occurs, some systems prioritize access to registers located at later stages.

In such conventional memory control methods, when the first processing request is in the bank busy state for memory processing requests and memory bank addresses from multiple processing units, the next processing request is processed regardless of the previous processing content (request code). This results in giving priority to processing requests. On the arithmetic processing device side, it is necessary to take into account that the request code sent from itself is not processed continuously, so there is a drawback that the arithmetic processing device side must be controlled by hardware or firmware.

Purpose of the Invention Therefore, the present invention has been made to eliminate the drawbacks of the above-mentioned prior art, and its purpose is to control processing requests from an arithmetic processing unit to memory without losing the order of processing requests. The object of the present invention is to provide a memory control device that does not require any hardware or firmware for performing the control on the arithmetic processing device side.

According to the present invention, there is provided a memory control device that processes memory processing requests from a plurality of processing devices while determining priorities, the memory control device being provided corresponding to each of the processing devices,
A plurality of reception registers are provided for accepting multiple memory processing requests when the memory request code is the same from corresponding processing devices, and a register is provided corresponding to each of the processing devices, and a memory processing request that is received first in the reception register is provided. Memory processing requests output by each of the priority I'l1 determining means that prioritizes and outputs the next memory processing request accepted when the address indicates a busy state, and the priority 111 determining means corresponding to these processing devices. means for determining the priority among each processing device according to a priority determination criterion set in advance; and means for transmitting the memory request request to the requesting processing device in the order in which the memory processing request is received by the reception register. A memory control device is obtained, characterized in that it includes:

Example Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

A memory processing request from an arithmetic processing unit (CPU) 1.2 is subjected to priority determination processing by a memory control device 3, and output as a memory processing request to a main storage device (hereinafter referred to as memory) 4. Further, the memory data from the memory 4 is processed by the memory control device 3 so that it is sent back to each CPUI 2 in order.

#1 to #3 reception registers 31 to 3 corresponding to CPUI
3 are provided, and first and third memory processing requests (including memory bank addresses) from the CPUI are stored in correspondence with each other.

The same applies to the reception registers 34 to 36 of #1 to #3 provided corresponding to the CPU 2.

The control circuit 37 receives the memory request code from the CPUI, and when the request codes of the processing requests are the same and consecutive, and the processing request stored in the #1 reception register 31 is unprocessed, the control circuit 37 receives the memory request code from the CPUI. The next processing request is stored in the #2 acceptance register 32.

Similar control is performed for the reception register 33 of #3.

Further, a control circuit 38 corresponding to the CPU 2 also has the same function as the control circuit 37.

A bank busy indicator (BBI) 41 indicates that a memory bank is in a busy state due to a processing request to the memory 4.

The priority determination circuit 39 includes reception registers 31 to 33.
Acceptance register 3 of #1 among the processing requests stored in
The processing request in #1 is output with the highest priority, and if the bank address of the reception register 31 of #1 is busy, #2 is output.
The processing request of the reception register 32 is given the next priority and output. Further, if the bank address of the reception register #2 is in a busy state, the processing request of the reception register 33 #3 is output with priority next.

Regarding the priority determination circuit 40, the BBI4 is also
1 and similarly performs priority processing and outputs.

The priority determination circuit 42 performs priority determination processing between two CPUs.
I is set in advance so that it has a high priority with respect to the CPU2.

The reply timing buffer 43 holds the processing request selected by the priority determination circuit 42, the bank address, and the reception register number until the timing when the reply data is sent from the memory 4.

The reply date reception buffers 45 and 46 are buffers for temporarily storing the reply reply data from the memory 4.
Compatible with UI and 2. The reply data control circuit 44 uses the output of the reply timing buffer 44 to control reading of the reply data to be sent to the CPU I, 2 from the reply reception buffer in the order in which the processing requests are received by the memory control device 3.

In such a configuration, at the same time that a processing request (including a bank address) from the CPUI is sent to the #1 reception register 31, a request code is sent to the control circuit 37.
sent to. The request codes are consecutive and #
When the processing request in the #1 acceptance register 31 is determined to be unprocessed, it is supplied to the #2 or #3 acceptance register.

The output of the #1 reception register 31 is processed by three priority ↑ resetting circuits based on the priority determination and the contents of the BBI 41, and if the bank address is not in a busy state, this processing request is processed as is. If it is in a busy state, the check target shifts to the output of the #2 reception register 32 based on the priority determination.

The processing request and bank address bused in the priority judgment circuit 39 are the reception, register number and CPU
It is supplied to the priority determination circuit 42 at the next stage together with the number.

The priority determination circuit 42 uses the output of the priority determination circuit 40 processed in the same manner as the three priority determination circuits, and stores the output determined according to the priority determination criteria preset for each CPU in the memory 4.
It will be supplied as a memory request.

The memory libri for this processing request is accepted as a reply date in the libri data reception buffer 45 or 46. When a request is accepted or privately received, the reply data control circuit 44 determines which processing request the reply date is accepted in relation to the requesting CPU's processing request, and the requesting CPU reply data is read out in the order of reception. will be supplied.

FIG. 2 is a circuit diagram showing a specific example of the optical data control circuit 44. LiBriday evening reception buffer 745 compatible with CPUI! IiH! ! Although only the control section 1 will be explained, the control section corresponding to the CPU 2 is also completely equivalent.

Reception register number included in Libra Day evening (memory 4
The register number (register number at which the processing request processed as a memory request was accepted) is supplied to the decoder 51 and the write address register 59, respectively. This decoder 5
1 identifies the reception register number in response to the reply timing regarding the CPUI from the reply timing buffer 43, and outputs the output #1 corresponding to the reception register #1 to #3.
One of #1 to #3 is made active.

Each output #1 to #3 is manually inputted to S-R flip-flop (P/P) 52 to 54 provided corresponding to each output, and outputs #1 to #3 are inputted in response to the reply timing.
The contents of #3 are taken in and set in the corresponding P/Ps 52-54.

[' The output of P/F 52 and the #2 output of decoder 51 are supplied to the two-man AND gate 55, and the outputs of P/Fs 52 and 53 and the output of decoder #3 are supplied to the three-man AND gate 56. Ru. The respective outputs of these AND gates 55 and 56 and the #1 output of the decoder 5l are applied to a triple OR gate 57, and this OR gate output is input to a read address counter 58.

This read address counter 58 is incremented (+
1) It is a counter whose contents increments sequentially from 0 to 3, and when it reaches "3", a carry output is generated to reset each P/P 52 to 54.

The reply date related to the CPUI is stored in the reply data reception buffer 45 corresponding to the CPUI every time a rewrite timing is generated. The storage address is generated from five write address registers, and the reception register number at the relevant reply timing becomes the write address.

Reading from the reply date reception buffer 45 is performed using the output address of the read address counter 58. First, at the initial stage, all P/F
The contents of 52 to 54 are in the reset state, and therefore the contents of the read address counter 58 are also "0".

At this time, if the processing request is preferentially received by the reception register #1, this library date reception buffer 45 is stored at an address corresponding to the #1 reception register number in the private date reception buffer 45. At the same time, the output #1 becomes active by the decoder 51, and the read address counter 58 becomes "1" due to the output of the OR gate 57. Therefore, the address corresponding to the #1 reception register number in the private reception reception buffer 45 becomes active. is read out and sent to CPUi.

Next, assume that the processing request for the #2 reception register is processed following the processing request for the #3 reception register. #3, #
#3 in the private reception buffer 45 for each processing request of #2. They are sequentially stored in the addresses corresponding to #2.

For #3, the contents of the read address counter 58 do not change at all, and in this example, it indicates the read address "1" corresponding to the previous #1.

For the next #2, the AND gate 55 is turned on, and the OR gate 57 causes the read address counter 58 to count up by +1. Therefore,
The read address becomes "2", and in the order in which the live birthday cards corresponding to #2 of the live birthday reception buffer 45 are received, they are sent to the requesting CPUs 1 and 2 as the cold birthday messages.

Effects of the Invention As described above, according to the present invention, when the same request code occurs consecutively, if the bank address of the first processing request is in a busy state, the next processing request is processed with priority, and the data is removed from the memory. Since the bridal party is returned to the request source in the order of requests, there is an effect that the processing requests from the processing device to the memory can be processed without losing the order of the processing requests.

Therefore, on the processing device side, it is possible to improve processing performance and efficiently process memory without adding extra hardware or firmware.

[Brief explanation of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing a specific example of a bride's day reception buffer control circuit. Explanation of symbols of main parts 1.2...CPU 3...Memory control device 4...Memories 31 to 36...Reception registers 39, 40, 42 ...Priority judgment circuit 41...
... Bank busy indicator 43 ... Reply timing buffer 44 ... Reply data reception buffer control circuit

Claims (1)

[Claims] (1) A memory control device that processes memory processing requests from a plurality of processing devices while determining priorities, and is provided corresponding to each of the processing devices, and is provided with a memory request code from the corresponding processing device. a plurality of reception registers for accepting a plurality of memory processing requests when A priority determination means that prioritizes and outputs the memory processing request received next, and a priority determination means corresponding to these processing devices processes each output memory processing request according to a preset priority determination criterion. A memory control device comprising: means for determining priorities between devices; and means for sending memory reply data to request source processing devices in the order in which memory processing requests are accepted by the acceptance register.