JPH0351973A - Microcomputer - Google Patents

Abstract

PURPOSE:To eliminate the need to execute a flag reset instruction and to simplify hardware and to lighten the load on software by providing a delay circuit which consists of an RS flip-flop and holds its input state for a next instruction cycle. CONSTITUTION:The microcomputer is equipped with an instruction decoder 1 which decodes a mode setting instruction, the RS flip-flop 2 which delays the output of the decoder 1 to specific timing of a next instruction cycle, and a data switching circuit 3 which selects and outputs the data of a RAM 6 or register 7 and the data of an accumulator 4 to the input terminal of an ALU 5 on the side of the accumulator 4 according to the output of the flip-flop 2. Then a memory mode is reset automatically at the end of the instruction cycle right after the setting of the memory mode. Consequently, the flag reset instruction need not be executed, the constitution of the instruction decoder is simplified, and the load on the software can be lightened.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Industrial Application Field This invention relates to a microcomputer that has two modes: an operation using an accumulator, a transfer mode and an operation using a memory, and a transfer mode. Microcomputers are classified into accumulator type, general-purpose register type, and memory type depending on the register configuration.The accumulator type has the advantage of a simple instruction format, and most 4- to 8-bit microcomputers belong to this type.General-purpose type The register method does not have an accumulator, but has general-purpose registers for arithmetic operations, transfers, and address calculations, and processes data using a two-address method. Because of its high degree of freedom, it is often used in 16-bit microcomputers. In addition, in the memory method, all registers are mapped on memory, and operations are performed between memories.Therefore, in order to take advantage of the advantages of each method described above, in recent years, an instruction set for the accumulator method and an instruction set for the memory method have been developed. Microphone viewers equipped with both of these functions are now available.

A conventional microcomputer will be explained with reference to FIG.

In the figure, (11) is an instruction decoder, (12) is a mode switching flag, (13) is a data switching circuit, and (14) is a data switching circuit.
is an accumulator, (15〉 is an arithmetic logic unit (
(hereinafter referred to as ALU), (16> and (17>) are first and second memories, respectively, and (18) is an internal bus.

When performing inter-memory calculations and transfers (memory mode) with a conventional microcomputer configured as described above,
Prior to execution of the calculation and transfer command, a mode set command SF written in a main memory circuit (not shown) is executed. As a result, the instruction decoder (11) outputs the memory mode flag FM and sets the mode switching flag <12>. The set output of the mode switching flag (12>) connects the B contact and C contact of the data switching circuit (13>), and connects the internal bus (18) to the data switching circuit (13>'s B contact - C contact -
A path consisting of the ALU (15) is formed to enable calculations and transfers without using the accumulator (14).

In contrast, operations using accumulators, transfers (
When executing the accumulator mode), a mode reset instruction RFM written in a main memory circuit (not shown) is executed prior to execution of the calculation and transfer instructions. As a result, the instruction decoder (11) outputs the accumulator mode flag FA and resets the mode switching flag (12>).The reset output of the mode switching flag (12>) connects the a contact and the c contact of the data switching circuit (13). The internal bus (18), the accumulator (14), the A contact of the data switching circuit (13) to the C contact, and the ALU (15) are formed, and calculations and transfers using the accumulator (14) are performed. .

In the microcomputer configured as described above, it is not determined whether the microcomputer is in accumulator mode or memory mode except at the time of start, so great care must be taken when creating software. In addition, large-scale software has the disadvantage that it imposes a large burden on the software, such as requiring initial setting of the mode switching flag for each routine. Furthermore, from a hardware perspective, the configuration of the instruction decoder (11) is complicated because it requires two instructions: a flag reset instruction and a flag set instruction to change the mode, and this flag must be saved during interrupt processing. It has its drawbacks.

{c} Problems to be Solved by the Invention The present invention has been made in view of the above-mentioned points of conventional microcomputers, and an object thereof is to provide a microcomputer that does not require execution of a flag reset instruction. The object of the present invention is to provide a microcomputer with simple hardware and light software load.

(2) Means for Solving the Problem The above problem is solved by the following: means for decoding the mode setting command; means for delaying the output of said means until a predetermined timing of the next command cycle; This problem can be solved by a microcomputer equipped with means for selectively outputting RAM or register data and accumulator data to the accumulator side input terminal of the ALU.

(E) Effect The above configuration operates so that the memory mode is automatically canceled at the end of the instruction cycle following the setting of the memory mode, thereby eliminating the need to execute the flag reset instruction.
This simplifies the configuration of the instruction decoder and reduces the burden on software.

(to) Example An embodiment of the present invention will be described with reference to FIG.

In the figure, (1) is an instruction decoder, (2) is a delay circuit composed of an RS flip-flop or a D flip-flop and holds the input state during the next instruction cycle, and (3) is a word-based data switch. circuit, (4) is an accumulator, (5> is an ALU, (6) and (7)
is a general-purpose register or a register set to RAM, or RAM (in the following explanation, it is unified to memory), (8
) is an internal bus, and in the data switching circuit (3), when there is no control signal, terminals a and C are closed, and the internal bus (8), accumulator (4) - ALU (5
) bus is formed, thereby guaranteeing an arithmetic operation using an accumulator (accumulator mode).

Examples of arithmetic instructions that can be executed by this embodiment are (1) first
Operand ← 1st operand + 2nd operand The operation of the embodiment will be explained as an example.

When the mode setting instruction SFM is decoded by the instruction decoder (1), the instruction decoder (1) outputs a microinstruction F1 specifying an inter-memory operation (memory mode) to the delay circuit (2). This microinstruction is simultaneously output to an interrupt inhibiting means (not shown), and the interrupt is suspended until the execution of the following arithmetic instruction is completed. Furthermore, the microinstruction FM is transferred from the instruction decoder (1) to the accumulator (
It is also provided for changing another microinstruction outputted for input gate control (not shown) in step 4) into a control signal for the input gate of the first input gate.

This will be explained in more detail with reference to the timing chart in FIG.

A microcomputer fetches instructions from its main memory circuit and executes them through a series of instruction cycles. In an actual microcombiner, both the fetch cycle and the instruction execution cycle are composed of more complex sequences, but to simplify it, each cycle consists of a control pulse φ for fetch and a control pulse φ for execution. , can be explained as two-phase operation based on two-phase pulses.

In FIG. 2(A), when the mode setting command S F M is decoded by the command decoder (1) at timing t,
At timing t, the instruction decoder (1) outputs a microinstruction FM specifying the memory mode.

The RS flip-flop, which inputs this microinstruction FM to the set terminal and inputs the control pulse φ, for executing the instruction to the reset terminal, is set at the falling edge of the microinstruction FM, and reset at the rising edge of the control pulse φ,. It outputs a high level only during the next instruction cycle, that is, during the fetch/execution periods ts and tm of the arithmetic instruction. By the output of this RS flip-flop, the contacts of the data switching circuit (3) are controlled to connect the terminals b and C, and a path of the internal bus (8) - ALU (s) is formed.

As a result, at timing t, the first Pelland, the second
If the data in the memory (6) and memory (7) specified by the operand is sequential, or if the internal bus (8) is a multibus, the ALU (5) in addition mode is
) is entered. The addition result of this ALU (5>) is output to the memory (6>) designated by the first operand at a further subdivided subsequent timing within timing t.

In the subsequent instruction cycle represented by timings ts and ts, since the output of the delay circuit (2> is at a low level), the operation using the accumulator (4) 4 - accumulator + second operand is performed. executed.

? FIG. 2(B) shows divided execution control signals φ11, φ. The timing of an embodiment that utilizes the rising edge of φ■ is explained. In the figure, at timing t1, the mode setting command SFM is sent to the command decoder (1).
When decoded at timings t■ and t. The instruction decoder 1 specifies the memory mode in the microinstruction F
Output M. The RS flip-flop inputs this microinstruction F1 to the set terminal and inputs the control pulse φ■ for executing the instruction to the reset terminal.
M is set at the falling edge of control pulse φ. It is reset at the rising edge of , and outputs a high level only during the next instruction cycle, that is, the fetch/execution period jl+j41 of the arithmetic instruction. The output of this RS flip-flop causes the contacts of the data switching circuit (3) to switch between terminals B and C.
internal bus (8) - A L
A path of U (5) is formed.

As a result, at timing t41, the memory (6) and memory (7) specified by the first and second peripheries are
data can be sent sequentially or via the internal bus (8)
If is a multibus, the ALU (
5) is input. The addition result of this ALU (5) is obtained at timing t. The memory specified by the first year old Peland (
6) is output. By modifying other microinstructions, it is also possible to execute an instruction such as accumulator ← 1st operand + 2nd operand. In the subsequent instruction cycle represented by timings ji and ta, since the output of the delay circuit (2) is at a low level, an operation using the accumulator 4←accumulator+2nd periphery is executed. Ru.

Although an example in which an RS flip-flop is used as the delay circuit (2) has been described above, it is clear to those skilled in the art that a D flip-flop can be used in the same way. According to the invention, since the mode setting command can be only a flag set command, the number of command sets is reduced, the configuration of the command decoder is simplified, and a plug reset program for mode setting is not required. Therefore, it is possible to provide a microcomputer that has a light burden on software and has remarkable effects such as no need to save flags during interrupt processing.

[Brief explanation of drawings]

FIG. 1 is a partial block diagram of one embodiment of the present invention, FIGS. 2A and 2B are timing charts of different embodiments, and FIG. 3 is a partial block diagram of a conventional example. (1). (11)...Instruction decoder, (2>・
...Delay circuit, (3), (13)...Data switching circuit, (4), (14)...Accumulator,
(5) (15)...ALU, (6), (7).
(16), (17)...memory, (8)(ta
)...Internal bus, (12)...Mode switching flag,
(9)...Memory mode flag, (FA)...
Accumulator mode flag.

Claims (2)

[Claims] (1) means for decoding a mode setting instruction; means for delaying the output of said means until a predetermined timing of the next instruction cycle; and based on the output of said delay means, data in the ram or register is sent to an input terminal on the accumulator side of the ALU. and means for selectively outputting the data of the accumulator. (2) The microcomputer according to claim 1, wherein the delay means is constituted by an RS flip-flop that is set at the falling edge of the output of the means for decoding the mode setting command and reset by the command execution control signal.