JPH0352060Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a digital television receiver having a function of displaying signals from an external signal generating device such as a character multiplexing adapter or a personal computer.

[Technical background of the invention] A digital television receiver (hereinafter referred to as a digital TV receiver) converts an analog input signal from an antenna into a digital signal,
This digital signal is separated into a luminance signal and a chrominance signal, and luminance signal processing and chrominance signal processing are performed digitally, respectively. The signals that have passed through each processing circuit are converted back into analog signals and supplied to the picture tube. Also, like analog television receivers, digital TV receivers can be connected to an external signal generating device such as a character multiplexing adapter or a personal computer.
It usually has a function of selectively switching and displaying signals from an antenna and signals from external equipment.

An example of a digital TV receiver having such an external signal switching display function is shown in Fig. 4.
Its configuration will be explained.

In FIG. 4, reference numeral 1 is an input terminal to which a composite video signal from a TV antenna, video tape recorder, etc. is supplied, and this signal is
A tuner/intermediate frequency amplification/detection circuit (hereinafter referred to as tuner/PIF circuit) 2 performs first and second detection and supplies the detected signals to a buffer circuit 3. The output of the buffer circuit 3 is supplied to a digital processing circuit 4 comprising an adder, a multiplier, a delay circuit, etc., and also supplies a synchronizing signal component to a blanking signal generation circuit 5. This blanking signal generation circuit 5 generates a horizontal blanking signal that defines a blanking area on the screen of the signal to be displayed in response to the input/output delay time based on the digital processing circuit 4. The signal is supplied to the digital processing circuit 4 to control the output of the circuit 4. The video signal with the blanking space set in this way (hereinafter referred to as TV display signal) is converted into an analog signal and supplied to one input side of the TV/external signal display switching circuit 6.

On the other hand, 7 is an external signal generating device that directly generates RGB signals, such as a character multiplexing adapter, and the adapter 7 is supplied to the other input side of the switching circuit 6 via an interface circuit 8. In this case, the teletext adapter 7 receives the analog signal (video signal) from the tuner/PIF circuit 2 via the interface circuit 8, and extracts the teletext signal inserted in a specific period from this signal. The RGB signals are supplied to the switching circuit 6 via the interface circuit 8 again.

In this way, each input side of the switching circuit 6 is supplied with
The TV display signal and the external signal are selectively switched in the switching circuit 6 according to the display mode switching operation, and are supplied to the picture tube drive circuit 10 at the next stage. The output of the picture tube drive circuit 10 is supplied to the picture tube 11 and displayed. In this case, the external signal is blanked at the timing of the blanking signal generation circuit 5.

[Problems of Background Art] By the way, when a digitized video signal is digitally processed, a circuit delay time occurs between its input and output. This delay time is
Generally, it is said to be 4 to 6 [μs]. standard tv
Since the horizontal period for display is 63.5 [μs],
If the signal from the blanking signal generation circuit 5 is generated ignoring the above delay time, the signal close to the blanking area will also be erased.

Therefore, in the digital TV receiver, the blanking signal is generated in accordance with the delay time of the digital processing circuit 4. i.e. delayed TV
This means that the blanking pulse is controlled to be inserted into the blanking period of the display signal.

However, the blanking signal is generated with respect to the TV display signal, and an external signal having no delay time is blanked with a delay time of the TV display signal. Therefore, when displaying an external signal, a part of the signal to be displayed is erased.

As described above, in conventional digital TV receivers, the delay time in the digital processing process of TV display signals has been an obstacle in displaying external signals at the TV display timing.

[Purpose of the invention] This invention was made in view of the above circumstances.
To provide a digital television receiver which supplies an appropriate blanking signal even to signals from an external signal generating device, and which does not cause screen defects when displaying external signals.

[Summary of the invention] In order to achieve the above object, a digital TV receiver according to the invention is capable of displaying a second video signal from an external device in addition to the first video signal from the tuner, and In a digital television receiver having a processing circuit for digitally processing a first video signal, first and second horizontal blanking are synchronized with an input phase and an output phase of the first video signal in the processing circuit. and selecting the first and second horizontal blanking signals in response to a display mode such that in the display mode of the first video signal, the second blanking signal is the second horizontal blanking signal; In the video signal display mode, the blanking period of each video signal is controlled by the first blanking signal.

[Embodiments of the invention] The present invention will be specifically described below with reference to illustrated embodiments.

Here, Figure 1 shows the digital TV according to the present invention.
FIG. 2 is a block diagram showing an overview of the receiver, FIG. 2 is a circuit diagram showing an example of a horizontal blanking signal selection circuit, and FIG. 3 is a timing chart for explaining the operation of the present invention.

In FIG. 1, the same parts as in FIG.
It is a PIF circuit, and before it undergoes digital processing.
TV display signal a is derived. 3 is a buffer circuit for the next stage digital processing circuit 4;
The signal b processed by the digital processing circuit 4 is
It is supplied to the TV/external signal switching circuit 6. Further, as an external signal generating device, for example, a character multiplexing adapter 7 derives its external signal e to the switching circuit 6 via an interface circuit 8.

On the other hand, 12 is a blanking signal generation circuit, and this signal generation circuit 12 generates a horizontal blanking signal c synchronized with the phase of the TV display signal a which has not passed through the digital processing circuit 4, and a phase of the digitally processed signal b. A synchronized horizontal blanking signal d is generated respectively. These horizontal blanking signals c and d are selectively applied to the digital processing circuit 4 via a signal selection circuit 13. This signal selection circuit 13 is supplied with a display control signal corresponding to the display of the external signal e supplied to the switching circuit 6, and selects the horizontal blanking signals c and d based on this signal. I can do it.

FIG. 2 shows an example of the signal selection circuit 13, and the configurations of its peripheral parts are denoted by the same reference numerals. However, since the display controller signal is originally generated by the interface circuit 8, this figure shows it as being supplied to the signal selection circuit 13 from the interface circuit 8. More specifically, the blanking signal generation circuit 12
The two horizontal blanking signals c and d from are supplied to the bases of a pair of transistors Q ₁ and Q ₂ through diodes D ₁ and D ₂ , respectively.
The collectors of these transistors Q ₁ and Q ₂ are connected to the power supply terminal V ₁ . The emitters are each connected to a ground terminal via _R1 , and output a control output to the digital processing circuit 4.
Further, a bias based on the power supply terminal V ₁ is applied to the base of each transistor Q ₁ and Q ₂ via resistors R ₂ and R ₃ , respectively, and the base of transistor Q ₁ is connected to the collector of transistor Q ₃ .
The base of transistor Q ₂ is connected to the collector of transistor Q ₄ via a diode D ₃ .
Each of these transistors Q ₃ and Q ₄ is a transistor
The collector output of _Q4 drives transistor _Q3 , and the collector of transistor _Q4 is connected to the base of transistor _Q3 via resistor _R4 , and each emitter is connected to the ground terminal. ing. In addition, the transistor _Q4 in the previous stage is
Its collector is connected to the power supply terminal _V2 via a resistor _R5 , and a display control signal from the interface circuit 8 is supplied to the base.

According to the above configuration, the two horizontal blanking signals c and d generated from the blanking signal generation circuit 12 have the phase of the TV display signal a on the input side of the digital processing circuit 4 having a predetermined delay time, and on the output side of the same circuit 4.
They are each synchronized with the phase of TV display signal b.
These timings are as shown in FIG.

In Fig. 3, a to e are the TVs explained in Fig. 1.
The signal periods of display signals a, b, horizontal blanking signals c, d, and external signal e are shown, respectively. Further, the symbol To indicates one horizontal scanning period, and τ indicates the delay time of the digital processing circuit 4. As is clear from the figure, the signal period of the external signal e starts a certain period after the back porch of the horizontal synchronizing signal of the TV display signal a before digital processing, and starts a certain period before the front porch of the next horizontal synchronizing signal. It's finished. In other words, TV display signal a
The signal period of the external signal e matches the signal period of the external signal e. In addition, the TV display signal b after digital processing
The blanking period coincides with the phase of the horizontal blanking signal d.

Therefore, by driving the signal selection 13 with the display control signal f responsive to the display operation of the external signal e, the horizontal blanking signal c is set to the horizontal blanking signal c in the display mode of the external signal e, and the horizontal blanking signal c is set to the horizontal blanking signal c in the display mode of the TV display signal a. Each ranking signal d can be supplied to the digital processing circuit 4. This makes it possible to perform blanking in synchronization with the phase of the signal in each display mode.

To explain an example of the selection operation of the horizontal blanking signals c and d as described above using the circuit of FIG. 2, first, the display control signal exhibits a high level in the display mode of the external signal e, and It is assumed that the signal exhibits a low level in the display mode of the display signal a. When this display control signal is at high level, transistor _Q4 is turned on and its collector output is at low level. This low level signal turns on diode _D3 , lowers the anode level of diode _D2 and the base level of transistor _Q2 , and turns off diode _D2 and transistor _Q2 . Therefore, the horizontal blanking signal d being supplied to the cathode of the diode _D2 is no longer supplied to the digital processing circuit 4. On the other hand, the next stage transistor _Q3 is turned off by the collector output of the transistor _Q4 , and the cathode level of the diode _D1 and the base level of the transistor _Q1 are raised to approximately the level of the power supply terminal _V1 by the resistor _R2 . Therefore, the horizontal blanking signal c is supplied to the digital processing circuit 4 through the diode _D1 and the transistor _Q1 .

Next, in the display mode of the TV display signal,
In contrast to the above, since the display control signal f is at a low level, the collector output level of the transistor _Q4 is at a high level, and the collector output level of the transistor _Q3 is at a low level. Therefore, the diode D ₁ and the transistor Q ₁ are turned off, and the horizontal blanking signal c is no longer supplied to the digital processing circuit 4. On the other hand, diode D ₃
is in the off state, so the transistor Q ₂ and the diode D ₂ are in the on state, and the horizontal blanking signal d is supplied to the digital processing circuit 4.

In this way, the present invention enables accurate blanking of both the tuner signal and the external signal in a digital TV receiver that has the function of displaying signals from an external signal generating device. .

[Effects of the invention] As explained above, according to the invention, a horizontal blanking signal synchronized with the phase of the signal delayed by the digital processing circuit and a horizontal blanking signal synchronized with the phase of the signal before being delayed are generated. Since the display mode is selected between the signal display mode from the tuner and the display mode of the external signal, it is possible to prevent the display signal from being missing due to the delay time of the digital processing circuit.
Digital with external signal display function with high commercial value
TV receivers can be provided.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the digital TV receiver according to the present invention, Fig. 2 is a circuit diagram showing an example of the signal selection circuit in Fig. 1, and Fig. 3 explains the operation of the present invention. FIG. 4 is a block diagram schematically showing a conventional digital TV receiver. 2... tuner/intermediate frequency amplification/detection circuit, 4...
...Digital processing circuit, 6...T/external signal switching circuit, 7...Character multiplex adapter, 8...Interface circuit, 12...Blanking signal generation circuit, 13...Signal selection circuit, Q ₁ to Q ₄ ...transistor, D ₁ - _{D 2} ... diode, R ₁ - _{R 5} ... resistance.

Claims (1)

[Claims for Utility Model Registration] A processing circuit capable of displaying a second video signal from an external device in addition to the first video signal from the tuner, and digitally processing the first video signal. a digital television receiver having: means for generating first and second horizontal blanking signals synchronized with the input phase and output phase of the first video signal in the processing circuit; A first and a second horizontal blanking signal can be selected depending on the display mode, and in the display mode of the first video signal, the second horizontal blanking signal
and means for controlling the blanking period of each video signal using the first blanking signal in the display mode of the second video signal.