JPH0352066A - Block data nullification processing system - Google Patents

Abstract

PURPOSE:To curtail the hardware quantity and to simplify its control by providing a means for generating a first nullification block address group, and a means for generating a second nullification block address group. CONSTITUTION:In a nullification block address generating means 8, from a vector store start address (B), a vector store end address (B+D*L), and an inter-vector store element distance (D) which are received, for instance, a nullification address (X) = (B, B+D, B+2D,...), and a nullification address (Y) = (B+D*L, B+D*L-D, B+D+L-2D,...) are generated. Also, a nullification block address corresponding to block data registered in a buffer storage means 4 is generated, and sent out to an address check means 9 and a nullification processing means 10. In such a way, the hardware is curtailed and the control is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a block data invalidation processing method, and more particularly to a method for invalidating data copies of main memory stored in a buffer storage device.

BACKGROUND ART Conventionally, in data invalidation processing of this type of buffer storage device, data on the main storage device is rewritten by a vector store request from a vector processing means, and a copy of that data is stored in blocks. Since the block data in the buffer storage device becomes invalid, this was done to guarantee the data in the buffer storage device against subsequent scalar load requests.

Invalidation processing methods at this time include a control method that invalidates all valid block data existing in the buffer storage device when a vector store request is executed, and a control method that invalidates all valid block data existing in the buffer storage device when a vector store request is executed.
B). The invalidation address (B, B
+D, B+2D, . . . , B+DL) and use each to perform invalidation processing in block units.

During these processes, in order to speed up the processing of subsequent scalar load instructions, a vector store area indicated by the vector store instruction is created and maintained, and when the address of the subsequent scalar load instruction to this area is checked, that area is If it is within the area, the scalar instruction is inhibited from accessing the buffer storage and is controlled to directly access the main storage.

Furthermore, in order to speed up the invalidation process, it is possible to have a copy of the tag part of the buffer storage device and use that copy to index the invalidation address, or to have multiple copies and create multiple invalidation addresses at the same time. They are trying to deal with it by coercing them.

For example, to explain using FIG. 3 as an example, a vector store instruction is issued, and the vector store start address (B
), the distance between vector store elements (D), and the number of vector store elements (L) are held in B register a, D register b, and L register C, respectively.

First, in this configuration, a vector store area is created in order to speed up subsequent scalar load instructions. The contents of B register a are set and held in area start register g, and are input to adder h via selector n.

On the other hand, the contents of D register b are input to multiplier d together with the contents of L register C, and the multiplication result (D*L) is input to adder h via selector e.

The adder h calculates the addition result (B
+D*L) is obtained, which is set and held in the area end register f. As a result, the vector store area (B-B+D*L) has been fully utilized. Subsequently, in order to create an invalidation address (this is an example of creating addresses of four elements at a time to create invalidation addresses/accelerate indexing), register B is added to adder h again. At the same time, the contents of D register b are input as D to adder h via selector e.

Adder h extracts the invalidation address (X) from the above two data.
Discipline (-B+D). Subsequently, the adder h selects the self-addition result (X) as an input via the selector n, performs addition with D again, and invalidates the address (Y) (-B+2D>
Create. In the same way, invalidate address (Z) (-B+
3D) is created.

The contents of B register a are used for the invalidation address (W) (-B). The invalidating addresses (W-Z) are respectively input to adders (j-m) as start addresses for generating invalidating addresses.

On the other hand, D from D register b is shifted 2 bits to the left in shift circuit i to become 4D, and the adder (
j-m). Addition is performed in each adder (j-rn), but from the second addition, the self-addition results are inputted through the selectors (O~') and addition is performed, and L/4 additions are performed. is performed, and the creation of the invalidation address is completed.

By this operation, the invalidation address (W
) − (B, B+4D, B+8D, . . . ) is the invalidation address (X) − (B+D, B+5
D, B+9D, .
) is the invalidating address (Z)− from the addition means m.
(B+3D, B+7D, B+11D, . . . ) are output as invalidation addresses (W-Z), respectively.

Furthermore, by having multiple sets (for example, four sets) of adders, the same invalidation address as described above is created.
, B+D, B+2D, B+3D, etc., and then repeat adding 4D to each address.

Conventional invalidation processing speeds up the processing of subsequent scalar instructions as described above, has multiple copies of the tag part of the buffer storage means, and creates multiple sets of invalidation addresses. This method creates a vector store area (B-B+D) to speed up the processing of subsequent scalar instructions.
*L) and the start address for invalidation address control (for example, B, B+D, B+2D, B+3D), the drawback of having separate adders is that the amount of l\-ware increases. be. One possibility is to use a common nasal inflator to reduce the amount of hardware, but this has the disadvantage of complicating its control.

OBJECTS OF THE INVENTION An object of the present invention is to provide a block data invalidation processing method that can reduce the amount of hardware and simplify its control.

Structure of the Invention According to the present invention, a main memory means, a buffer memory means for storing a copy of data in the main memory means in units of blocks,
block data of an information processing apparatus, including means for invalidating block data existing in the buffer storage means corresponding to data in the main storage means rewritten by a vector store request issued to the main storage means; The invalidation processing method includes: means ε for determining an end address of the vector store request using a vector store start address, the number of vector store elements, and a distance between vector store elements of the vector store request; A first invalidation block address group for invalidating block data in the buffer storage means corresponding to data rewritten by the vector store request is generated by adding the inter-element distance and the vector start address. and a second means for invalidating block data in the buffer storage means corresponding to data rewritten by the vector store request by subtracting the distance between the vector elements and the vector store end address. means for generating a group of invalidated block addresses; and means for detecting that the address value of the first group of invalidated block addresses reaches the address value of the second group of invalidated block addresses and generates a detection signal. and invalidating corresponding block data in the buffer storage means according to the first and second invalidation block address groups until generation of this detection signal. can get.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a system configuration diagram of an embodiment of the present invention. A scalar load request issued from the scalar processing means 2 is sent to the buffer storage means 4 via the scalar request line 108. The buffer storage means 4 returns the corresponding data to the scalar processing means 2 via the scalar data line 109 if the corresponding data exists.

Conversely, if the corresponding block data does not exist, a block data transfer request is output to the main memory means 3 via the main memory access line 113, and the block data is transferred from the main memory means 3 to the main memory. The data is returned to the buffer storage means 4 and registered via the data line 114, and only the corresponding data is returned to the scalar processing means via the scalar data line 109.

On the other hand, a vector load request from the vector processing means 1 is sent to the main storage means 3 via the vector request line 101, and the corresponding data is sent back to the vector processing means 1 via the vector data line 102.

In the case of a vector store request, the vector store request is issued to the main storage means 3 via the vector request line 101, and the store data is transferred to the main storage means 3 via the vector data line 102. At this time, the address information of the vector store request is transferred to the address information holding means 5 via the vector address information line 100 to ensure data in the buffer storage means 4.

The vector address information sent to the address information holding means 5, namely the vector store start address (B), the distance between vector store elements (D), the number of vector store elements (
Among L), the vector store inter-element distance (D) is transmitted via the inter-element distance information line 103, and the vector store start address (B) is transmitted via the start address information line 104 to the invalidation block address creation means 8. supplied to Furthermore, all of this vector address information is sent to the end address creation means 7 via the vector address information line 10B.

The end address creation means 7 multiplies the distance between the received vector address elements (D) and the number of vector store elements (L), and uses the result and the vector store start address CB.
) are added to create the store address (B+D*L) of the final store data according to the vector store request.

This is the end address information line 10 as a vector address.
5 to the invalidation block address creation means 8.

The invalidation block address creation means 8 generates, for example, the invalidation address (X) - from the received vector store start address (B), vector store end address (B+D*L), and distance between vector store elements (D). (B
, B+D, B+2D,...), invalidation address (Y)
- (B+D*L, B+D*L-D, B+D+L-2D
,...) are created, and an invalidation block address corresponding to the block address of the block data registered in the buffer storage means 4 is created, and the invalidation block address is sent to the address check means 9 and the invalidation block address via the invalidation block address line 110. It is sent to the processing means 10.

The address check means 9 compares the received invalidation block addresses, and if X and Y are detected, an instruction to terminate the invalidation process is issued via the termination signal line tti.

The invalidation processing means 10 performs invalidation processing on the block data when corresponding block data exists in the buffer storage means 4 based on the invalidation block address, and receives a termination instruction from the address checking means 9. Continue the process until.

Furthermore, an explanation will be added using FIG. As shown in FIG. 2, let us take as an example the case where four invalidation block addresses are created at once. First, B existing in the address information holding means 5
The vector store start address (B), the distance between vector store elements M (D), and the number of vector store elements (L) are set in the register 11, the D register 13, and the L register 12, respectively.

Next, in order to speed up the processing of subsequent scalar load instructions, B is manually held in the start address register 6 via the B data line 115, and is roughly transferred from the L register 12, D register 13 to the L data line 1l6, (L) and (D) are input to the multiplier 15 via the D data line li7, and the multiplication result (
D*L) is output.

This output is sent to the B data line 11 via the DL data line 11g.
It is input to the adder 14 together with (B) sent through the input terminal 5, and addition is performed. The result of this addition is input and held in the address register 16 via the end address line 119 as the vector store end address. This creates a vector store area, making it possible to speed up subsequent scalar load instructions.

Next, to create an invalidation address, the vector store start address (B) and vector store end address (B+D*L) obtained in the above operation are input as initial addresses to the adding means 22 to 25. At the same time, D sent from the D register 13 is once input to the conversion circuit 17, and in this circuit, ゜0'' is input to the addition means 22 and the subtraction means 24 as initial address addition/subtraction data.
3. "D" is connected to the subtraction means 25 from the data lines 124 to 3, respectively.
125.

The addition means 22 and 23 perform addition, and the subtraction means 24 and 25 perform subtraction, so that B, B+D, and B+ are respectively obtained.
DL-D, B+DL is used as the start address for creating an invalidation address, and a part of it is used as an invalidation block address on the invalidation block address lines 120 to 12.
3 to the invalidation processing means 10 and further to the address checking means 9.

When all start addresses are obtained, 2D is sent from the conversion circuit 17 as address addition/subtraction data, and the selection circuits 18 to 21 select the addition means 22.
23. By controlling the subtracting means 24.25 to input its own addition/subtraction results, the invalidation address is set as (W)-(B, B+2D, B+4D,...), (X
)-(B+D, B+3D, B+5D,...). (Y)
-(B+D*L-D, B+D*L-3D, B+I)kL
−5D, ・), (Z)− (B+D*L, B+D*L
-2D, B+D*L-4D,...).

The creation of this address is terminated when, for example, (X)k (Y) is detected in the address checking means 9.

Effects of the Invention According to the present invention, D and 2D can be added to the start address of the vector store area, and D and 2D can be added to the end address of the vector store area.
, 2D, it is possible to create an invalidation block address without performing any special address calculations (for example, 3D calculations), reducing hardware and simplifying @control. There is an effect.

[Brief explanation of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a specific example of a portion of the blocks in FIG. 1, and FIG. 3 is a block diagram showing a conventional technique. Explanation of symbols of main parts 3...Main storage means 4...Buffer storage means 5...Address information holding means 7...End address creation means 8 ...Invalidation block address creation means 9...
... Address check means 0 ... Invalidation processing means

Claims (1)

[Claims] (1) A main memory means, a buffer memory means for storing a copy of the data in the main memory means in block units, and an internal memory of the main memory means that is rewritten by a vector store request issued to the main memory means. a block data invalidation processing method of an information processing apparatus, the block data invalidation processing method of the information processing device including means for invalidating block data existing in the buffer storage means corresponding to data of the vector store request, the vector store start address of the vector store request, the number of vector store elements. and a means for generating an end address of the vector store request using the distance between the vector store elements, and an addition process of the distance between the vector elements and the vector start address to correspond to the data rewritten by the vector store request. means for generating a first invalidation block address group for invalidating the block data in the buffer storage means, and a subtraction process between the vector element distance and the vector store end address. means for generating a second invalidation block address group for invalidating the block data in the buffer storage means corresponding to the data rewritten by the above, and an address value of the first invalidation block address group is means for detecting that the address value of the second invalidation block address group has been reached and generating a detection signal, and until the generation of this detection signal,
A block data invalidation processing method, characterized in that corresponding block data in the buffer storage means is invalidated according to the first and second invalidation block address groups.