JPH0352076B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a CRT display capable of scrolling and displaying data in a video memory on a CRT.

(b) Prior Art and Problems First, Figure 1 shows an example of the configuration of a CRT display. In FIG. 1, 1 is a CRT display controller, 2 is a video memory, 3 is a character generator, 4 is a shift register, and 5 is a CRT.

The bus 6 transfers the line counter output from the CRT display controller 1 to the character generator 3.

The video memory 2 receives a video memory address via a bus 7, video memory data via a bus 8, and a video memory write signal via a signal line 9.

Then, the video memory 2 outputs the data stored in the video memory 2 to the character generator 3 through the bus 10.

The character generator 3 generates a character pattern from the video memory data from the video memory 2 and the line counter output via the bus 6, and sends it to the shift register 4 via the bus 11.

The shift register 4 converts the character pattern received as a parallel signal into a serial signal in synchronization with the bit clock through the signal line 13 and sends it to the CRT 5.
Then, the bright spot on the CRT 5 is made to shine brightly with a logic "1" and dimmed with a logic "0".

Next, an example of the display on the CRT5 will be shown in the second section.
As shown in the figure.

FIG. 2 shows a state in which the contents of the video memory 2 from address "0" to address "2" are displayed on the CRT 5. In order to display new information on the CRT 5, set the video memory address from the CRT display controller 1 to "1" to "3".
The number increases sequentially, such as from "2" to "4". As a result, the image displayed on the CRT 5 in FIG. 2 moves upward, creating an empty area at the bottom of the screen of the CRT 5. The contents of addresses "3" and "4" of the video memory 2, which are new information, are displayed in this empty area.

FIG. 2 shows an example in which the video memory 2 is large enough to store ²³ words of data from addresses "0" to "7".

In Figure 2, "5" to "7" of video memory 2 are
When displayed on the CRT 5, when the next video memory address comes, it is necessary to display the contents of "6" to "8" on the CRT 5.

However, in the example shown in Figure 2, the capacity of video memory 2 is
2 Since there are only ³ words, CRT for "6" to "8"
There is no video memory at address ``8'' above 5, and data cannot be displayed.

In order to display the data at the first address "0" after address "7" in such a state, conventionally, data "0" to "7" were displayed after address "8" in the video memory 2.
Measures are taken such as having a video memory that stores the contents of the video in duplicate.

(c) Purpose of the Invention This invention allows the contents of the video memory 2 to be transferred to a CRT without having to store data redundantly in the video memory 2.
The present invention provides a CRT display that can be displayed while scrolling upward.

(d) Embodiment of the invention First, the configuration diagram of the embodiment of this invention is shown in the third example.
As shown in the figure.

FIG. 3 is a diagram showing the relationship between the CRT display controller 1 and the video memory 2 shown in FIG. 1 in more detail.

In FIG. 3, a decoder 14 is connected between the CRT display controller 1 and the video memory 2.

This decoder 14 is included in the video memory 2 and is often not shown in the block diagram as shown in FIG. 1, but is specifically shown for clarity of content.

The video memory address by bus 7 in FIG.
It consists of m bits. FIG. 3 shows an example where m=6, and the bus 7 in FIG. 1 is represented by 6-bit signals on signal lines 71 to 76 in FIG.

Since the capacity of the video memory 2 is ²³ words, the input of the video memory 2 includes 3-bit terminals 21 to 23 as address inputs. Signal lines 71 to 73 are connected to these terminals 21 to 23, respectively, to transmit the video address output from the CRT display controller 1 to the video memory 2.

In addition to this, a selection signal via a signal line 15 is input to a terminal 24 of the video memory 2 .

When the selection signal from the signal line 15 is logic "0", the video memory 2 does not output a signal to the bus 10, and when the selection signal is logic "1", the contents of the video memory 2 specified by the address input are transferred to the bus 10. 1
Output to 0.

The selection signal is an output signal of the decoder 14, and the decoder 14 operates by receiving signals from signal lines 75 and 76 as input.

In the embodiment of FIG. 3, when the logical values of the signals on the signal lines 75 and 76 are both "0", the decoder 1
4 outputs a logical value "1".

Each signal from signal lines 71 to 76 is ²⁰
It has a value expressed as a binary code with a weight of 2 ⁵ .

Next, FIG. 4 shows the values of the signals via the signal lines 71 to 76, the selection signal, the video memory address input, and the state of the bus 10.

Note that since it is difficult to understand if the video memory address line and the video memory address input are displayed in binary code, they are shown in octal notation in FIG.

In this invention, when the capacity of the video memory 2 is set to 2 ⁿ words, the (n+1)th bit of the video memory address is not decoded, and the case where n=3 will be explained as an example.

The relationship between each signal on the signal lines 76 to 71 in FIG. 3 and the video memory address input is as shown in FIG. 4.

Signal lines 76 to 71 in Figure 4 are "00" to "07"
Up to the address, each signal on the signal lines 74 to 76 is logic "0". Therefore, the output of the decoder 14 receiving the signals from the signal line 75 and the signal line 76 becomes a logic "1", and the selection signal on the signal line 15 becomes a logic "1".

When the logical value of the selection signal becomes "1", the address input of video memory 2 becomes valid, and video memory 2
The contents of addresses "0" to "7" are output to the bus 10, and the data in the video memory 2 is displayed on the CRT 5.

For the signal lines 76 to 71 from addresses "10" to "17", the logic value of the signal line 74 = "1", the logic value of the signal line 75 = "0", and the logic value of the signal line 76 = "0". be.

Since the signal line 74 corresponding to the (n+1)th bit is not connected anywhere, address values "0" to "7" are input to the address input of the video memory 2, as shown in FIG.

On the other hand, a signal line 75 and a signal line 76 are connected to the input of the decoder 14, and the logical value of these signals is "0", so the output of the decoder 14, that is, the logical value of the selection signal is "1". Become. Therefore, the contents of the video memory 2 from addresses "0" to "7" are output to the bus 10.

The information output to the bus 10 has exactly the same content as in the case where the video memory addresses are from "00" to "07" described above.

If the video memory address is "20" or higher,
Since one or both of the logical values of the signal line 75 and the signal line 76 are "1", the selection signal by the signal line 15 is always a logic "0", and the signal from the video memory 2 is output to the bus 10. It will not be done.

In this way, according to the configuration in FIG. 3, the configuration in FIG.
Since data at address "0" is displayed next to address "7" on the CRT 5, the contents of the video memory 2 are displayed while being scrolled.

(e) Effects of the Invention According to this invention, when the video memory stores 2 ⁿ bits of data, the n+1th bit of the video memory address is not decoded, so that no data is duplicated in the video memory. The contents of the video memory can be scrolled and displayed on the CRT without having to store the data.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a CRT display, FIG. 2 is a diagram showing an example of a display on the CRT5 in FIG. 1, and FIG. 3 is a configuration diagram of an embodiment according to the present invention.
FIG. 4 is a diagram showing the relationship between each signal on the signal lines 76 to 71 and the address of the video memory. 1...CRT display controller, 2...
...Video memory, 3...Character generator,
4...Shift register, 5...CRT, 6-8...
...Bus, 9...Signal line, 10...Bus, 11...
Bus, 12, 13...Signal line, 14...Decoder, 15...Signal line, 21-24...Terminal, 71
~76...Signal line.

Claims (1)

[Scope of Claims] 1. A CRT display comprising a CRT display controller that outputs a video memory address, and a video memory that receives the video memory address as an input and outputs video memory data, wherein the video memory stores ²ⁿ bits of data. 2. A CRT display according to claim 1, wherein the CRT display is configured such that the (n+1)th bit of the video memory address from the CRT display controller is not decoded when the video memory address is stored.