JPH0352200A - Test system for semiconductor storage device - Google Patents

Abstract

PURPOSE:To apply the tester of an I/O individual processing system by inputting write data from one arbitrary input/output terminal, discriminating all data which are read into an input/output line and outputting them in a semiconductor memory which attains access in plural bit unit. CONSTITUTION:In writing in a test mode, only an input/output circuit IOB0 corresponding to one input/output terminal D0 comes to an operation state, and the other circuits IOB1-IOB3 are set to be a non-operation state. Input data from the terminal D0 are simultaneously written as against the selected memory cell of respective memory mats M0-M3. On the other hand, data which are read from the memory mats M0-M3 are transmitted to a test circuit TST, and coincidence/dissidence is decided. The result is transmitted to all the circuits IOB0-IOB3, and are outputted from the terminals D0-D3. Thus, the result can be selected by using a tester corresponding to an I/O processing or an individual processing by the test system.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a test method for semiconductor memory devices, and is an effective technique that can be used, for example, in a test method for a dynamic RAM in which memory access is performed in units of multiple bits. It is related to.

[Conventional technology]

As the storage capacity of semiconductor memory devices increases, the testing (selection) time increases. Dynamink type RAM
In this example, since the capacity is quadrupled for each beam generation, the sorting time simply increases four times for each generation. A test function provided in such a DRAM, which has a large storage capacity, shortens the selection time by selecting and processing a plurality of memory cells at the same time. Regarding the write operation, input data is simultaneously written into a plurality of memory cells.

In the read operation, since it is not possible to output multiple bits of data at the same time, an internal judgment circuit (test circuit) is provided, and in the binary judgment method, when all data match, it is a high level, and when it is a mismatch, it is a low level. . In the three-value determination method, when all data are high level and match, the level is high; when all data is low level and there is a loss, the level is low; when there is no match, the output is set to high impedance.

Among the approximately 4 Mbit dynamic RAMs currently under consideration, the test method for those in which memory access is performed in units of 4 bits is to simultaneously process 8 bits, 2 bits from each input/output terminal. Method (I/
O bulk method) and each 1/O individually (2 bits each)
There are two methods: a method in which simultaneous processing is performed (1/○ individual method), and a method in which processing is performed simultaneously.

The above-mentioned I/O batch processing method simultaneously processes all data of each I/O, so the number of processed data (number of bits) is large, and the reliability of the judgment value is accordingly high. However, on the other hand, there is a disadvantage that the test cannot be determined for each I/O.

In the above individual I/O method, data is processed simultaneously for each 1/0, so the number of processed data is small and the reliability of the judgment value is low, but it is possible to test and judge each 1/0 separately. . However, since it is for each I/O, it is necessary to perform AND processing externally (such as a tester) when considering all bits. This type of I/O batch processing method is based on the 4M focus Dyna-Fuku type RA announced by Hitachi.
There is M (HM5 1 4 4 0 0R), ■/○
As for the individual system, there is a 4 Mbit dynamic RAM announced by Mitsubishi Electric.

[Problem to be solved by the invention]

When the test methods are different in this way, it is necessary to change the configuration of the tester used.

This is because when inputting (writing) data, I/O
Testers that support the batch processing method have only one input pin, so dynamic RA that uses the I/O individual processing method
When used for M, one I/
Data is input only to the O terminal. In addition, regarding the output (judgment value), a tester that supports the I/O batch processing method is used as a dynamic type RA that supports the I/O individual processing method.
If used for M, AND processing cannot be performed and all fail.
IL). The reason for this is that in the I/O batch processing method,
Output is only one of any I/O bin, other I/O
This is because nothing is output to the O bin.

An object of the present invention is to provide a new semiconductor memory 4fi device testing method that basically adopts the I/O batch processing method, but is also compatible with a tester using the I/O individual processing method.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, in a semiconductor memory device where memory access is performed in units of multiple bits, write data is input from any one output terminal among multiple input/output terminals, and read out to the input/output line by an internal test circuit. At the same time, the judgment results are output from all the input/output terminals mentioned above. [Operation] According to the above-mentioned means, the same judgment result is output from all input/output terminals, so it can be applied as is to a tester using the I/O individual processing method that performs AND processing on all input/output terminals. .

〔Example〕

FIG. 1 shows a schematic block diagram of an embodiment of a dynamic RAM for explaining test method 2 according to the present invention. In the figure, only signal paths focusing on the test mode are shown to facilitate understanding of the test method according to the present invention.

Since the dynamic RAM of this embodiment performs memory access in units of x4 bits, it is basically excluded from the four memory mats M O -M3.

Input/output circuits 10BO to 10B3 are provided corresponding to the memory mats MO to M3. Terminals DO to D3 provided corresponding to these input/output circuits IOBO to rOB3 are input/output terminals.

When writing in the test mode, only the input circuit of the input/output circuit IOBO corresponding to one human output terminal DO among the input/output circuits IOBO to IOB3 becomes operational.
The other output circuits IOBI to tOB3 are left inactive. As a result, of the terminals DO to D3, only the data from the terminal DO is made valid and taken into the device, and the data from the other terminals DI to D3 are made invalid. The data inputted from the terminal DO is simultaneously written into selected memory cells of each of the memory cells MO to M3. In the figure, the data from the terminal DO is shown to be transmitted to the four memory mantles MO to M3 through the internally provided test circuit TST, but in reality, there is no substantial relationship with the test circuit. The same data is transmitted to the four memory mantles as a write signal by simultaneously selecting selectors which will be described later.

On the other hand, the data read from each memory mat MO to M3 is transmitted to a test circuit TST, where a match/mismatch determination is made.

The judgment result determined by this test circuit TST is transmitted to all of the four input/output circuits IOBO to TOB3. From this, the same determination result will be output from the terminals Do to D3.

In a write operation, in the conventional I/O batch processing method, data input from any one of the terminals, for example DO, is simultaneously written to all memory mants MO to M3. Therefore, in this respect, a device to which the test method of this embodiment is applied can perform writing in the same way as the I/O batch processing method. On the other hand, in the conventional I/O individual processing method, data is written independently from all terminals pO to D3. However, for the device to which the test method of this embodiment is applied, the above I/O
Even if data is input as in the individual processing method, the data input from one terminal is valid and the data input from the other three terminals are invalid, so the write operation can be performed without any apparent problem. It is something that can be done.

In the output of the judgment value, in the conventional I/O batch processing type device, the remaining three terminals DI to D3, excluding one terminal DO used as an input terminal, are used as input terminals.
Among them, the pass/fail determination result is output from one terminal D3 or the like. In the test method of this embodiment, the above judgment results are output to all four terminals DO to D3, but a tester compatible with the above I/O batch processing method does not have a function to accept the remaining three judgment results. . As a result, in a tester compatible with the I/O batch processing method, the remaining three determination results are invalidated, so that the determination results of the device adopting the test method according to the present invention can be processed without any problem. On the other hand, in the conventional I/O individual processing type device, the determination result corresponding to each memory cloak MO to M3 is outputted from the terminals DO to D3 through the respective input/output circuits 10BO to IOB3. Therefore, the determination results output from the terminals Do to D3 are subjected to AND processing on the tester side to obtain the final determination results. In the test method of this embodiment, the same determination result is output to all four terminals Do to D3. Therefore, I/
The same result can be obtained even if AND processing is performed on a tester using O individual processing method.

As a result, devices adopting the test method according to the present invention can be subjected to screening tests with either a tester compatible with the conventional I/O batch processing method or a tester compatible with the I/O individual processing method. Become what you can.

FIG. 2 shows a block diagram of an embodiment of a dynamic RAM employing the test method according to the present invention.

This embodiment is directed to a dynamic RAM of about 4 Mbits, although it is not particularly limited. In this example, by using the master slice method,
Switching between 1-bit configurations is possible. Therefore, the human output circuit is connected to terminal Do in order to correspond to ×4 bin configuration.
Four circuits 10B (l to IO) corresponding to D3 to D3
B3 is provided. In addition, in the ×1 bift ti, since the input circuit and the output circuit are separated, an output circuit DOB and an output terminal Dout corresponding to the output circuit DOB are provided. One of the four input/output circuits 10BO to I○B3 is used as an input circuit. The memory mats are each configured to have a storage capacity of approximately IM bits. Each is divided into four memory arrays for high-speed read operations, etc. That is, one memory mantle is composed of, for example, memory arrays MOO to MO3. Therefore, one memory array is approximately 256K
It has a storage capacity of bits. Memory array M
00, Mol and MO2. MO3 is an X address decoder. It is divided into drivers XDC and DVQ. As a result, the number of memory cells connected to one word line is halved (1024), making it possible to speed up the word line selection operation. The above X address decoder. Driver XDC, DVO
The memory cloak is divided into upper and lower parts and arranged as shown above, with . The memory array is divided into left and right such as M00 and Mol, and MO2 and MO3. This reduces the number of memory cells coupled to one complementary data line (bit line or digit line) by half (256), reduces its parasitic capacitance, and effectively reduces the level of the read signal from the memory cell. It's getting bigger. The memory arrays MOO and MOI or MO2 and MO3 divided into left and right sides are each provided with two pairs of input/output lines. Therefore, it is possible to read and write data in units of 2 bits from one memory array. Of the above two pairs of input/output lines, one of the input/output lines is crossed and sent to the first selectors SLIO and SLII.
is input into . This first selector SLIO and SLII
is alternatively brought into a selected state by an X-system address signal A9 or the like.

As a result, the 2-bit read signal is amplified by the two main amplifiers MAO and MAI. The output signals of these main amplifiers MAO and MAL are determined by the first test cycle 8TsIO as a match/unmatch jI& judgment output JO,
JO is in full form.

In addition, in normal memory operation with ×4 bit structure,
One of the output signals of the main amplifiers MAO and MAI is selected by the second selector SL20, and is output from the terminal DO via the corresponding input/output circuit 10BO. During a write operation, writing is performed using the opposite signal transmission path. In the case of the x1-bit configuration, the data is outputted through the third selector SL30 selected by the X-system address signal and the Y-system address signal, and through the data output buffer DOB, which is activated at this time. During a write operation, the output signal of the human output circuit IOBO, which operates as an input circuit, is input through one of the third selectors SL30 to SL33.

The memory arrays MIO to M13 to M3Q-M33 corresponding to the other memory mats M1 to M3 are also provided with first selectors SL12, SL13 to SL with the same configuration as above.
l6. SL17, main amp MA2 or MA? , 1st
test circuits TSII to TS13, second selectors SL21 to SL23 and the third selector SL3.
1 to SL33 are provided. In addition, a Y decoder is installed vertically in the center of the two memory mats. Driver YDC,D
V0.1 is provided. The second test circuit TS2 includes individual first test circuits TSO and TSO provided corresponding to each of the memory mantles.
Upon receiving the output signal JO, JO or J3, J3 of S3,
Performs a complete match/non-match judgment operation. This judgment result is sent to each of the input/output circuits 1 through the test judgment selector SLT.
0BO to 10B3 are transmitted to the commonly connected common input/output line. When in test mode, the third selector SL30
L33 is simultaneously brought into a selected state, and the same data input from terminals DO, etc., is transmitted to all memory mats as write signals. In addition, the determination result in the test mode is that the second and third selectors are all in the non-selected state (output high impedance state), and the test determination selectors Sf and T are in the selected state. The judgment output of the test circuit TS2 of
It should be output through B3.

The effects obtained from the above examples are as follows. In other words, (Write data is input from any one input/output terminal of the human output line in the 11X4 bit structure, and the internal test circuit judges all the data read out to the human output line, and the judgment By adopting a configuration in which the results are output from all of the above input/output terminals, selection can be performed using a tester that supports either the conventional I/O batch processing method or the I/O individual processing method. This effect can be obtained.

(2) From (1) above, it is possible to simplify the test aJW.

Although the invention made by the inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. do not have. For example, the semiconductor memory device to which the present invention is applied may be a static type RAM as well as a Guinamisoku type RAM.

Its storage capacity can take various embodiments, such as approximately 4 Mbit {ttl, 1M pinto, or 16 Mbit. Further, it goes without saying that the number of bits to be written/read in parallel may be 8 bits, 1 bits, etc. in addition to 4 bits.

The method for outputting the determination result may be the above-mentioned binary method, ternary method, or other method.

The present invention can be widely used as a test method for semiconductor memory devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, write data is input from any one input/output terminal of a multi-bit configuration such as ×4 bits, and an internal test circuit judges all the data read to the input/output line. At the same time, the judgment results are output from all the input/output terminals mentioned above. As a result, selection can be performed using a tester compatible with either the conventional I/O batch processing method or the I/O individual processing method.

[Brief explanation of drawings]

Fig. i is a schematic diagram showing an embodiment of a dynamic RAM for explaining the test method according to the present invention, and Fig. 2 is an embodiment of a dynamic RAM adopting the test method according to the present invention. FIG.

Claims (1)

[Claims] 1. In a semiconductor memory device in which memory access is performed in units of multiple bits, among a plurality of input/output terminals,
Input write data from any one input/output terminal,
A test method for a semiconductor memory device, characterized in that a test circuit judges all data read out to input/output lines, and outputs the judgment results from all the input/output terminals. 2. The method for testing a semiconductor memory device according to claim 1, wherein the semiconductor memory device is a dynamic RAM. 3. The test circuit includes a first test circuit group that compares and detects a match between signals read out to a pair of input/output lines, and a first test circuit group that receives each output signal of the first test circuit group and compares and detects a match. The semiconductor memory device according to claim 1 or 2, further comprising a second test circuit that detects and forms determination results to be output from all of the input/output terminals. test method.