JPH0352223B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular to manufacturing a semiconductor integrated circuit (IC) consisting of a composite element of a bipolar transistor and a MIS transistor on the same substrate. Regarding the method.

(b) Prior Art and Problems As is well known, ICs are devices in which active elements such as transistors and passive elements such as resistors and capacitors are provided on the same semiconductor substrate to form compact or solid-state electronic circuits. There is. However, the transistor as an active element is a bipolar transistor,
Or, an IC with a structure in which only one of the MIS transistors is used and both transistors are formed on the same substrate has never been manufactured before.

However, now that processes have stabilized and yields have improved, both transistors can be formed on the same substrate.
Considerations have been made to take advantage of this, for example, forming digital processing circuits using MIS transistors, and forming analog processing circuits using bipolar transistors, which have better current drive ability and lower noise than MIS transistors. Logic circuits to form are being manufactured.

An IC made of such a composite element is manufactured by combining the manufacturing processes of both transistors, each of which is formed by a different method, and therefore requires a large number of processing steps and is complex. However, if common steps such as heat treatment are combined as much as possible, the number of steps can be reduced and the yield can be improved.

(c) Purpose of the Invention The present invention proposes a basic manufacturing process for rationally forming an IC composed of such composite elements.

(d) Structure of the Invention The object of the invention is to form at least one of an element isolation band or a collector contact layer in a bipolar transistor formation area on a substrate formed by laminating a semiconductor layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, Next, after forming a gate electrode in the MIS transistor forming area, an oxidation prevention film is selectively provided on the substrate including the gate electrode, and a field silicon oxide film is formed by high temperature oxidation treatment using the oxidation prevention film as a mask. This is achieved by a method for manufacturing a semiconductor device, which includes a step of forming a semiconductor device.

(e) Examples of the invention Hereinafter, examples will be described in detail with reference to the drawings. 1 to 6 are cross-sectional views in order of steps of the manufacturing method according to the present invention.

First, as shown in FIG.
An N ⁺ type buried layer 2 is formed in the bipolar transistor forming area, and an N type silicon layer 3 with a thickness of 2 to 3 μm is epitaxially grown thereon, and a thin silicon dioxide (SiO ₂ ) film 4 is further formed on the upper surface. generate.

Next, as shown in FIG. 2, ions are selectively implanted and heat treated to form a P-type device isolation band 5 and an ^N5- type collector contact layer 6 in the bipolar transistor forming area. At this time, if a CMOS transistor is required, boron ions are implanted into the element isolation zone 5, and then similarly low concentration boron ions are selectively implanted into the P-well region of the MOS transistor formation area, and heat treatment is performed at the same time. You can also do it. Incidentally, all of the above steps are formed by conventionally known methods, but all of these steps require high temperature treatment of 1000° C. or higher.

Next, as shown in Fig. 3, a non-doped polycrystalline silicon film with a thickness of 0.5 μm is deposited by chemical vapor deposition, and then arsenic is ion-implanted into this polycrystalline silicon film (the conditions are an acceleration voltage of 50 keV). , toes amount
10 ¹⁶ /cm ² ), patterning is performed using a photo process to form the gate electrode 7 in the MOS transistor forming area. The reason for depositing a non-doped polycrystalline silicon film and then implanting impurities is that the impurity doping can be done with good uniformity and that the process is easy.

Next, as shown in FIG. 4, a silicon nitride (Si ₃ N ₄ ) film 8 having a thickness of about 1000 Å is deposited by low pressure vapor deposition and patterned. This Si ₃ N ₄ film is an oxidation-preventing film, and the mask portions covered are the areas where the field silicon oxide film is not formed, that is, the base region of the bipolar transistor formation area, the collector conductive layer, the gate electrode and source region of the MIS transistor formation area. , drain region, etc.

Next, as shown in FIG. 5, a field silicon oxide film 9 having a thickness of about 1 μm is formed by high-temperature oxidation treatment. At this time, the gate electrode 7 is heated to a high temperature of about 1000°C, or at the same time, the gate electrode 7 is heated in the above process.
The arsenic implanted into the gate electrode is diffused to define the gate electrode.

Next, as shown in FIG. 6, the P-type base region 10 in the bipolar transistor formation area and the P-type source and drain regions 11 in the MIS transistor formation area are formed simultaneously, and then the shallow emitter region 12 is formed last. Finalize.

If formed in this way, arsenic diffusion into the gate electrode 7 and formation of the field oxide film 9 can be performed in the same high-temperature process. Of course, this is a step in which the base region, source and drain regions are also formed at the same time.

(f) Effect of the invention As is clear from the explanation using the above embodiments,
According to the present invention, since the high-temperature heat treatment step is shortened, factors that cause instability of characteristics are eliminated, and the yield and quality of ICs made of composite elements can be improved.

[Brief explanation of drawings]

1 to 6 are cross-sectional views in order of steps of the manufacturing method according to the present invention. In the figure, indicates the bipolar transistor formation area,
is the MIS transistor formation area, 1 is the P-type silicon substrate, 2 is the buried layer, 3 is the N-type semiconductor layer, and 4 is the N-type semiconductor layer.
SiO ₂ film, 5 is an element isolation band, 6 is a collector contact layer, 7 is a gate electrode (polycrystalline silicon film),
8 is a Si ₃ N ₄ film, 9 is a field oxide silicon film, 10 is a base region, 11 is a source and drain region, and 12 is an emitter region.

Claims (1)

[Claims] 1. For a substrate formed by laminating a semiconductor layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, at least one of an element isolation band or a collector contact layer is formed in a bipolar transistor formation area, and then a gate electrode is formed in an MIS transistor formation area. After forming,
The method includes the step of selectively providing an anti-oxidation film on the substrate including the gate electrode, and forming a field silicon oxide film by high-temperature oxidation treatment using the anti-oxidation film as a mask. A method for manufacturing a semiconductor device.