JPH0352229B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention is directed to field effect transistors (FETs).
This invention relates to a pinhole closing method. Recently, a large number of gate lines (scanning lines) and drain lines (signal lines) are arranged perpendicularly to each other on one substrate of an LCD panel, insulated from each other, and a thin film is placed at the intersection of these lines.
A liquid crystal matrix that displays images on televisions, etc. by disposing FETs (TETs) as switching elements and opening and closing them to apply signals to display electrodes provided at each intersection, driving the display of the liquid crystal in this area. Attempts are being made to develop panels. The present invention particularly relates to FETs used as switching elements in such display panels.

Prior Art Figure 1 shows the overall structure of a matrix panel using FETs as switching elements, in which 1 is a front glass transparent substrate, 2 is a common electrode made of an ITO film deposited on the entire inner surface of this transparent substrate 1, and 3 is a matrix panel using FETs as switching elements. 4 is a liquid crystal layer, and 4 is a spacer made of glass frit, resin, etc., which also functions as a sealant. Reference numeral 5 denotes a rear glass transparent substrate, on the inner surface of which a plurality of gate lines X and drain lines Y (which may also be source lines; the same applies hereinafter) are arranged orthogonally insulated from each other. 6, 6... are amorphous silicon FETs at each intersection of gate line X and drain line Y
The display electrodes are connected through the . It takes
The circuit configuration of one liquid crystal cell in a matrix panel using an FET array is shown in Figure 2. C is a capacitor inserted in parallel with the liquid crystal panel (LCD) as an additional capacitor.

Figures 3, 3A and 3B show one
The specific structure of the FET is shown, and X and Y are the aforementioned gate line and drain line, which are separated by an insulating layer 7. A gate line X and a drain line Y are formed on the surface of the glass substrate 5. The gate G of the FET is formed on the gate line X. An amorphous silicon layer AS is formed above the gate G with an insulating layer 7 interposed therebetween, and a source S and a drain D are formed at both ends thereof so as to sandwich the gate G. A part of the drain line Y also serves as the drain D. Reference numeral 6 denotes the display electrode described above, which is connected to the source S. Normally, the gate line X and display electrode 6 are formed of an ITO film, and the source S and drain line Y are formed of aluminum. Further, as the insulating layer 7, a distilled film of silicon nitride Si ₃ N ₄ formed by a plasma CVD method is used.

In an FET with such a structure, as shown in FIG. 3B, the gate line X and the drain line Y
There is a portion where the two intersect with each other with the insulating layer 7 interposed therebetween.

The number of intersections is the same as the number of pixels; for example, if the number of gate lines X and drain lines Y are 220 and 240, respectively, the number reaches 52,800. Therefore, a small number of these intersections are shot through pinholes formed in the insulating layer 7. Even if this short is only one point, two defective lines, one gate line and one drain line, will be generated, resulting in a large defect in the display.

OBJECTS OF THE INVENTION It is an object of the present invention to prevent shoots caused by pinholes occurring at the intersections of gate lines and drain lines, and to improve the yield of FETs.

Structure of the Invention The present invention provides a structure in which a gate line insulating layer and a drain line are sequentially laminated on an insulating substrate.
The entire board is immersed in an electrolytic solution, the gate line is set to a positive potential, and the negative potential electrode is immersed in the solution. If there is a pinhole between the gate and drain line, a current is passed through it, and the pinhole is set as an anode. It is oxidized to transform it into an insulating oxide, which closes the pinholes.

Example FIG. 4A shows a gate with a pinhole 8.
A cross section between drain lines is shown, where 5 is an insulating substrate such as glass, X is an insulating layer for gate line 7, and Y is an insulating layer.
has a drain line, such a pinhole 8
The FET is immersed together with its substrate in an electrolytic solution, the gate line X is connected to a positive potential terminal, and the negative potential terminal is immersed in this electrolytic solution. As a result, a current flows between the gate line X and the drain line Y through the pinhole 8, and the surface of the drain line Y is oxidized. In this case, due to the resistance of the drain line Y, oxidation progresses from the part close to the pinhole 8, and eventually the pinhole 8 and its surroundings are covered with an insulator 9 produced by the oxidation of the gate. Insulation between the line X and the drain line Y is achieved. Once oxidation is complete, anodic oxidation is stopped. When aluminum is used as the material for the drain line Y, the insulator 9 becomes alumina Al ₂ O ₃ . In this way, the pinhole 8 is completely closed by the formation of the insulator 9 by anodic oxidation, and the insulation between the gate line X and drain line Y is completed. At this time, most of the remaining portion of the drain line Y is not oxidized and remains as it is, so that its function as a conductor is not impaired.

Effects of the invention Pinholes that occur between the gate line and drain line of the FET are completely blocked by the insulating oxide produced by anodic oxidation.
FET can be significantly reduced. This is particularly effective when used in liquid crystal display panels that have tens of thousands of gate line/drain line intersections, and where a few percent of defective FETs occur due to pinholes, contributing to improved FET yields. In addition, since the oxidation reaction continues to progress until the oxidation is completely completed and insulation is reliably performed, incomplete insulation treatment does not pose a problem in blocking pinholes due to anodic oxidation.

[Brief explanation of drawings]

FIG. 1 is an exploded perspective view showing the general configuration of a liquid crystal matrix panel, FIG. 2 is a partial circuit diagram thereof, FIG. 3 is a plan view showing a specific structure, and FIGS. 3A and 3B are The A-A' cross-sectional view, the B-B' cross-sectional view, FIG. 4A, and FIG. 4B in FIG. 3 are, respectively,
FIG. 2 is a sectional view for explaining an embodiment of the present invention. 1, 5...Transparent substrate, 2...Common electrode, 3...
Liquid crystal layer, 6... Display electrode, 7... Insulating layer, 8...
Pinhole, 9...insulator, X...gate line, Y...drain line.

Claims (1)

[Claims] 1. In a pinhole closing method for a power effect transistor having a gate line formed on an insulating substrate, and a drain line (or source line) formed through the gate line and an insulating layer, the oxide of which forms an insulator. Applying a positive potential to the gate line in an electrolytic solution in which a negative potential electrode is immersed, and passing a current through the pinhole existing between the gate line and the drain line (or source line),
A method for closing a pinhole in a field effect transistor, the method comprising anodizing the drain line (or source line) in the pinhole portion to produce an insulating oxide, thereby closing the pinhole.